DETAILED ACTION
This action is responsive to the following communications: the Application filed February 07, 2024, and Information Disclosure Statement filed on February 07, 2024.
Claims 1-10 are pending. Claims 1 and 6 are independent.
Information Disclosure Statement
Acknowledged is made of Application’s Information Disclosure Statement (IDS) Form PTO-1449 filed on February 07, 2024. This IDS has been considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the recitation “the test results” in line 6 is considered indefinite because it does not have an antecedent basis.
Regarding claim 1, the term “a fail I/O” in line 8 should be “a fail input/output (I/O).
Regarding claim 2, the recitation “the fail I/O value” in 7 is considered indefinite because it does not have antecedent basis.
Regarding claim 3, the recitation “the peripheral circuit” in lines 5 and 6 is considered indefinite because it does not have an antecedent basis.
Regarding claim 6, the recitation “the test results” in lines 4 and 5 is considered indefinite because it does not have an antecedent basis.
Regarding claim 6, the term “a fail I/O” in line 6 should be “a fail input/output (I/O).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carnevale et al. (US 2010/0174955) in view of Ogushi (US 11,288,435).
Regarding independent claim 1, Carnevale et al. disclose a failure analysis device for analyzing a failure of a semiconductor device (figures 1 and 4) having a logic circuit (TEST LOGIC, figures 1and 2) and a memory circuit (100, figure 1), comprising: a storage device for storing fail bit data obtained by testing the memory circuit, and failure diagnosis data obtained by failure diagnosis for the test results of the logic circuit (see figure 1 and paragraphs below).
Abstract
A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
[0008] An additional exemplary embodiment is a design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a configured command sequencer to launch an architected command to a target device configurable between local execution of the architected command at a memory hub device and remote execution at one or more of: a downstream memory hub device and an upstream memory hub device. The design structure further includes and configuration registers to hold fault and diagnostic information, and to initiate one or more tests.
Claims
1. A memory hub device with test logic, the memory hub device configured to communicate with memory devices via multiple hub device ports and configured to communicate on one or more busses in an upstream and downstream direction, the test logic comprising: a built-in self test (MBIST) apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns; and configuration registers to hold fault and diagnostic information, and to initiate one or more tests.
However, Carnevale et al. are silent with respect to wherein the processor extracts a fail I/O from the fail bit data and extracts data of a memory connection port which is a connection port to the memory circuit from an estimated failure part included in the failure diagnosis data, and determines whether the fail I/O and a port ID included in the data of the memory connection port match or not
Ogushi discloses wherein the processor extracts a fail I/O from the fail bit data and extracts data of a memory (The processor converts logical addresses and I/O value of a fail bit obtained by testing the memory circuit into physical addresses using predetermined arithmetic expressions, and converts the physical addresses into physical coordinate values using the size values of the memory cell, the size values of the peripheral circuit, and the arrangement spacing values of the peripheral circuit) connection port which is a connection port to the memory circuit (see figure 1 below) from an estimated failure part included in the failure diagnosis data, and determines whether the fail I/O and a port ID included in the data of the memory connection port match or not (see para.(65) discloses: As described above, by using the method of the first embodiment, it is typically possible to improve the efficiency of the failure analysis. Specifically, since the exact location of the fail bit can be calculated, it is possible to improve the efficiency of the physical analysis on the fail bit in particular. Further, by using the display device 330 to indicate the exact location of the fail bit on the layout of the semiconductor device, the visual effect may allow efficient estimation of the cause of the failure. Furthermore, since the failure analysis can be performed using the general layout tool 328, the user's operability can be improved)
PNG
media_image1.png
562
802
media_image1.png
Greyscale
Since Carnevale et al. and Ogushi are both from the same field of endeavor, the purpose disclosed by Ogushi would have been recognized in the pertinent art of Carnevale et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Carnevale et al. to teaching of Ogushi for purpose of using processor to converts logical address.
Regarding independent claim 6, Carnevale et al. disclose a failure analysis method of a semiconductor device with a logic circuit and a memory circuit: obtains a fail bit data by a test of the memory circuit, and the failure diagnosis data by failure diagnosis for the test results of the logic circuit stored in the storage device (ABSTRACT discloses A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features, also see figure 1 below) extracts a fail I/O from the fail bit data, extracts data of the memory connection port which is a connection port to the memory circuit from an estimated failure part included in the failure diagnosis data, determines whether the fail I/O and a port ID included in the data of the memory connection port match or not (see rejection of claim 1).
PNG
media_image2.png
812
804
media_image2.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH D DINH whose telephone number is (571)270-5375. The examiner can normally be reached Monday to Friday 8:00am 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MINH D DINH/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827