Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 20 May 2026 has been entered.
Response to Amendment
The amendment filed 20 May, 2026 has been entered. Claims 1-4 and 6-22 remain pending in the application. Examiner acknowledges amendments to the claims and persuasive arguments which have overcome the rejections of claims 1 and 8 previously set forth in the Office Action mailed 20 February, 2026. Rejection of claim 15 and its dependents is updated and new rejections under 35 U.S.C. § 112 have been raised.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5 June 2026 and 17 July 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-4 and 6-22 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations “based on the first messages being the control messages” in line 14, and “based on the second messages being the data messages” in line 17. This language is unclear because the first messages as claimed must comprise control messages and the second messages as claimed must comprise data messages, so the step of determining the content of the messages implied by the phrase “based on” would never need to occur. Therefore, the claim is not further limited by this recitation. Applicant is recommended to simply remove these specific limitations to address the rejection and maintain claim scope.
Claims 2-4, 6-7, and 21-22 depend from claim 1 and are therefore seen to contain the same deficiencies.
Claim 8 recites the limitations “based on the first messages being the control messages” in line 11, and “based on the second messages being the data messages” in line 14. This language is unclear because the first messages as claimed must comprise control messages and the second messages as claimed must comprise data messages, so the step of determining the content of the messages implied by the phrase “based on” would never need to occur. Therefore, the claim is not further limited by this recitation. Applicant is recommended to simply remove these specific limitations to address the rejection and maintain claim scope.
Claims 9-14 depend from claim 8 and are therefore seen to contain the same deficiencies.
Claim 15 recites the limitations "the first messages" in line 8 and “the second messages” in line 12. There is insufficient antecedent basis for these limitations in the claim.
Claims 16-20 depend from claim 15 and are therefore seen to contain the same deficiencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Subbarao et al. (US 2020/0409855) (hereafter Subbarao), in view of Farhan et al. (US 11,360,708) (hereafter Farhan), Bolkhovitin et al (U.S. Patent Pub. No. 2018/0341606), hereinafter referred to as Bolkhovitin, and Tong et al (Chinese Patent CN-101833989-A), hereinafter referred to as Tong.
As per claim 15, Subbarao teaches an apparatus, comprising:
a first interface (fig. 8, network interface device; [0117] system 500 may be host having a memory subsystem);
a second interface (fig. 1, memory subsystem 110 connected to host 120);
a memory (fig. 1, 119);
a storage device (fig. 1, devices 102-104); and
a logic circuit (fig. 1, 115) configured to:
receive, among messages received in the second interface to access the storage device,
control and data messages ([0031] wherein in order to perform the commands, i.e. read, write, etc.);
buffer first messages in the memory for processing by a system connected to the first interface ([0040] wherein the commands received from the host are buffered into the queues).
Subbarao does not explicitly teach that the first and second interfaces are configured to connect to different host systems, nor does it teach a logic circuit configured to identify, among messages received in the second interface to access the storage device, second messages; and provide the second messages to the storage device for processing without the second messages being buffered in the memory.
However, Farhan teaches that the first and second interfaces are configured to connect to different host systems. Farhan Column 8, lines 4-20 disclose that a host system is any device comprising a processor and connected to a storage device, either over a cable or bus or through a network connection. Fig. 7 shows a compute service provider with storage devices 721 connected directly to a host 716 which is then connected to a local area network 730 as well as a wide area network 740 linked to other hosts, e.g. an apparatus comprising at least two interfaces each utilized to communicate with internal and external host systems. Farhan Column 18, lines 1-24 additionally disclose that the host 716 may provide the disclosed storage system to other hosts over the network, achieving the claimed limitation.
Farhan also teaches a logic circuit configured to receive second messages; and provide the second messages to the storage device for processing without the second messages being buffered in the memory (col. 3, lines 61-col. 4, lines 20, wherein the second commands are high priority or commands when the processing load is low).
The combination of Subbarao and Farhan teaches wherein the first messages are control messages in accessing the storage device ([Subbarao- 0023] describing the reading, writing and erase commands); and the second messages are data messages in accessing the storage device (Farhan- col. 3, lines 61-col. 4, lines 20, wherein the second commands are high priority data access commands).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the second message of Farhan with the first messages of Subbarao because it allows for high priority commands to be processed more quickly and/or prevents unnecessary buffering when it is not necessary (col. 4, lines 10-20).
Additionally, Bolkhovitin teaches a memory subsystem having a controller with two interfaces, each for networked host access (Fig. 4F process for access (host memory buffers are accessible to one host system, but a combination with Farhan would make it obvious to one of ordinary skill in the art to access different systems); Fig. 1B shows data storage subsystem having controller 110). Implementing the main controller of Bolkhovitin as the "internal" host or integrating it with the memory controller(s) of the combination of previously cited references would then also achieve the claimed limitation, providing external hosts with full access to the apparatus over separate interfaces. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Bolkhovitin in order to directly connect to multiple hosts and improve the performance of non-volatile memory storage (¶ 0006, lines 1-2).
The previously cited references do not explicitly teach multiple interfaces connecting directly to different hosts, however Tong teaches a storage apparatus having several interfaces for direct host connection. The original Figures of Tong, particularly Fig. 6, show an SSD with multiple interfaces directly connected to external hosts. In the translated copy of the reference, ¶ 0006, 0018, 0021, 0038, and further discuss directly connecting hosts to the storage device as opposed to indirectly. While the translated resource is not of perfect clarity, a person having ordinary skill in the art could easily arrive at the claimed limitations based on the disclosure and figures. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Tong to address lower performance and higher latency from indirectly accessing storage devices (¶ 0004) by providing direct connections to several hosts (¶ 0006), achieving the claimed limitation.
As per claim 16, Subbarao teaches wherein the second interface is a network interface (fig. 8 network interface device 508) and Farhan Column 18, lines 1-24 additionally disclose that the host 716 may provide the disclosed storage system to other hosts over the network, achieving the claimed limitation in combination.
As per claim 17, Subbarao teaches wherein the first interface is a host interface (fig. 1 interfacing with host).
As per claim 18, Subbarao teaches wherein the storage device includes a memory device having a plurality of memory cells configured on at least one integrated circuit die ([0023]).
As per claim 19, Subbarao teaches wherein the storage device further includes a local memory and a processing device (fig. 1).
As per claim 20, Subbarao teaches: an interconnect configured to connect the memory, the storage device, the logic circuit, the network interface, and the host interface (see fig. 8, 530 bus).
Allowable Subject Matter
Claims 1-4, 6-14, and 21-22 would be allowable if amended to address rejections under 35 U.S.C. § 112.
Claims 1 and 8 include the limitations of (claim 8) a method, comprising: communicating, via a first interface of an apparatus directly connected to a first host system, with the first host system outside of the apparatus; receiving, from a second host system in a second interface of an apparatus directly connected to the second host system, messages to access storage; identifying, among the messages received in the second interface, first messages comprising control messages configured to exercise access control, security control, or perform administrative or management operations; and second messages comprising data messages configured to read data from or write data to the storage device; buffering, based on the first messages being the control messages, the first messages in a memory of the apparatus for processing by the first host system connected to the first interface; and providing, based on the second messages being the data messages, the second messages for processing without the second messages being buffered in the memory of the apparatus. No prior art reference taken alone or in combination was found to teach the entirety of the claimed limitations. Specifically, buffering first messages comprising control messages (of specified types) for processing by a host connected to an interface was not found to be sufficiently taught by prior art. Reference Tiwari et al (U.S. Patent Pub. No. 2022/0100422) teaches selectively buffering certain control messages in volatile memory (¶ 0073-0074), but does not include the specified types and does not include a direct interface with two hosts or motivation to include such a limitation. As such, the claims are allowed.
Claims 2-4, 6-7, and 21-22 would be allowable by virtue of dependence on allowable claim 1.
Claims 9-14 would be allowable by virtue of dependence on allowable claim 8.
Response to Arguments
Applicant’s arguments (see remarks filed 20 May 2026) with respect to amended claims 1 and 8 and their dependents under 35 U.S.C. 103 have been considered and are persuasive. However, amendments have presented issues under 35 U.S.C. § 112 which must be addressed prior to allowance.
Amended claim 15 is now additionally rejected under 35 U.S.C. § 112 and the rejection under 35 U.S.C. § 103 has been updated to better match the claim language, but claim 15 would be allowable if amended to include all of the limitations of allowed claims 1 or 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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