Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 29 January, 2026 has been entered. Claims 1-22 remain pending in the application. Examiner acknowledges amendments to the claims, which upon further search and consideration have been rejected under 35 U.S.C. § 103.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 30 January 2026 and 13 February 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Subbarao et al. (US 2020/0409855) (hereafter Subbarao), in view of Farhan et al. (US 11,360,708) (hereafter Farhan), Bolkhovitin et al (U.S. Patent Pub. No. 2018/0341606), hereinafter referred to as Bolkhovitin, and Tong et al (Chinese Patent CN-101833989-A), hereinafter referred to as Tong.
As per claims 1, 8 and 15, Subbarao teaches an apparatus, comprising:
a first interface (fig. 8, network interface device; [0117] system 500 may be host having a memory subsystem);
a second interface (fig. 1, memory subsystem 110 connected to host 120);
a memory (fig. 1, 119);
a storage device (fig. 1, devices 102-104); and
a logic circuit (fig. 1, 115) configured to:
identify, among messages received in the second interface to access the storage device,
first messages ([0031] wherein in order to perform the commands, i.e. read, write, etc.);
buffer the first messages in the memory for processing by a system connected to the first interface ([0040] wherein the commands received from the host are buffered into the queues).
Subbarao does not explicitly teach that the first and second interfaces are configured to connect to different host systems, nor does it teach a logic circuit configured to identify, among messages received in the second interface to access the storage device, second messages; and provide the second messages to the storage device for processing without the second messages being buffered in the memory.
However, Farhan teaches that the first and second interfaces are configured to connect to different host systems. Farhan Column 8, lines 4-20 disclose that a host system is any device comprising a processor and connected to a storage device, either over a cable or bus or through a network connection. Fig. 7 shows a compute service provider with storage devices 721 connected directly to a host 716 which is then connected to a local area network 730 as well as a wide area network 740 linked to other hosts, e.g. an apparatus comprising at least two interfaces each utilized to communicate with internal and external host systems. Farhan Column 18, lines 1-24 additionally disclose that the host 716 may provide the disclosed storage system to other hosts over the network, achieving the claimed limitation.
Farhan also teaches a logic circuit configured to identify, among messages received in the second interface to access the storage device, second messages; and provide the second messages to the storage device for processing without the second messages being buffered in the memory (col. 3, lines 61-col. 4, lines 20, wherein the second commands are high priority or commands when the processing load is low).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the second message of Farhan with the first messages of Subbarao because it allows for high priority commands to be processed more quickly and/or prevents unnecessary buffering when it is not necessary (col. 4, lines 10-20).
Additionally, Bolkhovitin teaches a memory subsystem having a controller with two interfaces, each for networked host access (Fig. 4F process for access (host memory buffers are accessible to one host system, but a combination with Farhan would make it obvious to one of ordinary skill in the art to access different systems); Fig. 1B shows data storage subsystem having controller 110). Implementing the main controller of Bolkhovitin as the "internal" host or integrating it with the memory controller(s) of the combination of previously cited references would then also achieve the claimed limitation, providing external hosts with full access to the apparatus over separate interfaces. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Bolkhovitin in order to directly connect to multiple hosts and improve the performance of non-volatile memory storage (¶ 0006, lines 1-2).
The previously cited references do not explicitly teach multiple interfaces connecting directly to different hosts, however Tong teaches a storage apparatus having several interfaces for direct host connection. The original Figures of Tong, particularly Fig. 6, show an SSD with multiple interfaces directly connected to external hosts. In the translated copy of the reference, ¶ 0006, 0018, 0021, 0038, and further discuss directly connecting hosts to the storage device as opposed to indirectly. While the translated resource is not of perfect clarity, a person having ordinary skill in the art could easily arrive at the claimed limitations based on the disclosure and figures. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Tong to address lower performance and higher latency from indirectly accessing storage devices (¶ 0004) by providing direct connections to several hosts (¶ 0006), achieving the claimed limitation.
As per claims 2, 10 and 16, Subbarao teaches wherein the second interface is a network interface (fig. 8 network interface device 508) and Farhan Column 18, lines 1-24 additionally disclose that the host 716 may provide the disclosed storage system to other hosts over the network, achieving the claimed limitation in combination.
As per claims 3, 9 and 17, Subbarao teaches wherein the first interface is a host interface (fig. 1 interfacing with host).
As per claims 4 and 11, Subbarao teaches wherein the host interface is operable on a computer memory bus connected to a microprocessor ([0022] describes wherein the host interface is connected to the microprocessor).
As per claims 5 and 12, the combination of Subbarao and Farhan teaches wherein the first messages are control messages in accessing the storage device ([Subbarao- 0023] describing the reading, writing and erase commands); and the second messages are data messages in accessing the storage device (Farhan- col. 3, lines 61-col. 4, lines 20, wherein the second commands are high priority data access commands).
As per claim 6, Subbarao teaches wherein the storage device is a solid-state drive ([0017]).
As per claims 7, 14 and 18, Subbarao teaches wherein the storage device includes a memory device having a plurality of memory cells configured on at least one integrated circuit die ([0023]).
As per claim 13, the combination of Subbarao and Farhan teaches providing a storage capacity via a storage device of the apparatus (Subbarao, fig. 3 wherein the storage capacity is the media and/or namespaces; also see fig. 2; [0048] discloses implementing fig. 3 in the memory subsystem of figs. 1 and 2), the first messages and the second messages configured to access the storage capacity (Subbarao teaches wherein the operations are write, read and erasing of data within the storage capacity and Farhan teaches wherein the commands are data access commands accessing a storage capacity).
As per claim 19, Subbarao teaches wherein the storage device further includes a local memory and a processing device (fig. 1).
As per claim 20, Subbarao teaches: an interconnect configured to connect the memory, the storage device, the logic circuit, the network interface, and the host interface (see fig. 8, 530 bus).
As for claim 21, the previously cited references teach the apparatus of claim 1. Additionally, Farhan teaches wherein the first host system is external to the apparatus and is configured to externally control the storage device. Farhan Column 18, lines 1-24 disclose that the host 716 may provide the disclosed storage system to other hosts over the network, achieving the claimed limitation.
As for claim 22, the previously cited references teach the apparatus of claim 21. Additionally, Farhan teaches wherein the second host system is external to the apparatus. Farhan Column 18, lines 1-24 disclose that the host 716 may provide the disclosed storage system to other hosts simultaneously over a local area network and over a wide area network. If an apparatus is interpreted to include; the first host 716 in Fig. 7 and its storage service provided by devices 721, the local area network 730 (i.e. first interface), and wide area network 740 (i.e. second interface); the claimed limitation is achieved.
Response to Arguments
Applicant’s arguments (see remarks filed 29 January, 2026) with respect to claims 1, 8, and 15 and their dependents under 35 U.S.C. 103 have been considered but are moot because the new ground of rejection to address the added limitations in the independent claims does not rely on any reference applied in the prior rejection of record for the claims for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139