Prosecution Insights
Last updated: October 02, 2026
Application No. 18/435,628

UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY

Non-Final OA §102§103
Filed
Feb 07, 2024
Priority
Dec 15, 2016 — continuation of 9905527 +4 more
Examiner
PARKER, JOHN M
Art Unit
2800
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lodestar Licensing Group LLC
OA Round
2 (Non-Final)
92%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
791 granted / 859 resolved
+24.1% vs TC avg
Minimal +1% lift
Without
With
+0.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
21 currently pending
Career history
874
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
45.3%
+5.3% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 859 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Terminal Disclaimer The terminal disclaimer filed on 18 May 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 9,905,527 has been reviewed and is accepted. The terminal disclaimer has been recorded. Double Patenting Previous double patenting rejections are now withdrawn. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 11 and 16-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cate et al. (US Pat. #9,324,557). Regarding claim 11, Cate teaches an apparatus, comprising: A first semiconductor die having a first region and a second region discrete from the first region [fig. 1, first die 102, first region with 106W, second region with 106N]; A plurality of first pillars extending from the first region of the first semiconductor die toward a second semiconductor die [fig. 1, 108 in region containing 106W, second die 104]; and A plurality of second pillars, wherein a minimum lateral spacing between the plurality of first pillars is different than a minimum lateral spacing between the plurality of second pillars, or an average height of the plurality of second pillars is less than an average height of the plurality of first pillars [fig. 1, 106N has a different spacing between the pillars than 106W]. Regarding claim 16, Cate discloses the apparatus of claim 11, further comprising volumes of solder respectively disposed between the respective plurality of first pillars and the second semiconductor die [fig. 1, solder 110w between pillars 108 and second die 104]. Regarding claim 17, Cate teaches the apparatus of claim 11, further comprising: A plurality of third pillars, wherein a minimum lateral spacing between the plurality of second pillars and the plurality of first pillars is less than a minimum lateral spacing between the plurality of third pillars and the plurality of first pillars [claim 1, there are three sets of pillars with three widths (diameters) disclosed, if the second diameter is greater than the first, and the third is greater than the second, then the first pillars of Cate can be the first pillars as claimed, the third pillars of Cate can be the second pillars as claimed an the second pillars of Cate can be the third pillars as claimed, giving a minimum lateral spacing between the second pillars and the first pillars is less than the minimum lateral spacing between the third pillars and the first pillars]. Regarding claim 18, Cate discloses the apparatus of claim 17, wherein an average width from a first side to a second side of each respective third pillar of the plurality of third pillars is less than an average width from the first side to the second side of each respective second pillar of the plurality of second pillars [claim 1, the third pillars of cate are the second pillars as claimed and the second pillars of cate are the third pillars as claimed, the average width of the third pillar is less than the average width of the second]. Claim(s) 11, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kwon et al. (US Pat. Pub. 2016/0005707). Regarding claim 11, Cate teaches an apparatus, comprising: A first semiconductor die having a first region and a second region discrete from the first region [fig. 1, first die 200, first region with 320 and 330, second region with 310 and 311]; A plurality of first pillars extending from the first region of the first semiconductor die toward a second semiconductor die [fig. 1, first pillars 320 and 330 extending towards second die 100]; and A plurality of second pillars, wherein a minimum lateral spacing between the plurality of first pillars is different than a minimum lateral spacing between the plurality of second pillars, or an average height of the plurality of second pillars is less than an average height of the plurality of first pillars [fig. 1, second pillars 310 and 311 with an average height less than the firs pillars 320 and 330]. Regarding claim 17, Kwon teaches the apparatus of claim 11, further comprising: A plurality of third pillars, wherein a minimum lateral spacing between the plurality of second pillars and the plurality of first pillars is less than a minimum lateral spacing between the plurality of third pillars and the plurality of first pillars [fig. 10, third pillars 730, spacing between second pillars 310/311 and first pillars 320/330 is less than the spacing between 320/330 and 730]. Regarding claim 19, Kwon discloses the apparatus of claim 17, wherein an average height of the plurality of third pillars is less than the average height of the plurality of second pillars [fig. 10, 730 is shorter than 310/311]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 12, 14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cate as applied to claims 11 and 16-18 above, and further in view of the following arguments. Regarding claim 12, while Cate teaches different widths for the pillars and demonstrates different lateral spacing between the pillars [fig. 1, spacing between 108 in 106W vs 108 in 106N], they fail to teach the minimum lateral spacing is different by a least 5%. However, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization to achieve desired number of different width pillars while ensuring they have equal heights [Cate, summary of invention paragraphs]. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B). Regarding claim 14, white Cate teaches the first pillar and second pillars have different average widths (diameters) [fig. 1, pillars 108 in 106W vs pillars 108 in 106N], they fail to specifically teach the different is at most 3%. However, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization to achieve desired number of different width pillars while ensuring they have equal heights [Cate, summary of invention paragraphs]. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B). Regarding claim 20, white Cate teaches the second pillar and third pillars have different average widths (diameters) [claim 1], they fail to specifically teach the minimum lateral spacing between the second pillars is differetn than the laterals pacing ebtween the third pillars is at least 10% However, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization to achieve desired number of different width pillars while ensuring they have equal heights [Cate, summary of invention paragraphs]. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon as applied to claims 11, 17 and 19 above, and further in view of the following arguments. Regarding claim 13, while Kwon teaches different heights for the pillars and demonstrates different lateral spacing between the pillars [fig. 1, height difference between 310/311 and 320/330 ], they fail to teach the average height of the second pillars is less than the average height of the first pillars by 10% However, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization to achieve desired mechanical and electrical reliability by providing sufficient gap space between dies [paragraph [0008]]. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B). Allowable Subject Matter Claims 1-10 are allowed. Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a plurality of second pillars extending from the second region of the first semiconductor die toward the second semiconductor die, wherein the plurality of second pillars are electrically isolated from one or both of the first semiconductor die or second semiconductor die, and wherein a minimum lateral spacing between the plurality of first pillars is different than a minimum lateral spacing between the plurality of second pillars. Regarding claim 6, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a plurality of second pillars extending from the second region of the first semiconductor die toward the second semiconductor die, wherein the plurality of second pillars are electrically isolated from one or both of the first semiconductor die or the second semiconductor die, and wherein an average width from a first side to a second side of each respective first pillar of the plurality of first pillars is different than an average width from a first side to a second side of each respective second pillar of the plurality of second pillars. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN M PARKER/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Feb 07, 2024
Application Filed
Dec 13, 2025
Non-Final Rejection (signed) — §102, §103
Feb 25, 2026
Non-Final Rejection mailed — §102, §103
May 18, 2026
Response Filed
Sep 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
92%
Grant Probability
93%
With Interview (+0.9%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 859 resolved cases by this examiner. Grant probability derived from career allowance rate.

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