DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-11, 17-18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20210073166), in view of Hwang (US 20190012281).
Regarding Claim 1, Jeon teaches
A system-on-chip comprising: a chip; plural components on the chip, the plural components configured to perform separate functions, separate calculations or separate operations; (Jeon [0003] A system on chip (SoC) is a semiconductor technology for integrating complicated multifunctional systems into a single chip. Intellectual Properties (hereinafter, IPs), which are provided in the SoC, may be designed to be effectively connected to one another through a system bus. [0043] the interconnect system 110 may include one or more master IPs or may include one or more slave IPs.)
and a bus on the chip configured to support data communication between the plural components on the chip according to a point-to-point interconnect protocol, (Jeon [0004] an interconnect system may be formed to include various functional blocks (e.g., an IP, an asynchronous bridge, a multiplexer, etc.). [0046] Regarding the connection technologies, the AXI is an interface protocol between IPs and provides a multiple outstanding address function and a data interleaving function.)
plural commands that are input through the bus, and a gating logic configured to arbitrate an order of processing the plural commands. (Jeon [0057] The first slave clock controller 122_1 may perform the clock gating in response to the clock on/off command CLK On/Off and provide the master clock controller 121 with the clock acknowledgement ACK On/Off indicating that the clock gating has been completed. [0063] each of the clock controllers may include at least one selected from among an oscillator, a phase-locked loop, a multiplexer, a divider, and a gate.)
Jeon does not teach wherein at least one component of the plural components on the chip is arranged between the bus and a volatile memory device on the chip, and wherein the at least one component on the chip comprises: plural memory interfaces configured to access the volatile memory device in an n-way interleaving way, 'n' being a positive integer equal to or greater than 2, to support performing in parallel memory operations of reading and writing; at least one slave intellectual property (IP) core which is arranged between the bus and the plural memory interfaces, and configured to distribute and transmit, to the plural memory interfaces accessing the volatile memory device, configured to arbitrate an order of processing the plural commands.
However, Hwang teaches wherein at least one component of the plural components on the chip is arranged between the bus and a volatile memory device on the chip, (Hwang [0031] FIG. 3 is a block diagram illustrating a master, a slave, and a bus of a SoC [0045] FIG. 3, there are a master 0 310, a master 1 311, a master 2 312, and a master 3 313, there are a slave 0 320, a slave 1 321, a slave 2 322, and a slave 3 323, there are a master port 0 330, a master port 1 331, a master port 2 332, and a master port 3 333, and there are a slave port 0 340, a slave port 1 341, a slave port 2 342, and a slave port 3 343. [0048] the bus 305 may connect M master ports and N slave ports. [0050] The internal memory 370 may be connected to C (C is a natural number, C≤N) slave ports that are selected among N slave ports according to the predetermined priority. [0053] The internal memory 370 may operate based on a memory clock. The internal memory 370 may be various types of memories according to embodiments. For example, the internal memory 370 may use a static random access memory (SRAM).) (i.e., slave is between bus and volatile memory of the SoC)
and wherein the at least one component on the chip comprises: plural memory interfaces configured to access the volatile memory device in an n-way interleaving way, 'n' being a positive integer equal to or greater than 2, to support performing in parallel memory operations of reading and writing; (Hwang [0075] the internal memory controller 570 may be connected to four slave ports. [0076] The memory time-sharing apparatus may apply C (C is a natural number)-way interleaved method)
at least one slave intellectual property (IP) core which is arranged between the bus and the plural memory interfaces, and configured to distribute and transmit, to the plural memory interfaces accessing the volatile memory device, (Hwang [0001] The present disclosure relates to a technology of distributing bus traffic of a system-on-chip)
configured to arbitrate an order of processing the plural commands. (Hwang [0004] FIG. 1 is a schematic block diagram of a general bus system of a SoC. Various components are broadly classified into a master and a slave. Referring to FIG. 1, the bus system may include a master 110, a slave 120, an arbiter 130)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 2, Jeon and Hwang teach
The system-on-chip according to claim 1, wherein: the at least one slave IP core is configured to operate according to a first clock, (Jeon [0006] The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.)
the plural memory interfaces are configured to operate according to a second clock, (Jeon [0128] a memory controller 640 are illustrated as the functional blocks that receive a clock signal CLK from a CMU 610.)
and the first and second clocks respectively have first and second frequencies different from each other. (Jeon [0066] The asynchronous bridge 230 may be provided to exchange data between functional blocks using different operating frequencies.)
the volatile memory device (Jeon [0042] The SoC 100 may include various types of IPs …. a volatile memory device)
Jeon does not teach but Hwang does not teach the volatile memory device includes a Static Random Access Memory (SRAM) cell (Hwang [0053] The internal memory 370 may operate based on a memory clock. The internal memory 370 may be various types of memories according to embodiments. For example, the internal memory 370 may use a static random access memory (SRAM).)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 3, Jeon and Hwang teach
Jeon does not teach but Hwang wherein the first frequency is higher than the second frequency. (Hwang [0014] time-sharing of an internal memory for distributing bus traffic by scaling a memory clock of the internal memory connected to a plurality of slave ports on a system-on-chip)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 7, Jeon and Hwang teach
The system-on-chip according to claim 1, wherein the at least one slave IP core comprises: a write module configured to sequentially transmit, to the plural memory interfaces, write commands and write data input through the bus and configured to output, to the plural components, responses corresponding to the write commands; (Jeon [0041] the interconnect system 110 may include at least a part of a system bus. Furthermore, when the SoC 100 has a hierarchical bus structure, the interconnect system 110 may include at least a part of a local data bus. [0043] slave IP may perform data communication based on control of the processing unit.)
and a read module configured to sequentially transmit, to the plural memory interfaces, read commands input through the bus and configured to output, to the plural components, read data corresponding to the read commands. (Jeon [0144] The CPU 721 may process or execute codes and/or data stored in the RAM 724. For example, the CPU 721 may process or execute the codes and/or the data in response to the operating clock output from the CMU 723. The CPU 721 may be implemented as a multi-core processor. The multi-core processor may be a single computing component having two or more independent substantial processors, and each of the processors may read and execute program instructions.)
Regarding Claim 8, Jeon and Hwang teach
Jeon teaches second number of the at least one slave IP core (Jeon [0043] the interconnect system 110 may include one or more slave IPs)
Jeon does not teach but Hwang teaches wherein a first number of the plural memory interfaces is twice a second number of the at least one slave IP core. (Hwang [0104] 2-way interleaved memory address map…slave may be allocated two address areas for a 2-way port.)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 9, Jeon and Hwang teach
Jeon teaches wherein the gating logic on the chip configured to perform at least one operation of: (Jeon [0056] Each of the slave clock controllers 122_1 to 122_n may perform a clock gating)
distributing and transferring, to the plural memory interfaces, the write commands and the write data transmitted from the write module, (Jeon [0041] the interconnect system 110 may include at least a part of a system bus. Furthermore, when the SoC 100 has a hierarchical bus structure, the interconnect system 110 may include at least a part of a local data bus. [0043] slave IP may perform data communication based on control of the processing unit.)
and collecting the read data transmitted from the plural memory interfaces to transfer the read data to the read module. (Jeon [0144] The CPU 721 may process or execute codes and/or data stored in the RAM 724. For example, the CPU 721 may process or execute the codes and/or the data in response to the operating clock output from the CMU 723. The CPU 721 may be implemented as a multi-core processor. The multi-core processor may be a single computing component having two or more independent substantial processors, and each of the processors may read and execute program instructions.)
Jeon does not teach but Hwang teaches distributing (Hwang [0001] The present disclosure relates to a technology of distributing bus traffic of a system-on-chip)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 10, Jeon and Hwang teach
Jeon teaches second number of the at least one slave IP core (Jeon [0043] the interconnect system 110 may include one or more slave IPs)
Jeon does not teach but Hwang teaches wherein a first number of the plural memory interfaces is four times a second number of the at least one slave IP core. (Hwang [0102] The memory time-sharing apparatus is configured in such a way that the five slave ports illustrated in FIGS. 8A and 8B are connected to the internal memory may variably select and use the 4-way interleaved memory address map and the 2-way interleaved memory address map.)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 11, Jeon and Hwang teach
Jeon teaches wherein the gating logic on the chip comprises (Jeon [0004] a clock signal may be provided to various functional blocks including the IPs, and the output of the clock signal may be controlled according to a gating operation based on an operating state of the SoC)
Jeon does not teach but Hwang teaches a first arbitration circuit configured to parallelly process the write commands and the write data; (Hwang [0004] the bus system may include a master 110, a slave 120, an arbiter 130, [0005] The master 110 may be a device that transmits a control signal, an address, data, and so on to the slave 120 and permits the slave 120 to perform an operation such as read and write. The slave 120 may be a device that has an address area and performs write, on the address area. The slave 120 may transmit a signal indicating a state of the slave 120 to the master 110.)
a first switching circuit configured to collect and transmit the responses to the plural components; (Hwang [0021] a multiplexer connected to the internal memory controller, and a memory unit connected to the multiplexer and configured to write data,)
a second arbitration circuit configured to parallelly process the read commands; (Hwang [0004] the bus system may include a master 110, a slave 120, an arbiter 130, [0005] The master 110 may be a device that transmits a control signal, an address, data, and so on to the slave 120 and permits the slave 120 to perform an operation such as read and write. The slave 120 may be a device that has an address area and performs read, on the address area. The slave 120 may transmit a signal indicating a state of the slave 120 to the master 110.)
and a second switching circuit configured to collect and transmit the read data to the read module. (Hwang [0073] [0073] The memory units 490 and 590 may each be a memory device that is capable of reading or writing data and may be connected to the multiplexers 480 and 580)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 17, Jeon teaches
A memory system comprising: (Jeon [0003] A system on chip (SoC) is a semiconductor technology for integrating complicated multifunctional systems into a single chip. Intellectual Properties (hereinafter, IPs), which are provided in the SoC, may be designed to be effectively connected to one another through a system bus. [0043] the interconnect system 110 may include one or more master IPs or may include one or more slave IPs.)
and a system-on-chip memory controller comprising: at least one slave intellectual property (IP) circuit on the chip which is arranged between a bus and the n number of volatile memories and configured to receive commands transferred through the bus; (Jeon [0043] the interconnect system 110 may include one or more master IPs or may include one or more slave IPs [0046] Regarding the connection technologies, the AXI is an interface protocol between IPs and provides a multiple outstanding address function and a data interleaving function.)
and a gating logic on the chip (Jeon [0063] each of the clock controllers may include at least one selected from among an oscillator, a phase-locked loop, a multiplexer, a divider, and a gate.)
Jeon does not teach n number of volatile memories on a chip, 'n' being a positive integer equal to or greater than 2; at least one slave intellectual property (IP) circuit on the chip which is arranged between a bus and the n number of volatile memories; and a gating logic on the chip which is arranged between the at least one slave intellectual property (IP) circuit and the n number of memories on the chip and configured to distribute and transmit the commands input from the at least one slave IP circuit to the n number of volatile memories for accessing the n number of volatile memories in an n-way interleaving manner.
However, Hwang teaches
n number of volatile memories on a chip, 'n' being a positive integer equal to or greater than 2; (Hwang [0075] the internal memory controller 570 may be connected to four slave ports. [0076] The memory time-sharing apparatus may apply C (C is a natural number)-way interleaved method)
at least one slave intellectual property (IP) circuit on the chip which is arranged between a bus and the n number of volatile memories; (Hwang [0031] FIG. 3 is a block diagram illustrating a master, a slave, and a bus of a SoC [0045] FIG. 3, there are a master 0 310, a master 1 311, a master 2 312, and a master 3 313, there are a slave 0 320, a slave 1 321, a slave 2 322, and a slave 3 323, there are a master port 0 330, a master port 1 331, a master port 2 332, and a master port 3 333, and there are a slave port 0 340, a slave port 1 341, a slave port 2 342, and a slave port 3 343. [0048] the bus 305 may connect M master ports and N slave ports. [0050] The internal memory 370 may be connected to C (C is a natural number, C≤N) slave ports that are selected among N slave ports according to the predetermined priority. [0053] The internal memory 370 may operate based on a memory clock. The internal memory 370 may be various types of memories according to embodiments. For example, the internal memory 370 may use a static random access memory (SRAM).) (i.e., slave is between bus and volatile memory of the SoC)
and a gating logic on the chip which is arranged between the at least one slave intellectual property (IP) circuit and the n number of memories on the chip and configured to distribute and transmit the commands input from the at least one slave IP circuit to the n number of volatile memories for accessing the n number of volatile memories in an n-way interleaving manner. (Hwang [0001] The present disclosure relates to a technology of distributing bus traffic of a system-on-chip [0075] the internal memory controller 570 may be connected to four slave ports. [0076] The memory time-sharing apparatus may apply C (C is a natural number)-way interleaved method)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 18, Jeon and Hwang teach
Jeon does not teach but Hwang teaches wherein each of the n number of volatile memories comprises: plural memory cells for storing data; a memory interface configured to access the plural memory cells; and a data path circuit coupled to the memory interface. (Hwang [0053] the internal memory 370 may use a static random access memory (SRAM). [0085] Referring to FIG. 7, the two address areas may be connected to two slave ports that are selected based on the predetermined priority. One of the two address areas and three slave port for time-sharing may be connected to an input to one of the two time-sharing may be connected to an input to one of the two multiplexers and outputs of the two multiplexers may be connected to two memory units, respectively.)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 20, Jeon and Hwang teach
The memory system according to claim 17, wherein: the at least one slave IP core and the gating logic are each configured to operate according to a first clock, (Jeon [0006] The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.)
the n number of volatile memories having a same data storage capacity are configured to operate according to a second clock, (Jeon [0042] The SoC 100 may include various types of IPs … a volatile memory device [0128] a memory controller 640 are illustrated as the functional blocks that receive a clock signal CLK from a CMU 610.)
and the first and second clocks respectively have first and second frequencies different from each other. (Jeon [0066] The asynchronous bridge 230 may be provided to exchange data between functional blocks using different operating frequencies.)
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20210073166), in view of Hwang (US 20190012281), further in view of Liu (US 20240364346).
Regarding Claim 4, Jeon and Hwang teach
Jeon teaches second number of the at least one slave IP core (Jeon [0043] the interconnect system 110 may include one or more slave IPs)
Jeon does not teach but Hwang teaches a first number of the plural memory interfaces
(Hwang [0021] B slaves connected to the N slave ports, respectively, where B is a natural number, and an internal memory controller connected to C slave ports that are selected according to predetermined priority among the N slave ports, where C is a natural number, and C≤N, a multiplexer connected to the internal memory controller, and a memory unit connected to the multiplexer and configured to write data,)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Jeon-Hwang does not teach a ratio of the first frequency to the second frequency depends on a ratio of
However, Liu teaches a ratio of the first frequency to the second frequency depends on a ratio of (Liu [0016] a clock frequency calculator is provided in silicon products, application specific circuits (ASIC), digital signal processors, programmable logic circuits, SoCs, or standard products. a clock frequency calculator provides very fine ratio-based frequency resolution [0017] The circuit is to determine a ratio of a first frequency of the reference clock signal to a second frequency)
Jeon, Hwang and Liu are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon, Hwang and Liu to modify the Jeon-Hwang‘s SOC system with Liu’s teaching of clock frequency calculation. The motivation for doing so would be to have (Liu [0016]) systems and methods of clock frequency calculation are used in modern high-speed and power-efficient data communication and processing systems.
Regarding Claim 5, Jeon, Hwang and Liu teach
Jeon does not teach but Hwang teaches wherein the first number is four times the second number. (Hwang [0102] select and use the 4-way interleaved memory address map)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 6, Jeon, Hwang and Liu teach
Jeon-Hwang teaches the second frequency (Jeon [0128] a memory controller 640 are illustrated as the functional blocks that receive a clock signal CLK from a CMU 610.)
Jeon- Hwang does not teach but Liu teaches is greater than or equal to a value obtained by: multiplying the first frequency by 2 to obtain a first multiplication value, multiplying the first multiplication value by the second number to obtain a second multiplication value, and dividing the second multiplication value by the first number. (Liu [0017] The circuit is to determine a ratio of a first frequency of the reference clock signal to a second frequency [0019] the circuit determines the ratio according to the following equation: Y(n)/(K+1)=(Q((X(n)−Y(n−1))+Y(n−1)))/(K+1)) (i.e., Liu teaches a formula for the calculation of frequency using a first frequency and a ratio)
Jeon, Hwang and Liu are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon, Hwang and Liu to modify the Jeon-Hwang‘s SOC system with Liu’s teaching of clock frequency calculation. The motivation for doing so would be to have (Liu [0016]) systems and methods of clock frequency calculation are used in modern high-speed and power-efficient data communication and processing systems.
Claim(s) 12-15, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20210073166), in view of Hwang (US 20190012281), further in view of Lu (US 20230240087).
Regarding Claim 12, Jeon teaches
A system-on-chip comprising: a chip; plural components on the chip, the plural components configured to perform separate functions, separate calculations or separate operations; (Jeon [0003] A system on chip (SoC) is a semiconductor technology for integrating complicated multifunctional systems into a single chip. Intellectual Properties (hereinafter, IPs), which are provided in the SoC, may be designed to be effectively connected to one another through a system bus. [0043] the interconnect system 110 may include one or more master IPs or may include one or more slave IPs.)
and a bus on the chip (Jeon [0004] an interconnect system may be formed to include various functional blocks (e.g., an IP, an asynchronous bridge, a multiplexer, etc.). [0046] Regarding the connection technologies, the AXI is an interface protocol between IPs and provides a multiple outstanding address function and a data interleaving function.)
[the SoC] comprising plural memory cells for storing data, the plural memory cells in [the SoC] comprising volatile memory cells; and [the SoC] comprising a logic or a circuit, configured to input or output the data to or from [the SoC] (Jeon [0042] The SoC 100 may include various types of IPs…a volatile memory device, a non-volatile memory, a memory controller, an input and output interface block)
Jeon does not teach comprising at least one slave intellectual property (IP) core which is arranged between the bus and the first area and;
However, Hwang teaches comprising at least one slave intellectual property (IP) core which is arranged between the bus and the first area; (Hwang [0031] FIG. 3 is a block diagram illustrating a master, a slave, and a bus of a SoC [0045] FIG. 3, there are a master 0 310, a master 1 311, a master 2 312, and a master 3 313, there are a slave 0 320, a slave 1 321, a slave 2 322, and a slave 3 323, there are a master port 0 330, a master port 1 331, a master port 2 332, and a master port 3 333, and there are a slave port 0 340, a slave port 1 341, a slave port 2 342, and a slave port 3 343. [0048] the bus 305 may connect M master ports and N slave ports. [0050] The internal memory 370 may be connected to C (C is a natural number, C≤N) slave ports that are selected among N slave ports according to the predetermined priority. [0053] The internal memory 370 may operate based on a memory clock. The internal memory 370 may be various types of memories according to embodiments. For example, the internal memory 370 may use a static random access memory (SRAM).) (i.e., slave is between bus and volatile memory of the SoC)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Jeon-Hwang does not teach
a first area comprising plural memory cells for storing data, the plural memory cells in the first area comprising volatile memory cells; and a second area comprising a logic or a circuit, configured to input or output the data to or from the first area, and wherein a planar size of the first area is 50 to 65 times a planar size of the second area.
However, Lu teaches
a first area comprising plural memory cells for storing data, the plural memory cells in the first area comprising volatile memory cells; (Lu FIG. 10 [0106] a SRAM circuit 1011B)
and a second area comprising a logic or a circuit, (Lu [0106] a logic circuit 1011A)
configured to input or output the data to or from the first area, and wherein a planar size of the first area is 50 to 65 times a planar size of the second area. (Lu [0007] logic circuit and SRAM circuit are two major circuit the combination of which approximately occupy around 90% of the AI chip size. [0109] In the another view of adding more devices, as shown in the right hand of FIG. 10, the area of SRAM circuit 1001B′ in the single monolithic die 1001′ can not only include more SRAM cells, but can also include additional major function blocks not in the conventional monolithic die 1011.) (i.e., in the right side of FIG. 10, additional SRAM 5.7X makes the SRAM 1001B′ area much bigger than Logic 1001A′ area)
The claimed invention differs from the prior art of record in that the relative sizes of the two areas are different. Applicant has provided no evidence that the relative size of the two portions provides any unexpected benefit. As discussed in MPEP 2144.04 (IV)(A), changes to size and shape are not considered to distinguish over the prior art the claimed invention either merely scales up the prior art process and does not perform differently from the prior art device In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) and Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984). Applicant has not provided any evidence that changing the size of a circuit, or that the specific relative sizes would result in different operation. Accordingly, the relative sizes of the circuit areas is considered to be a design choice and does not patentably distinguish over the prior art.
Jeon, Hwang and Lu are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon, Hwang and Lu to modify the Jeon-Hwang‘s SOC system having clock management with Lu’s teaching of semiconductor structure. The motivation for doing so would be to have (Lu [0002-0003]) semiconductor structure of SRAM or DRAM, a high performance computing SOC.
Regarding Claim 13, Jeon, Hwang and Lu teach
Jeon-Hwang does not teach but Lu teaches the plural memory cells are arranged in rows and columns, and each of the plural memory cells is a Static Random Access Memory (SRAM) cell. (Lu [0002] a plurality of static random access memory (SRAM) arrays [0009] When the word-line (WL) is enabled (i.e., a row is selected in an array) … the vertically-running bit-lines) (i.e., word-lines are the rows and bit-lines are the columns)
Jeon, Hwang and Lu are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon, Hwang and Lu to modify the Jeon-Hwang‘s SOC system having clock management with Lu’s teaching of semiconductor structure. The motivation for doing so would be to have (Lu [0002-0003]) semiconductor structure of SRAM or DRAM, a high performance computing SOC.
Regarding Claim 14, Jeon, Hwang and Lu teach
Jeon teaches wherein the logic or the circuit comprises: plural memory interfaces configured to access the plural memory cells in an n-way interleaving way, ‘n’ being a positive integer equal to or greater than 2; (Jeon [0042] The SoC 100 may include various types of IPs… a volatile memory device, a non-volatile memory, a memory controller, an input and output interface block [0128] The memory may be a functional block included in the interconnect system)
and at least one slave intellectual property (IP) core configured to distribute and transmit, to the plural memory interfaces, plural commands that are input through the bus. (Jeon [0040] The interconnect system 110 may include a master Intellectual Property (IP) and/or a slave IP. I [0131] bus 630 and the memory controller 640 corresponding to the slave functional blocks of the interconnect system.)
Jeon does not teach but Hwang teaches
in an n-way interleaving way, ‘n’ being a positive integer equal to or greater than 2; (Hwang [0075] the internal memory controller 570 may be connected to four slave ports. [0076] The memory time-sharing apparatus may apply C (C is a natural number)-way interleaved method)
distribute (Hwang [0001] The present disclosure relates to a technology of distributing bus traffic of a system-on-chip)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Regarding Claim 15, Jeon, Hwang and Lu teach
The system-on-chip according to claim 14, wherein: the at least one slave IP core is configured to operate according to a first clock, (Jeon [0006] The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.)
the plural memory interfaces are configured to operate according to a second clock, (Jeon [0128] a memory controller 640 are illustrated as the functional blocks that receive a clock signal CLK from a CMU 610.)
and the first and second clocks respectively have first and second frequencies different from each other. (Jeon [0066] The asynchronous bridge 230 may be provided to exchange data between functional blocks using different operating frequencies.)
Regarding Claim 19, Jeon and Hwang teach
Jeon does not teach but Hwang teaches wherein each of the plural memory cells is a Static Random Access Memory (SRAM) cell, (Hwang [0053] the internal memory 370 may use a static random access memory (SRAM).)
Jeon and Hwang are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon and Hwang to modify the Jeon‘s SOC system having clock management with Hwang’s teaching of distributing bus traffic by scaling memory clock. The motivation for doing so would be to have (Hwang [0001) a technology of distributing bus traffic of a system-on-chip.
Jeon-Hwang does not teach and wherein a planar size occupied by the plural memory cells accounts for 98 to 98.5% of a total planar size of the memory system.
However, Lu teaches a planar size occupied by the plural memory cells accounts for 98 to 98.5% of a total planar size of the memory system. (Lu [0007] logic circuit and SRAM circuit are two major circuit the combination of which approximately occupy around 90% of the AI chip size. [0109] In the another view of adding more devices, as shown in the right hand of FIG. 10, the area of SRAM circuit 1001B′ in the single monolithic die 1001′ can not only include more SRAM cells, but can also include additional major function blocks not in the conventional monolithic die 1011.) (i.e., in the right side of FIG. 10, additional SRAM 5.7X makes the SRAM 1001B′ area much bigger than Logic 1001A′ area)
The claimed invention differs from the prior art of record in that the relative sizes of the two areas are different. Applicant has provided no evidence that the relative size of the two portions provides any unexpected benefit. As discussed in MPEP 2144.04 (IV)(A), changes to size and shape are not considered to distinguish over the prior art the claimed invention either merely scales up the prior art process and does not perform differently from the prior art device In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) and Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984). Applicant has not provided any evidence that changing the size of a circuit, or that the specific relative sizes would result in different operation. Accordingly, the relative sizes of the circuit areas is considered to be a design choice and does not patentably distinguish over the prior art.
Jeon, Hwang and Lu are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon, Hwang and Lu to modify the Jeon-Hwang‘s SOC system with Lu’s teaching of semiconductor structure. The motivation for doing so would be to have (Lu [0002-0003]) semiconductor structure of SRAM or DRAM, a high performance computing SOC.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20210073166), in view of Hwang (US 20190012281), further in view of Lu (US 20230240087), further in view of Liu (US 20240364346).
Regarding Claim 16, Jeon, Hwang and Lu teach
Jeon-Hwang-Lu teaches a number of the at least one slave IP core is m, where m is a positive integer, (Jeon [0043] include one or more slave Ips)
and the second frequency (Jeon [0128] a memory controller 640 are illustrated as the functional blocks that receive a clock signal CLK from a CMU 610.)
Jeon-Hwang-Lu does not teach greater than or equal to a value obtained by: multiplying the first frequency by 2 to obtain a multiplication value, and multiplying the multiplication value by m/n.
However, Liu teaches greater than or equal to a value obtained by: multiplying the first frequency by 2 to obtain a multiplication value, and multiplying the multiplication value by m/n. (Liu [0017] The circuit is to determine a ratio of a first frequency of the reference clock signal to a second frequency [0019] the circuit determines the ratio according to the following equation: Y(n)/(K+1)=(Q((X(n)−Y(n−1))+Y(n−1)))/(K+1)) (i.e., Liu teaches a formula for the calculation of frequency using a first frequency and a ratio)
Jeon, Hwang, Lu and Liu are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jeon, Hwang, Lu and Liu to modify the Jeon-Hwang-Lu‘s SOC system with Liu’s teaching of clock frequency calculation. The motivation for doing so would be to have (Liu [0016]) systems and methods of clock frequency calculation are used in modern high-speed and power-efficient data communication and processing systems.
Response to Arguments
Applicant's arguments filed 02/24/2026 have been fully considered.
The amended limitations are addressed in new rejection based on the amendment.
First, for claim 1, Applicant argued that cited references do not teach limitation of slave IP core arranged between the bus and the volatile memory. The Office disagrees.
The Office submits that Jeon teaches SoC with slave IP cores. Jeon does not teach but Hwang teaches slave IP is arranged between bus and volatile memory. The combination of Jeon and Hwang teaches the amended limitation of claim 1. Please see office action for details.
Next, for claim 12, Applicant argued as cited references do not teach limitation of slave IP core arranged between the bus and the volatile memory and input or output the data to or from the first area comprising the plural memory cells. The Office disagrees.
The Office submits that Jeon teaches SoC with slave IP cores. Jeon does not teach but Hwang teaches slave IP is arranged between bus and volatile memory. Jeon-Hwang teaches SoC with slave IP cores and SoC includes volatile memory, memory controller, and input and output interface block. Jeon-Hwang does not teach but Lu teaches a first area comprising volatile memory and a second area comprising logic circuit. The combination of Jeon, Hwang and Lu teaches the limitations of claim 12.
Next, for claim 17, Applicant argued as similar to claim 1.
Applicant’s arguments for dependent claims are based on their respective base independent claim 1, 12 and 17, which are addressed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WEI MA/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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