DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of claims 1-18 in the reply filed on 8/13/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claim(s) 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species and device/method claim, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US publication 2020/0168572 A1), hereinafter referred to as Lin572.
Regarding claim 1, Lin572 teaches a semiconductor package (fig. 8 and related text) comprising: an interposer (A+B, examiner markup below) including a power distribution structure (A, examiner markup below), and a redistribution structure (B, examiner markup below) on the power distribution structure; a first semiconductor die (110, [0045]) on the interposer; and a second semiconductor die (210, [0045]) on the interposer, wherein the power distribution structure includes: a power distribution module (310, power management integrated circuit (PMIC), [0087]) connected to a bottom surface of the redistribution structure (fig. 8); a plurality of conductive posts (322, [0055]) connected to the bottom surface of the redistribution structure (fig. 8); and a molding material (320, [0054]) molding the power distribution module and the plurality of conductive posts (fig. 8).
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Regarding claim 2, Lin572 teaches wherein the power distribution module includes at least one of a controller, a buck converter, a capacitor, a resistor, and an inductor (power management integrated circuit (PMIC) will have at least one of a controller, a buck converter, a capacitor, a resistor, and an inductor, [0087]).
Regarding claim 3, Lin572 teaches wherein the power distribution module includes a regulator (power management integrated circuit (PMIC) will have a regulator, [0087]).
Regarding claim 6, Lin572 teaches wherein the redistribution structure includes a plurality of redistribution lines, and wherein the power distribution module is electrically connected only through the redistribution lines disposed at the lowest level of the plurality of redistribution lines (fig. 8).
Regarding claim 7, Lin572 teaches wherein the redistribution structure includes a plurality of redistribution vias, and wherein each redistribution via among the plurality of redistribution vias has an uppermost width smaller than a lowermost width (fig. 8).
Regarding claim 8, Lin572 teaches wherein the second semiconductor die is disposed side by side with the first semiconductor die (fig. 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin572, as applied to claim 1 above, and further in view of Lee (US publication 2022/0199008 A1), hereinafter referred to as Lee008.
Regarding claim 4, Lin572 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Lin572 does not explicitly teach wherein an input voltage of the power distribution structure is higher than an output voltage of the power distribution structure.
Lee008 teaches wherein an input voltage of the power distribution structure is higher than an output voltage of the power distribution structure ([0095-0102]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin572 with that of Lee008 so that wherein an input voltage of the power distribution structure is higher than an output voltage of the power distribution structure for a desired application.
Regarding claim 5, Lin572 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Lin572 does not explicitly teach wherein an output current of the power distribution structure is higher than an input current of the power distribution structure.
Lee008 teaches wherein an output current of the power distribution structure is higher than an input current of the power distribution structure ([0095-0102).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin572 with that of Lee008 so that wherein an output current of the power distribution structure is higher than an input current of the power distribution structure for a desired application.
Claim 9-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US publication 2020/0168572 A1), hereinafter referred to as Lin572, in view of Seo et al. (US publication 2015/0130041 A1), hereinafter referred to as Seo041.
Regarding claim 9, Lin572 teaches a semiconductor package (fig. 8 and related text) comprising: an interposer (A+B, examiner markup above) including a power distribution structure (A, examiner markup above) and a redistribution structure (B, examiner markup above) on the power distribution structure; a plurality of external connection members (226, [0075]) connected to a bottom surface of the interposer (fig. 8); a first semiconductor die (110, [0045]) on the interposer; and a second semiconductor die (210, [0045]) on the interposer, wherein the power distribution structure includes: a power distribution module (310, power management integrated circuit (PMIC), [0087]) connected to a bottom surface of the redistribution structure (fig. 8); a plurality of conductive posts (322, [0055]) connected to the bottom surface of the redistribution structure (fig. 8), wherein each conductive post of the plurality of conductive posts electrically connects the redistribution structure to an external connection member of the plurality of external connection members (fig. 8); and a molding material (320, [0054]) for molding side surfaces of the plurality of conductive posts, the power distribution module (fig. 8).
Lin572 does not explicitly teach a surface mounting device connected to the bottom surface of the redistribution structure; and a molding material for molding the surface mounting device.
Seo041 teaches a surface mounting device (223, [0048]) connected to the bottom surface of the redistribution structure (fig. 5); and a molding material (117, [0046]) for molding the surface mounting device (fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Lin572 with that of Seo041 so that a surface mounting device connected to the bottom surface of the redistribution structure; and a molding material for molding the surface mounting device so that passive elements are mounted on semiconductor packages in order to improve a power integrity characteristic ([0005]).
Regarding claim 10, Seo041 teaches wherein the surface mounting device includes an integrated stack capacitor (ISC) chip ([0053]).
Regarding claim 11, Lin572 teaches wherein the first semiconductor die includes a system on chip (SoC) ([0046]).
Regarding claim 12, Lin572 teaches wherein the second semiconductor die includes a high bandwidth memory (HBM) ([0046]).
Regarding claim 13, Lin572 teaches wherein the molding material includes an epoxy molding compound (EMC) ([0039 and 0054]).
Regarding claim 14, Seo041 teaches wherein the redistribution structure includes a plurality of redistribution lines, and wherein the surface mounting device is electrically connected only through the redistribution lines disposed at the lowest level of the plurality of redistribution lines (fig. 5).
Regarding claim 15, Lin572 teaches further comprising: an interconnect structure between the interposer and the first semiconductor die, and between the interposer and the second semiconductor die (fig. 8).
Regarding claim 16, Lin572 teaches wherein the interconnect structure includes connection members and an insulating member surrounding the connection members (fig. 8).
Regarding claim 17, Lin572 teaches wherein the connection members include micro bumps (fig. 8).
Regarding claim 18, Lin572 teaches wherein the insulating member includes a non-conductive film (NCF) (fig. 8).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
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