DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-19 in the reply filed on June 22, 2026 is acknowledged.
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 22, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Covey (US 20070189665).
Regarding claim 1, Covey discloses (Figs. 1-23) a photonic circuit, comprising: one or more photonic logic gates (40) having a first set of one or more inputs (1, 2) and a first set of one or more outputs (3, 4), the first set of one or more inputs configured to receive one or more photonic input signals, the one or more photonic logic gates (40) configured to generate one or more photonic intermediate output signals (3, 4) at the first set of one or more outputs based at least in part on the one or more photonic input signals (1, 2); and one or more nonlinear photonic elements (10, 10’) having a second set of one or more inputs (3, 3’, 4, 4’) and a second set of one or more outputs (7, 7’), the second set of one or more inputs coupled to the first set of one or more outputs and configured to receive the one or more photonic intermediate output signals, the one or more nonlinear photonic elements (10, 10’) configured to generate one or more photonic output signals at the second set of one or more outputs through application of a nonlinear transfer function (6, 6’) of the one or more nonlinear photonic elements to one or more amplitudes of the one or more photonic intermediate output signals (sections 0053-0060, 0083).
Regarding claim 9, Covey discloses (Figs. 1-23) the one or more nonlinear photonic elements comprise one or more active semiconductor optical amplifier-based amplitude thresholders (sections 0047-0048, 0071).
Regarding claim 15, Covey discloses (Figs. 1-23) the one or more photonic logic gates are composed of one or more linear photonic elements (sections 0014, 0055, 0057,0065).
Regarding claim 16, Covey discloses (Figs. 1-23) the photonic circuit is part of a photonic processor comprising the photonic circuit and one or more other photonic circuits, one or more inputs (1, 2, 3, 3’, 4, 4’) of the one or more other photonic circuits coupled to the second set of one or more outputs of the photonic circuit (section 0075).
Allowable Subject Matter
Claims 2-8 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the prior art does not disclose or suggest the photonic circuit of claim 2, in particular the limitations of the one or more nonlinear photonic elements comprise one or more amplitude thresholders configured to apply the nonlinear transfer function by saturating the one or more amplitudes of the one or more photonic intermediate output signals to one or more amplitude saturation levels when generating the one or more photonic output signals. The prior art does not disclose or suggest the photonic circuit of claims 3-4, in particular the limitations of one or more differences between two or more amplitude levels of the one or more photonic output signals generated by the one or more nonlinear photonic elements are smaller than one or more differences between two or more amplitude levels of the one or more photonic intermediate output signals input to the one or more nonlinear photonic elements. The prior art does not disclose or suggest the photonic circuit of claims 5-6, in particular the limitations of the one or more nonlinear photonic elements operate in at least one of: a first operating regime defined by a first portion of the nonlinear transfer function, a second operating regime defined by a second portion of the nonlinear transfer function, and a third operating regime defined by a third portion of the nonlinear transfer function. The prior art does not disclose or suggest the photonic circuit of claims 7-8, in particular the limitations of the one or more nonlinear photonic elements are configured to: saturate an amplitude of the one or more photonic intermediate output signals to a first amplitude level, when the one or more nonlinear photonic elements operate in the first operating regime, apply a transfer gain of the nonlinear transfer function to the amplitude of the one or more photonic intermediate output signals, when the one or more nonlinear photonic elements operate in the second operating regime, or saturate the amplitude of the one or more photonic intermediate output signals to a second amplitude level, when the one or more nonlinear photonic elements operate in the third operating regime. The prior art does not disclose or suggest the photonic circuit of claims 10-12, in particular the limitations of the one or more nonlinear photonic elements comprise a saturable absorber. The prior art does not disclose or suggest the photonic circuit of claims 13-14, in particular the limitations of the one or more nonlinear photonic elements comprise: a first semiconductor optical amplifier (SOA) having a first input and a first output, the first input coupled to the first set of one or more outputs and configured to receive the one or more photonic intermediate output signals; a saturable absorber having a second input and a second output, the second input coupled to the first output of the first SOA; and a second SOA having a third input and a third output, the third input coupled to the second output of the saturable absorber, the second SOA configured to output the one or more photonic output signals at the third output.
Claims 17-19 are considered allowable subject matter.
The prior art does not disclose or suggest the computer-readable storage medium of claims 17-19, in particular the limitations of a non-transitory computer-readable storage medium comprising stored instructions that, when executed by at least one processor, cause the at least one processor to execute operations and instruct the one or more nonlinear photonic elements to generate one or more photonic output signals at a second set of one or more outputs through application of a nonlinear transfer function of the one or more nonlinear photonic elements to one or more amplitudes of the one or more photonic intermediate output signals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES S CHANG whose telephone number is (571)270-5024. The examiner can normally be reached Monday - Friday, 9:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Caley can be reached at (571) 272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLES S CHANG/Primary Examiner, Art Unit 2871
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