Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6 and 9-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawahara et al. (Kawahara et al., “Bandwidth Tripler: Broadband Signal Generation with an Image-Rejection Analog Multiplexer for Fiber Optical Transmitters”, IEEE Transactions on Microwave Theory and Techniques, Vol. 71, No. 1, January 2023).
Regarding claim 1, Kawahara et al. teaches in FIG. 2(b) an apparatus comprising a first analog multiplexer configured to provide a respective one of a plurality of first input signals (data 1 and data 2) as a first output signal based on a first control signal (the AMUX shown in FIG. 2(b) consists of two multiplexers controlled by two clock signals), a second analog multiplexer configured to provide a respective one of a plurality of second input signals (data 3 and data 4) as a second output signal based on a second control signal, and a combiner configured to combine the first output signal and the second output signal to obtain a third output signal (the analog output).
Regarding claim 2, Kawahara et al. teaches in FIG. 2(b) that the two clock signals has a phase shift of 90°.
Regarding claim 3, Kawahara et al. teaches on page 28, right col., last paragraph that the clock signals are generated with a signal generator (SG) Keysight E8257D and a 90° hybrid Marki QH-0867.
Regarding claim 5, Kawahara et al. teaches in FIG. 2(b) that the two clock signals has a phase shift of 90°.
Regarding claim 6, Kawahara et al. teaches in FIG. 2(a) that the symbol rate of the input signals is 1/3 of fm and the switch clock rate is 2/3 of fm.
Regarding claim 9, Kawahara et al. teaches in FIG. 2(b) that the multiplexers are 2:1 (see page 23, left col., second paragraph).
Regarding claim 10, Kawahara et al. teaches in FIG. 2(b) 2*2 input signals data1, data2, data3 and data4.
Claim 11 is rejected based on the same reason for rejecting claim 1 because an apparatus implies the method of using it.
Claim(s) 13, 15 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thomas et al. (Thomas et al., “1-to-4 Analog Demultiplexer With up to 128 GS/s for Interleaving of Bandwidth-Limited Digitizers in Wireline and Optical Receivers”, IEEE Journal of Solid-State Circuits, Vol. 56, No. 9, September 2021).
Regarding claim 13, Thomas et al. teaches in FIG. 3 an apparatus comprising a first analog de-multiplexer (the upper de-multiplexer for Vin at the upper output of gm) configured to provide, based on a first de-multiplexer control signal, a respective portion of a modulated signal at a respective output of the first analog de-multiplexer, a second analog de-multiplexer (the bottom de-multiplexer for Vin₋ at the bottom output of gm) configured to provide, based on a second de-multiplexer control signal, a respective portion of the modulated signal at a respective output of the second analog de-multiplexer.
Regarding claim 15, Thomas et al. teaches in FIG. 3 that the switch frequency of the analog de-multiplexer and the second analog de-multiplexer for switching between respective outputs is equal to a symbol rate of first and second input signals associated with the modulated signal.
Regarding claim 17, Thomas et al. teaches in FIG. 1 photodetectors for converting optical signal to electrical signal.
Regarding claim 18, Thomas et al. teaches in FIG. 3 two 1:4 de-multiplexer and generate 2*4 = 8 output signals which implies 2*4 input signals.
Claim 19 is rejected based on the same reason for rejecting claim 13 because an apparatus implies the method of using it.
Regarding claim 20, Thomas et al. teaches in FIG. 1 a receiver comprising the demultiplexers of claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawahara et al. (Kawahara et al., “Bandwidth Tripler: Broadband Signal Generation with an Image-Rejection Analog Multiplexer for Fiber Optical Transmitters”, IEEE Transactions on Microwave Theory and Techniques, Vol. 71, No. 1, January 2023) in view of Shankar (U.S. Patent Application Pub. 2015/0229403 A1).
Kawahara et al. has been discussed above in regard to claims 1-3, 5-6 and 9-11. The difference between Kawahara et al. and the claimed invention is that Kawahara et al. does not teach a modulator stage. However, it is well known in the art that signals can be sent from one place to another by using a communication system. For example, Shankar teaches in FIG. 1 an optical communication system comprising a transmitter and a receiver. Shankar teaches in FIG. 6 details of the transmitter. Shankar teaches in FIG. 1 laser as an optical carrier for the modulator. One of ordinary skill in the art would have been motivated to combine the teaching of Shankar with the system of Kawahara et al. because Kawahara et al. suggests in the title to use the apparatus in an optical transmitter. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a modulator stage, as taught by Shankar, in the system of Kawahara et al.
Regarding claim 8, Shankar teaches in FIG. 1 MZ modulator.
Regarding claim 12, the combination of Kawahara et al. and Shankar teaches a transmitter comprising at least one apparatus according to claim 1.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al. (Thomas et al., “1-to-4 Analog Demultiplexer With up to 128 GS/s for Interleaving of Bandwidth-Limited Digitizers in Wireline and Optical Receivers”, IEEE Journal of Solid-State Circuits, Vol. 56, No. 9, September 2021) in view of Shimizu et al. (U.S. Patent Application Pub. 2023/0353253 A1).
Thomas et al. has been discussed above in regard to claims 13, 15 and 17-20. The difference between Thomas et al. and the claimed invention is that Thomas et al. does not teach a clock recovery unit configured to recover a clock signal and used as the control signal. Shimizu et al. teaches in FIG. 2 an apparatus comprising a demultiplexer (DMX1 (1:4)) and a clock recovery unit (CRU) wherein the clock signal recovered by the CRU is used as the clock signal for the demultiplexer. One of ordinary skill in the art would have been motivated to combine the teaching of Shimizu et al. with the system of Thomas et al. because it ensures that the data and the clock are synchronized. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a clock recovery unit for generating the clock signal, as taught by Shimizu et al., in the system of Thomas et al.
Allowable Subject Matter
Claim 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHI K LI whose telephone number is (571)272-3031. The examiner can normally be reached M-F 6:53 a.m. -3:23 p.m.
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skl23 February 2026
/SHI K LI/Primary Examiner, Art Unit 2635