DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites the limitation “capacitance of WBG power semiconductor” in Line 32.
Claim 1, Line 32 should recite: capacitance of the WBG power semiconductor.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the WBG power semiconductor device” in Lines 14, 15-16, 23-24, 26, 29-30, and 33-34. There is insufficient antecedent basis for this limitation in the claim.
In addition, the limitation includes the acronym “WBG” not previously defined.
Claim 1 recites the limitation “a wide bandgap power device” in Line 1.
It appears the limitation of Claim 1, Lines 14, 15-16, 23-24, 26, 29-30, and 33-34 is referring to the limitation found on Claim 1, Line 1.
The examiner suggests Claim 1, Line 1 recite: a wide bandgap (WBG) power semiconductor device.
Claims 2-20 are rejected under 112(b) as they inherit the deficiencies of Claim 1 as identified above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kobayashi (US 2024/0356541) discloses a gate drive circuit comprising a resistor (RgOn) (Fig.3A) forming a charging path and a resistor (RgOff) forming a discharging path (Par.49).
Nagatomi et al. (US 2022/0345128) discloses a gate driver separate charge and discharge paths (Par.80) (Fig.2B).
Koyama et al. (US 2020/0220534) discloses a gate drive circuit (Fig.1) including a first resistor (5), a second resistor (6), a first inductor (10), and a second inductor (11) (Par.31).
Cyr et al. (US 2014/0321178) discloses diodes to protect the transistors of a gate drive (Par.39).
Tao et al. (US 2013/0162322) discloses a circuit (104), comprising a diode and a Zener diode (Par.33), coupled to a gate of a semiconductor device (Fig.10).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHALI ALEJANDRA TORRES RUIZ whose telephone number is (571)270-1262. The examiner can normally be reached M-F 10:00am-6:00pm.
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/JOHALI A TORRES RUIZ/Examiner, Art Unit 2859
/JULIAN D HUFFMAN/Supervisory Patent Examiner, Art Unit 2859
