DETAILED ACTION
This Office action is in response to the application filed on 09 February 2024.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being obvious over YOSHIDA US 2021/0203372 A1.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). The claimed elements of “module substrate”, “passive component”, “electronic components”, … are similar elements in YOSHIBA as explained and mapped as follows:
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
As to claim 1, YOSHIBA discloses substantially the invention as claimed, including a radio-frequency module (Figure 2B, the radio frequency module 1A) having a first major surface (the upper surface of the shield electrode layer 80G in figure 2B) and a second major surface (the lower surface) that are opposite to each other (as illustrated in Figure 2B, the radio frequency module 1A may further include a shield electrode layer 80G that covers the front surface and side surfaces of the resin component 92 and the side surfaces of the resin component 93, and is set to the ground potential, [83]), the radio-frequency module comprising:
a module substrate (Figure 2B, the module board 91) having a third major surface and a fourth major surface that are opposite each other, the third major surface being disposed alongside the first major surface, the fourth major surface being disposed alongside the second major surface (Figure 2B, the module board 91 having an upper surface corresponding to the claimed third major surface and a lower surface corresponding to the claimed fourth major surface in figure 2B);
a plurality of electronic components disposed at the third major surface and at the fourth major surface (the matching circuit 32, reception filter 40R, and Power Amplifier 10 disposed on the surface corresponding to the claimed third major surface, and the low noise amplifier 20 and switch 50 disposed on the surface corresponding to the claimed fourth major surface in figure 2B);
a plurality of external connection terminals disposed at the second major surface, the plurality of external connection terminals including a first external connection terminal (corresponding to the ground electrode 71G, signal electrodes 120A, 160A, etc., in figure 2B);
a first resin member at least partially covering the fourth major surface and an electronic component disposed at the fourth major surface (Figure 2B, the resin member 93); and
a plurality of electrodes (the electrodes 21, 51) disposed at the fourth major surface, the plurality of electrodes being coupled to the plurality of external connection terminals (Figure 2B, the electrodes 21, 51, etc.), wherein
the plurality of electronic components include a passive component that is disposed at the fourth major surface and that includes at least one of a capacitor (Figure 4, capacitor 95, 96) and an inductor (an inductor 94) (the switch 50, in figure 2B is one type of passive component. Moreover, a passive component such as an inductor 94 or capacitor 95/96 is normally disposed in a circuit and is well understood to also disposed in the circuit in Figure 2B; corresponding to said passive component), and
at least a portion of the first external connection terminal overlaps at least a portion of the passive component in plan view of the module substrate (Figure 2B, the external connection terminal 120A of the low noise amplifier 20 overlaps with the low noise amplifier 20; it would have been obvious to ordinary skill in the art that the same can also be done for the same passive component).
As to claim 2, YOSHIBA discloses, wherein the plurality of electronic components further include an active component including an active element, the plurality of external connection terminals include a power supply terminal (power supply terminal 160) and a ground terminal, the passive component includes a capacitor (capacitors 95, 96), the power supply terminal is coupled to one end of the capacitor and the active element, the ground terminal is coupled to another end of the capacitor, and the first external connection terminal is the power supply terminal or the ground terminal (Figure 3 and associated paragraphs, [27]).
As to claim 3, YOSHIBA discloses, wherein the plurality of external connection terminals further include a second external connection terminal (Figure 2B, the external connection terminal 160A of the switch 50 does not overlap with the switch 50; it would have been obvious to ordinary skill in the art that the same can also be done for the same passive component) that does not overlap the passive component in plan view of the module substrate, the first external connection terminal is the ground terminal, and the second external connection terminal is the power supply terminal, and the second external connection terminal is coupled to the one end of the capacitor (the capacitor 95 or 96) and the active element via at least one of the plurality of electrodes (Figures 2B, and associated paragraphs).
As to claim 4, YOSHIBA discloses, further comprising a control circuit (figure 1, the PA control circuit 60) configured to control a power amplifier (figure 1, the PA 10), wherein the active component includes the control circuit (Figure 3A, the PA control circuit 60 may be a control circuit that control a RF component using a control signal, [92]).
As to claim 5, YOSHIBA discloses, further comprising a low-noise amplifier (Figures 1-4, the LNA 20), wherein the active component includes the low-noise amplifier(Figures 1-4, the LNA 20).
As to claim 6, YOSHIBA discloses, further comprising a Power Amplifier (Figures 1-4, the PA 10), wherein the active component includes the power amplifier (Figures 1-4, the PA 10).
As to claim 7, YOSHIBA discloses, wherein the passive component is a semiconductor component (Figures 1-4, the semiconductor 70).
As to claim 8, YOSHIBA discloses, wherein the passive component is an integrated passive device (IPD) using a semiconductor substrate (Figures 1-4, the semiconductor 70).
As to claim 9, YOSHIBA discloses, wherein the passive component has a fifth major surface and a sixth major surface, the fifth major surface facing the fourth major surface, the sixth major surface being opposite to the fifth major surface, and at least a portion of the sixth major surface is exposed at a surface of the first resin member (Figure 2B, the resin member 93) (Figure 2B-4B, and associated paragraphs).
As to claim 10, YOSHIBA discloses, wherein the first external connection terminal is in physical contact with the passive component (figure 1, the PA 10).
As to claim 11, YOSHIBA discloses, further comprising a second resin member (the resin member 92) disposed over the first resin member, wherein the second resin member is disposed between the passive component and the first external connection terminal in sectional view of the module substrate (Figure 2B, the resin member 92) (Figure 2B-4B, and associated paragraphs).
As to claim 12, YOSHIBA discloses, wherein the second resin member extends over the first resin member to cover the electronic component disposed at the fourth major surface (Figure 2B, the resin member 92) (Figure 2B-4B, and associated paragraphs).
As to claim 13, YOSHIBA discloses, wherein a plurality of through-holes are formed in the second resin member, at least a portion of each of the plurality of electrodes overlaps at least a portion of a corresponding through-hole in the second resin member in plan view of the module substrate, and each of the plurality of electrodes is electrically coupled to a corresponding external connection terminal via the corresponding through-hole (Figure 2B, the resin member 92) (Figure 2B-4B, and associated paragraphs).
As to claim 14, YOSHIBA discloses, wherein a permittivity of the second resin member is lower than a permittivity of the first resin member (Figures 2A, 2B, 2C and associated paragraphs).
As to claim 15, YOSHIBA discloses, wherein a portion of the first external connection terminal is in physical contact with the second resin member (Figures 2A, 2B, 2C and associated paragraphs).
As to claim 16, YOSHIBA discloses, wherein the first external connection terminal is not electrically coupled to the passive component in the radio-frequency module (Figures 2-4 and associated paragraphs).
As to claim 17, YOSHIBA discloses, wherein the plurality of external connection terminals include an antenna connection terminal (the antenna connection terminal 100C), the radio-frequency module further comprising: a plurality of filters (the filters 40); a switch (the switch 50) coupled between the antenna connection terminal and the plurality of filters; and a matching circuit (the matching circuit 31, 32) coupled between the antenna connection terminal and the switch, wherein the passive component includes the matching circuit (Figures 2-4 and associated paragraphs).
As to claim 18, YOSHIBA discloses, wherein the plurality of external connection terminals include a first radio-frequency terminal, a second radio-frequency terminal, and a ground terminal, and the first external connection terminal is a ground terminal (the ground terminal 71G), and the first external connection terminal is disposed between the first radio-frequency terminal (the terminal 120A) and the second radio-frequency terminal (the terminal 160A) in plan view of the module substrate (Figures 2-4 and associated paragraphs).
As to claim 19, YOSHIBA discloses, wherein the passive component is a semiconductor component (Figures 2-4 and associated paragraphs, the semiconductor IC 70).
As to claim 20, YOSHIBA discloses, a communication device (Figure 1, the communication device 5) comprising: a signal processing circuit (Figure 1, the RFIC 3 and the BBIC 4) configured to process a radio-frequency signal; and the radio-frequency module (Figure 1, the RF module 1) according to claim 1, the radio-frequency module being configured to transfer the radio-frequency signal between the signal processing circuit and an antenna (Figure 1, the antenna 2).
The prior art cited in this Office action is: YOSHIDA US 2021/0203372 A1.
Conclusion
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/HAI V NGUYEN/Primary Examiner, Art Unit 2649