DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I, with corresponding claims 1-8 and 14-20, in the reply filed on 08/07/2026 is acknowledged. Claims 9-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: CHIP PACKAGE STRUCTURE COMPRISING HYBRID BONDING STRUCTURE AND METHOD FOR PREPARING THE SAME
Drawings
Figure 1A-1D should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al. (US 2020/0126906 A1; hereinafter “Uzoh”) in view of Kang et al. (US 2021/0366852 A1; hereinafter “Kang”).
Regarding claim 1, referring to Fig. 3E-3F, Uzoh teaches a chip package structure, comprising a first chip and a first hybrid bonding structure (one of 302 as a first device die including integrated circuits and at least conductive interconnect structures for hybrid bonding) (paragraphs 3-10, 28, 38, and 45), wherein: the first chip is connected to another chip (the other one of 302 as a second device die as shown in Fig. 3F) through the first hybrid bonding structure (paragraph 45); the first hybrid bonding structure comprises a first bonding layer (102 and 114), and the first bonding layer comprises a first insulation material (an insulating layer 102) and a plurality of first metal solder pads (the conductive interconnect structures 114) embedded in the first insulation material (paragraphs 37-44); each of the plurality of first metal solder pads comprises a groove structure (a recessed region of 114 corresponding to a dishing region 116), wherein a groove bottom of the groove structure is buried in the first insulation material, and a groove opening of the groove structure is exposed to a surface of the first insulation material and is flush with the surface of the first insulation material (Fig. 3E); and the groove structure is filled with a first insulation medium (an embedded layer 304 formed of a dielectric material), wherein a surface of the first insulation medium is flush with the surface of the first insulation material (Fig. 3E and paragraphs 37 and 44-45).
Uzoh does not teach a substrate of the first chip such that the first bonding layer is disposed on a side away from the substrate of the first chip. Kang teaches a chip package structure (a semiconductor package 100 for hybrid bonding as shown in Fig. 1) comprising: a first chip (a bottom portion of 100 including at least 110) comprising a substrate (a first substrate 110) such that a first hybrid bonding structure comprising a first bonding layer (a hybrid bonding structure including 150 and 134) is disposed on a side away from the substrate of the first chip (Fig. 1 and paragraphs 31-34). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Uzoh with that of Kang as an obvious design choice for forming the bonding structures on the substrate of the first chip in order to additionally bond with another chip/die having the bonding structures.
Regarding claim 2, Kang teaches wherein: a plurality of vias are (132) further disposed in the first bonding layer (150); each of the plurality of vias is filled with or electroplated with a conductive material (for example, copper); and at least a part of the plurality of first metal solder pads are connected to the first chip through a corresponding via (Fig. 1 and paragraph 33-34).
Regarding claim 3, Kang teaches wherein: the first hybrid bonding structure further comprises a first redistribution layer (120); the first redistribution layer is formed between the first chip and the first bonding layer (Fig. 1); the first redistribution layer comprises a plurality of layers of patterned conductive lines (122 and 124); and the at least a part of the plurality of first metal solder pads are connected to the first chip through the plurality of vias and the plurality of layers of patterned conductive lines (Fig. 1 and paragraph 31).
Regarding claim 4, while Uzoh in view of Kang does not teach that a pattern formed on a surface of each of the plurality of first metal solder pads is a ring, it would have been obvious to one of ordinary skill in the art to provide the plurality of first metal solder pads having the ring shape from a top-down view of the chip package structure as one of design choices with the embedded dielectric layer 304 formed at the center region of the interconnect structures 114 from Uzoh in Fig. 3F.
Regarding claim 5, Uzoh in view of Kang teaches further comprising a second chip and a second hybrid bonding structure (the other one of 302 as a second device die including integrated circuits and conductive interconnect structures for hybrid bonding), and wherein: the second chip is stacked above the first chip; and the second chip is connected to the first chip through the first hybrid bonding structure and the second hybrid bonding structure (Uzoh, Fig. 3F and paragraph 45 and Kang, Fig. 1).
Regarding claim 6, Uzoh in view of Kang teaches wherein: the second hybrid bonding structure comprises a second bonding layer, wherein the second bonding layer is disposed on a side away from a substrate of the second chip (See the rejection of claim 1 as discussed above, which is similarly applied for this limitation reciting “a substrate of the second chip”); the second bonding layer comprises a second insulation material and a plurality of second metal solder pads (114A) embedded in the second insulation material; each of the plurality of second metal solder pads comprises the groove structure, wherein a groove bottom of the groove structure is buried in the second insulation material, and a groove opening of the groove structure is exposed to a surface of the second insulation material and is flush with the surface of the second insulation material; and the groove structure is filled with a second insulation medium (304), wherein a surface of the second insulation medium is flush with the surface of the second insulation material (Uzoh, Fig. 3F).
Regarding claim 7, Uzoh teaches wherein: the first metal solder pads are configured to be correspondingly bonded to the second metal solder pads; the first insulation material is configured to be correspondingly bonded to the second insulation material; and the first insulation medium is configured to be correspondingly bonded to the second insulation medium (Fig. 3F).
Regarding claim 8, while Uzoh in view of Kang does not teach that a pattern formed on a surface of each of the plurality of second metal solder pads is a ring, it would have been obvious to one of ordinary skill in the art to provide the plurality of second metal solder pads having the ring shape from a top-down view of the chip package structure as one of design choices with the embedded dielectric layer 304 formed at the center region of the interconnect structures 114A from Uzoh in Fig. 3F.
Regarding claim 14, referring to Fig. 3E-3F, Uzoh teaches an electronic device, comprising a chip package structure (a bonded device 312), wherein the chip package structure comprises a first chip and a first hybrid bonding structure (one of 302 as a first device die including integrated circuits and at least conductive interconnect structures for hybrid bonding) (paragraphs 3-10, 28, 38, and 45), and wherein: the first chip is connected to another chip (the other one of 302 as a second device die as shown in Fig. 3F) through the first hybrid bonding structure (paragraph 45); the first hybrid bonding structure comprises a first bonding layer (102 and 114), and the first bonding layer comprises a first insulation material (an insulating layer 102) and a plurality of first metal solder pads (the conductive interconnect structures 114) embedded in the first insulation material (paragraphs 37-44); each of the plurality of first metal solder pads comprises a groove structure (a recessed region of 114 corresponding to a dishing region 116), wherein a groove bottom of the groove structure is buried in the first insulation material, and a groove opening of the groove structure is exposed to a surface of the first insulation material and is flush with the surface of the first insulation material (Fig. 3E); and the groove structure is filled with a first insulation medium (an embedded layer 304 formed of a dielectric material), wherein a surface of the first insulation medium is flush with the surface of the first insulation material (Fig. 3E and paragraphs 37 and 44-45).
Uzoh does not teach a substrate of the first chip such that the first bonding layer is disposed on a side away from the substrate of the first chip. Kang teaches a chip package structure (a semiconductor package 100 for hybrid bonding as shown in Fig. 1) comprising: a first chip (a bottom portion of 100 including at least 110) comprising a substrate (a first substrate 110) such that a first hybrid bonding structure comprising a first bonding layer (a hybrid bonding structure including 150 and 134) is disposed on a side away from the substrate of the first chip (Fig. 1 and paragraphs 31-34). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Uzoh with that of Kang as an obvious design choice for forming the bonding structures on the substrate of the first chip in order to additionally bond with another chip/die having the bonding structures.
Regarding claim 15, Kang teaches wherein: a plurality of vias are (132) further disposed in the first bonding layer (150); each of the plurality of vias is filled with or electroplated with a conductive material (for example, copper); and at least a part of the plurality of first metal solder pads are connected to the first chip through a corresponding via (Fig. 1 and paragraph 33-34).
Regarding claim 16, Kang teaches wherein: the first hybrid bonding structure further comprises a first redistribution layer (120); the first redistribution layer is formed between the first chip and the first bonding layer (Fig. 1); the first redistribution layer comprises a plurality of layers of patterned conductive lines (122 and 124); and the at least a part of the plurality of first metal solder pads are connected to the first chip through the plurality of vias and the plurality of layers of patterned conductive lines (Fig. 1 and paragraph 31).
Regarding claim 17, while Uzoh in view of Kang does not teach that a pattern formed on a surface of each of the plurality of first metal solder pads is a ring, it would have been obvious to one of ordinary skill in the art to provide the plurality of first metal solder pads having the ring shape from a top-down view of the chip package structure as one of design choices with the embedded dielectric layer 304 formed at the center region of the interconnect structures 114 from Uzoh in Fig. 3F.
Regarding claim 18, Uzoh in view of Kang teaches further comprising a second chip and a second hybrid bonding structure (the other one of 302 as a second device die including integrated circuits and conductive interconnect structures for hybrid bonding), and wherein: the second chip is stacked above the first chip; and the second chip is connected to the first chip through the first hybrid bonding structure and the second hybrid bonding structure (Uzoh, Fig. 3F and paragraph 45 and Kang, Fig. 1).
Regarding claim 19, Uzoh in view of Kang teaches wherein: the second hybrid bonding structure comprises a second bonding layer, wherein the second bonding layer is disposed on a side away from a substrate of the second chip (See the rejection of claim 1 as discussed above, which is similarly applied for this limitation reciting “a substrate of the second chip”); the second bonding layer comprises a second insulation material and a plurality of second metal solder pads (114A) embedded in the second insulation material; each of the plurality of second metal solder pads comprises the groove structure, wherein a groove bottom of the groove structure is buried in the second insulation material, and a groove opening of the groove structure is exposed to a surface of the second insulation material and is flush with the surface of the second insulation material; and the groove structure is filled with a second insulation medium (304), wherein a surface of the second insulation medium is flush with the surface of the second insulation material (Uzoh, Fig. 3F).
Regarding claim 20, Uzoh teaches wherein: the first metal solder pads are configured to be correspondingly bonded to the second metal solder pads; the first insulation material is configured to be correspondingly bonded to the second insulation material; and the first insulation medium is configured to be correspondingly bonded to the second insulation medium (Fig. 3F).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL WHALEN/Primary Examiner, Art Unit 2893
Prosecution Insights