DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanabe et al. (US 5,796,301), in view of Heineman et al. (US 8,829,990 B2), in further view of Dong (US, 9,674,009 B2).
Regarding Claim 1, Tanabe et al. teaches in Figure 5 a receiver circuit comprising:
a first circuit configured to receive a first signal pair and generate a first compensation signal (received at nodes 1 and 2 of 11, which outputs Vo1+, Vcm1, and Vo1-);
a second circuit configured to receive a second signal pair and generate a second compensation signal (received at nodes 3 and 4 of 12, which outputs Vo2+, Vcm2, and Vo2-); and
an averaging circuit configured to receive the first compensation signal pair and the second compensation signal pair to average voltage levels of the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair (using R3 and R4 to generate Vcm at node 7);
but does not explicitly disclose
a first summing circuit configured to receive an input signal pair and equalize the input signal pair with a first offset to generate a first compensation signal pair;
a second summing circuit configured to receive the input signal pair and equalize the input signal pair with a second offset to generate a second compensation signal pair;
a sampling circuit configured to receive the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair to compare the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair with a first reference voltage and a second reference voltage to generate a first sampling signal pair, a second sampling signal pair, and a third sampling signal pair, respectively; and
an output circuit configured to generate an nth reception symbol from one sampling signal pair among the first to third sampling signal pairs based on an n-1th reception symbol, wherein the n is an integer of 2 or more.
Heineman et al. teaches in Figure 12
a first summing circuit configured to receive the input signal pair and equalize the input signal pair with a first offset to generate a first signal pair (upper adder 910); and
a second summing circuit configured to receive the input signal pair and equalize the input signal pair with a second offset to generate a second signal pair (lower adder 910);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Heineman et al. with the input signals of Tanabe et al. for the purpose of adding “a DC-Offset … to both PWM signals to prevent the rising and falling edges of the PWM A and PWM B signals from lining up.” Heineman et al.: Col. 10, lines 63-65.
Tanabe et al. and Heineman et al., as a whole, teach all the limitations of the present invention, but do not explicitly teach
a sampling circuit configured to receive the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair to compare the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair with a first reference voltage and a second reference voltage to generate a first sampling signal pair, a second sampling signal pair, and a third sampling signal pair, respectively; and
an output circuit configured to generate an nth reception symbol from one sampling signal pair among the first to third sampling signal pairs based on an n-1th reception symbol, wherein the n is an integer of 2 or more.
Dong teaches in Figure 1 a receiver circuit comprising:
a sampling circuit configured to receive the first compensation signal pair (where 120 receives REF 162), the second compensation signal pair (where 130 receives VCM 131), and the third compensation signal pair (where 124 receives REF 163) to compare the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair with a first reference voltage and a second reference voltage (where each pair of signals is compared to 118p and 118n) to generate a first sampling signal pair, a second sampling signal pair, and a third sampling signal pair, respectively (generating errorP 122, Data 132, and errorN 126, respectively); and
an output circuit configured to generate an nth reception symbol from one sampling signal pair among the first to third sampling signal pairs based on an n-1th reception symbol (using Calibration 140),
wherein the n is an integer of 2 or more (n is 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Dong with the outputs of Tanabe et al. and Heineman et al., as a whole, for the purpose of “correctly recover[ing] data from the differential signal.” Dong: Col. 1, lines 18-19.
Regarding Claim 2, Tanabe et al., Heineman et al., and Dong, as a whole, teach all the limitations of the present invention, and further teaches wherein the receiver circuit,
wherein the input signal pair includes an input signal and a complementary input signal (Tanabe et al.: Vi1+, Vi1-; see also Heineman et al.: 502), and the first compensation signal pair includes a first compensation signal and a first complementary compensation signal (Heineman et al.: at upper and lower 910), and
wherein the first summing circuit is configured to generate the first compensation signal having a voltage level substantially equal to a voltage level of the input signal (Heineman et al.: as outputted by upper 910), and the first complementary compensation signal having a voltage level lower than a voltage level of the complementary input signal (Heineman et al.: as outputted by lower 910).
Regarding Claim 5, Tanabe et al., Heineman et al., and Dong, as a whole, teach all the limitations of the present invention, wherein Tanabe et al. further teaches the receiver circuit, wherein the averaging circuit comprises:
a first load circuit (R3); and
a second load circuit (R4),
wherein one end of the first load circuit receives the first compensation signal pair (as connected to Vcm1), and the other end of the first load circuit is coupled to a node from which the third compensation signal pair is output (Vcm), and
wherein one end of the second load circuit receives the second compensation signal pair (as connected to Vcm2), and the other end of the second load circuit is coupled to the node from which the third compensation signal pair is output (Vcm).
Regarding Claim 6, Tanabe et al., Heineman et al., and Dong, as a whole, teach all the limitations of the present invention, wherein Dong further teaches the receiver circuit, wherein the sampling circuit comprises:
a first sense amplifier configured to sense and amplify the first compensation signal pair, the first reference voltage, and the second reference voltage to generate the first sampling signal pair (using 120, which receives REF 162, 118p, and 118n);
a second sense amplifier configured to sense and amplify the second compensation signal pair, the first reference voltage, and the second reference voltage to generate the second sampling signal pair (using 130, which receives VCM 131, 118p, and 118n); and
a third sense amplifier configured to sense and amplify the third compensation signal pair, the first reference voltage, and the second reference voltage to generate the third sampling signal pair (using 124, which receives REF 164, 118p, and 118n).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanabe et al. (US 5,796,301), Heineman et al. (US 8,829,990 B2), and Dong (US, 9,674,009 B2), as a whole, and as applied to Claim 1 above, and further in view of Francese et al. (US 9,860,087 B1).
Regarding Claim 7, Tanabe et al., Heineman et al., and Dong, as a whole, teach all the limitations of the present invention, but does not explicitly teach the receiver circuit, wherein the output circuit is configured to output the second sampling signal pair as the nth reception symbol when the n-1th reception symbol is in a first state, configured to output the third sampling signal pair as the nth reception symbol when the n-1th reception symbol is in a second state, and configured to output the first sampling signal pair as the nth reception symbol when the n-1th reception symbol is in a third state.
Francese et al. teaches in Figure 1 a circuit,
wherein the output circuit is configured to output the second sampling signal pair as the nth reception symbol when the n-1th reception symbol is in a first state, configured to output the third sampling signal pair as the nth reception symbol when the n-1th reception symbol is in a second state, and configured to output the first sampling signal pair as the nth reception symbol when the n-1th reception symbol is in a third state (based on 116A and the Clock Gating and De-mux Select Logic 122A; based on 116B and the Clock Gating and De-mux Select Logic 122B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output circuit of Francese et al. with the amplifier outputted signals of Tanabe et al., Heineman et al., and Dong, as a whole, for the purpose of reducing power consumption. Francese et al.: Col. 1, lines 31-32.
Regarding Claim 8, Tanabe et al., Heineman et al., and Dong, as a whole, teach all the limitations of the present invention, but does not explicitly teach the receiver circuit, wherein the output circuit comprises:
a multiplexer configured to output one of the first to third sampling signal pairs as a selected sampling signal pair based on the n-1th reception symbol; and
a latch circuit configured to latch the selected sampling signal pair to generate the nth reception symbol.
Francese et al. teaches in Figure 1 an output circuit comprises:
a multiplexer configured to output one of the first to third sampling signal pairs as a selected sampling signal pair based on the n-1th reception symbol (116A, based on Clock Gating and De-mux Select Logic 122A; 116B, based on Clock Gating and De-mux Select Logic 122B); and
a latch circuit configured to latch the selected sampling signal pair to generate the nth reception symbol (118A, 118B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output circuit of Francese et al. with the amplifier outputted signals of Tanabe et al., Heineman et al., and Dong, as a whole, for the purpose of reducing power consumption. Francese et al.: Col. 1, lines 31-32.
Claim(s) 9 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bartling et al. (12, 052, 335 B2), in view of Tanabe et al. (US 5,796,301), in further view of Dong (US, 9,674,009 B2), and in further view of Francese et al. (US 9,860,087 B1).
Regarding Claim 9, Bartling et al. teaches in Figure 1 a semiconductor apparatus comprising:
a first receiver circuit configured to receive an input signal pair, and configured to generate a first reception symbol from the input signal pair in synchronization with a first phase clock signal (receiver 102 and clock signals 114); and
a second receiver circuit configured to receive the input signal pair, and configured to generate a second reception symbol from the input signal pair in synchronization with a second phase clock signal (receiver 103 and clock signals 115),
but does not explicitly teach wherein the first receiver circuit comprises:
a compensation signal generation circuit configured to equalize the first input signal pair with a first offset to generate a first compensation signal pair, configured to equalize the input signal pair with a second offset to generate a second compensation signal pair, and configured to average voltage levels of the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair; a sampling circuit configured to compare the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair with a first reference voltage and a second reference voltage to generate a first sampling signal pair, a second sampling signal pair, and a third sampling signal pair, respectively in synchronization with the first phase clock signal; and an output circuit configured to select one sampling signal pair among the first to third sampling signal pairs based on the second reception symbol to generate a selected sampling signal pair, and configured to generate the selected sampling signal pair as the first reception symbol in synchronization with the first phase clock signal.
Tanabe et al. teaches in Figure 5 a receiver circuit comprising:
a compensation signal generation circuit
configured to equalize the first input signal pair with a first offset to generate a first compensation signal pair (using 11 and 15, which outputs Vo1+, Vcm1, Vo1-, and Vo+),
configured to equalize the input signal pair with a second offset to generate a second compensation signal pair (using 12 and 16, which outputs Vo2+, Vcm2, Vo2-, and Vo2), and
configured to average voltage levels of the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair (using R2 and R4 to generate Vcm at node 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the circuitry of Tanabe et al. within the receiver of Bartling et al. for the purpose of “cancelling offset quantities existing in respective common mode output potentials.” Tanabe et al.: Col. 2, lines 1-3.
Bartling et al. and Tanabe et al., as a whole, teach all the limitations of the present invention, but does not explicitly teach a sampling circuit configured to compare the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair with a first reference voltage and a second reference voltage to generate a first sampling signal pair, a second sampling signal pair, and a third sampling signal pair, respectively in synchronization with the first phase clock signal; and an output circuit configured to select one sampling signal pair among the first to third sampling signal pairs based on the second reception symbol to generate a selected sampling signal pair, and configured to generate the selected sampling signal pair as the first reception symbol in synchronization with the first phase clock signal.
Dong teaches in Figure 1 a circuit comprising:
a sampling circuit configured to receive the first compensation signal pair (where 120 receives REF 162), the second compensation signal pair (where 130 receives VCM 131), and the third compensation signal pair (where 124 receives REF 163) to compare the first compensation signal pair, the second compensation signal pair, and the third compensation signal pair with a first reference voltage and a second reference voltage (where each pair of signals is compared to 118p and 118n) to generate a first sampling signal pair, a second sampling signal pair, and a third sampling signal pair, respectively in synchronization with the first phase clock signal (generating errorP 122, Data 132, and errorN 126, respectively, as calibrated with the first phase clock signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Dong with the outputs of Bartling et al. and Tanabe et al., as a whole, for the purpose of “correctly recover[ing] data from the differential signal.” Dong: Col. 1, lines 18-19.
Bartling et al., Tanabe et al., and Dong, as a whole, do not explicitly teach
an output circuit configured to select one sampling signal pair among the first to third sampling signal pairs based on the second reception symbol to generate a selected sampling signal pair, and configured to generate the selected sampling signal pair as the first reception symbol in synchronization with the first phase clock signal.
Francese et al. teaches in Figure 1 a circuit comprising,
an output circuit configured to select one sampling signal pair among the first to third sampling signal pairs based on the second reception symbol to generate a selected sampling signal pair, and configured to generate the selected sampling signal pair as the first reception symbol in synchronization with the first phase clock signal (based on 116A and the Clock Gating and De-mux Select Logic 122A; based on 116B and the Clock Gating and De-mux Select Logic 122B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the output circuit of Francese et al. with the amplifier outputted signals of Bartling et al., Tanabe et al., and Dong, as a whole, for the purpose of reducing power consumption. Francese et al.: Col. 1, lines 31-32.
Regarding Claim 15, Bartling et al., Tanabe et al., Dong, and Francese et al, as a whole, teach all the limitations of the present invention, wherein Dong further teaches the receiver circuit, wherein the sampling circuit comprises:
a first sense amplifier configured to sense and amplify the first compensation signal pair, the first reference voltage, and the second reference voltage to generate the first sampling signal pair in synchronization with the first phase clock signal (using 120, which receives REF 162, 118p, and 118n; operating in synchronization with the clock signals of Bartling et al.);
a second sense amplifier configured to sense and amplify the second compensation signal pair, the first reference voltage, and the second reference voltage to generate the second sampling signal pair in synchronization with the first phase clock signal (using 130, which receives VCM 131, 118p, and 118n; operating in synchronization with the clock signals of Bartling et al.); and
a third sense amplifier configured to sense and amplify the third compensation signal pair, the first reference voltage, and the second reference voltage to generate the third sampling signal pair in synchronization with the first phase clock signal (using 124, which receives REF 164, 118p, and 118n; operating in synchronization with the clock signals of Bartling et al.).
Regarding Claim 16, Bartling et al., Tanabe et al., Dong, and Francese et al, as a whole, teach all the limitations of the present invention, wherein Francese et al. further teaches the semiconductor apparatus,
wherein the output circuit is configured to output the second sampling signal pair as the first reception symbol when the second reception symbol is in a first state, configured to output the third sampling signal pair as the first reception symbol when the second reception symbol is in a second state, and configured to output the first sampling signal pair as the first reception symbol when the second reception symbol is in a third state (based on 116A and the Clock Gating and De-mux Select Logic 122A; based on 116B and the Clock Gating and De-mux Select Logic 122B).
Regarding Claim 17, Bartling et al., Tanabe et al., Dong, and Francese et al, as a whole, teach all the limitations of the present invention, wherein Francese et al. further teaches the semiconductor apparatus, wherein the output circuit comprises:
a multiplexer configured to output one sampling signal pair among the first to third sampling signal pairs as the selected sampling signal pair based on the second reception symbol (116A, based on Clock Gating and De-mux Select Logic 122A; 116B, based on Clock Gating and De-mux Select Logic 122B); and
a latch circuit configured to latch the selected sampling signal pair to generate the first reception symbol in synchronization with the first phase clock signal (118A, 118B).
Regarding Claim 18, Bartling et al., Tanabe et al., Dong, and Francese et al, as a whole, teach all the limitations of the present invention, wherein Bartling et al. further teaches the semiconductor apparatus, wherein the second receiver circuit is configured to further receive the first reception symbol, and configured to generate the second reception symbol from the input signal pair based on the first reception symbol (based on clock circuit 104).
Claim(s) 10, 11, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bartling et al. (12, 052, 335 B2), Tanabe et al. (US 5,796,301), Dong (US, 9,674,009 B2), and Francese et al. (US 9,860,087 B1), as a whole, and as applied to Claim 9, and in further view of Heineman et al. (US 8,829,990 B2).
Regarding Claim 10, Bartling et al., Tanabe et al., Dong, and Francese et al, as a whole, teach all the limitations of the present invention, wherein Tanabe et al. further teaches the semiconductor apparatus, wherein the compensation signal generation circuit comprises:
a first circuit configured to receive a first signal pair and generate a first compensation signal (received at nodes 1 and 2 of 11, which outputs Vo1+, Vcm1, and Vo1-);
a second circuit configured to receive a second signal pair and generate a second compensation signal (received at nodes 3 and 4 of 12, which outputs Vo2+, Vcm2, and Vo2-); and
an averaging circuit configured to average the voltage levels of the first compensation signal pair and the second compensation signal pair to generate the third compensation signal pair (using R3 and R4 to generate Vcm at node 7);
but does not explicitly teach a first summing circuit configured to equalize the input signal pair with the first offset to generate the first compensation signal pair; a second summing circuit configured to equalize the input signal pair with the second offset to generate the second compensation signal pair; and.
Heineman et al. teaches in Figure 12
a first summing circuit configured to receive the input signal pair and equalize the input signal pair with a first offset to generate a first signal pair (upper adder 910); and
a second summing circuit configured to receive the input signal pair and equalize the input signal pair with a second offset to generate a second signal pair (lower adder 910);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Heineman et al. with the input signals of Bartling et al., Tanabe et al., Dong, and Francese et al, as a whole, for the purpose of adding “a DC-Offset … to both PWM signals to prevent the rising and falling edges of the PWM A and PWM B signals from lining up.” Heineman et al.: Col. 10, lines 63-65.
Regarding Claim 11, Bartling et al., Tanabe et al., Dong, Francese et al, and Heineman et al., as a whole, teach all the limitations of the present invention, and further teaches wherein the receiver circuit,
wherein the input signal pair includes an input signal and a complementary input signal (Tanabe et al.: Vi1+, Vi1-; see also Heineman et al.: 502), and the first compensation signal pair includes a first compensation signal and a first complementary compensation signal (Heineman et al.: at upper and lower 910), and
wherein the first summing circuit is configured to generate the first compensation signal having a voltage level substantially equal to a voltage level of the input signal (Heineman et al.: as outputted by upper 910), and the first complementary compensation signal having a voltage level lower than a voltage level of the complementary input signal (Heineman et al.: as outputted by lower 910).
Regarding Claim 14, Bartling et al., Tanabe et al., Dong, Francese et al, and Heineman et al., as a whole, teach all the limitations of the present invention, wherein Tanabe et al. further teaches the receiver circuit, wherein the averaging circuit comprises:
a first load circuit (R3); and
a second load circuit (R4),
wherein one end of the first load circuit receives the first compensation signal pair (as connected to Vcm1), and the other end of the first load circuit is coupled to a node from which the third compensation signal pair is output (Vcm), and
wherein one end of the second load circuit receives the second compensation signal pair (as connected to Vcm2), and the other end of the second load circuit is coupled to the node from which the third compensation signal pair is output (Vcm).
Allowable Subject Matter
Claims 3, 4, 12, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior art does not disclose, teach or suggest the receiver circuit,
wherein the second summing circuit is configured to generate the second compensation signal having a voltage level lower than a voltage level of the input signal, and the second complementary compensation signal having a voltage level substantially equal to a voltage level of the complementary input signal;
in combination with all the other claimed limitations.
Claim 4 is objected to for depending from Claim 3.
Regarding Claim 12, the prior art does not disclose, teach or suggest the semiconductor apparatus,
wherein the second summing circuit is configured to generate the second compensation signal having a voltage level lower than a voltage level of the input signal, and the second complementary compensation signal having a voltage level substantially equal to a voltage level of the complementary input signal;
in combination with all the other claimed limitations.
Claim 13 is objected to for depending from Claim 12.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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/DIANA J. CHENG/Primary Examiner, Art Unit 2849