DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Applicants' communication filed on February 09, 2024. In virtue of this communication, claims 1-20 are currently presented in the instant application.
Drawings
The drawings submitted on February 09, 2024. These drawings are reviewed and accepted by the examiner.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed on February 09, 2024 and September 02, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copies have been filed on May 08, 2023.
Claim Objections
Claim 18 is objected to because of the following informalities: “The electronic device of claim 18” that depends on itself. The invention’s claims depend on claim 1; therefore, Examiner assumes claim 18 depend on claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1).
Regarding claim 1. Kim discloses an electronic device comprising:
a memory (Kim, see par. [0042]);
at least one processor, comprising processing circuitry;
display driving integrated circuitry operably coupled with the at least one processor (Kim, see par. [0021] The display device 1000 includes an application processor (AP) 1300, a plurality of display driving circuits 1201 and 1202, and a display panel 1100.); and
a display panel operably coupled with the display driving integrated circuitry, wherein the memory stores instructions causing the display driving integrated circuitry (Kim, see par. [0022] The display panel 1100 is divided into two regions I and II. For the convenience of description, the display panel 1100 is divided into two regions I and II, and the present inventive concept is not limited thereto. For example, the display panel 1100 may be divided into three or more regions. The display driving circuits 1201 and 1202 serves to control the respective regions of the display panel 1100.) to:
in response to obtaining first commands from the at least one processor, display, by providing the first commands to a register in the display driving integrated circuitry, an image through the display panel controlled using the first commands (Kim, see par. [0043] The first command pre-buffer 310 temporarily stores the first command CMD1. The first command sync controller 330 generates the first sync signal SSYNC1 based on the completion signal EXE that is an external signal. The first sync signal SSYNC1 is provided to the first command pre-buffer 310 and the second interface circuit 340. The first command pre-buffer 310 loads the first command CMD1 stored therein to the first command register 320 in response to the first sync signal SSYNC1. For example, after receiving the completion signal EXE, the first command pre-buffer 310 loads the first command CMD1 to the first command register 320. Further, after receiving the first sync signal SSYNC1, the first command pre-buffer 310 may load the first command CMD1 to the first command register 320 in synchronization with another internal sync signal (e.g., vertical sync signal Vsync). For example, after the commands CMD1 and CMD2 are transferred to (or stored in) the corresponding display driving circuits 1201 and 1202, the first command CMD1 is loaded to the first command register 320. Here, the first command signal CMD1 includes control information for operating the driving circuit according to the display driving environment. For example, the first command signal CMD1 may include various control information according to resolution of the panel, the processing method of a video signal, and the like. The first command register 320 analyzes the first command signal CMD1, and generates signals MCNT, IPCNT, and TCNT for controlling the memory controller 130, the image processor 150, and the timing controller 110. Alternatively, the first command register may store values to generate signals MCNT, IPCNT, and TCNT for controlling the memory controller 130, the image processor 150, and the timing controller 110. In this case, the command signals includes the values to generate the signals MCNT, IPCNT, and TCNT.); and
Kim does not disclose in response to obtaining second commands from the at least one processor, defer providing the second commands to the register until obtaining a designated request from the at least one processor, and display, by providing the second commands to the register based on obtaining the designated request from the at least one processor, an image through the display panel controlled using the second commands. However,
Iwamoto discloses:
in response to obtaining second commands from the at least one processor, defer providing the second commands to the register until obtaining a designated request from the at least one processor (Iwamoto, see at least par. [0037], In accordance with a slightly more detailed example of a computational hardware resource allocation system in accordance with this disclosure, a “data master” represents a hardware entity that acts as the interface for executing software to submit work to a graphics processor. There may be multiple types of data masters within a single system. There could also be multiple instances of the same type of data master associated with a single graphics processor. In tile based deferred rendering (TBDR) GPU architectures, for example, where graphics rendering may be divided into geometry and pixel phases, there may be one or more vertex data masters, one or more pixel data masters and one or more compute data masters. In immediate mode rendering GPU architectures, where graphics rendering may be grouped by draw commands, different data masters may be used for different objects (wherein each object is responsible for processing its own vertex and pixel data). As such, data masters may be considered heterogeneous in the sense each type of data master can have different characteristics for acquiring resources and being dispatched to a graphics processor.), and display, by providing the second commands to the register based on obtaining the designated request from the at least one processor, an image through the display panel controlled using the second commands (Iwamoto, see at least par. [0046], the cache/memory controller 820 may include or be coupled to one or more caches and/or memories that include instructions that, when executed by one or more processors (e.g., compute complex 810 and/or graphics unit 100), cause the processor, processors, or cores to initiate or perform some or all of the operations described above with reference to FIGS. 1-8 or below with reference to FIG. 9. Display unit 825 may be configured to read data from a frame buffer and provide a stream of pixel values for display.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with in response to obtaining second commands from the at least one processor, defer providing the second commands to the register until obtaining a designated request from the at least one processor, and display, by providing the second commands to the register based on obtaining the designated request from the at least one processor, an image through the display panel controlled using the second commands, as provided by Iwamoto. The modification of system and method for synchronizing timing of processing commands for controlling display pane that simultaneously executes multiple processes in parallel and dynamically allocate the hardware resources between. (Iwamoto, see par. [0002]).
Regarding claim 7. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), and KIM in view of Iwamoto further discloses, wherein the memory stores instructions causing the display driving integrated circuitry to:
provide, in response to obtaining the designated request, the second commands to the register (Kim, see at least par. [0055] For example, the first command sync controller 330 receives the completion signal EXE, generates and provides the first sync signal SSYNC1 to the first command pre-buffer 310 and the second interface circuit 340. The first command CMD1 stored in the first command pre-buffer 340 is transferred to the first command register 320 in response to the first sync signal SSYNC1. The second interface circuit 340 transfers the first sync signal SSYNC1 to the fourth interface circuit 342. The second command sync controller 332 receives the first sync signal SSYNC1, and generates the second sync signal SSYNC2. The second command CMD2 stored in the second command pre-buffer 312 is transferred to the second command register 322 in response to the second sync signal SSYNC2. Accordingly, the first command register 320 and the second command register 322 analyze the first command CMD1 and the second command CMD2, and generate the control signals MCNT, IPCNT, and TCNT, respectively.).
Regarding claim 8. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), KIM in view of Iwamoto further discloses wherein the memory stores instructions causing the display driving integrated circuitry to:
provide, based on a start timing of a vertical synchronization signal following a timing obtaining the designated request, the second commands to the register (Kim, see par. [0026], the first command CMD1 may be first provided to the first display driving circuit 1201, and then the second command CMD2 may be provided to the second display driving circuit 1202 with a time difference. Due to this time difference, an operation that corresponds to the first command CMD1 may be shown in the first region I that is controlled by the first display driving circuit 1201, but an operation that corresponds to the second command CMD2 need not be shown in the second region II that is controlled by the second display driving circuit 1202. That is, divided screens may be shown on the display panel 1100… 0028] To implement the above-described operation, the first display driving circuit 1201 includes a first command pre-buffer 310, shown in FIG. 4, that temporarily stores the first command CMD1. The first command CMD1 that is stored in the first command pre-buffer 310 is loaded to a first command register 320, shown in FIG. 4, after the first display driving circuit 1201 receives the completion signal EXE. Similarly, the second display driving circuit 1202 includes a second command pre-buffer 312, shown in FIG. 4, that temporarily stores the second command CMD2. The second command CMD2 that is stored in the second command pre-buffer 312 is loaded to a second command register 322, shown in FIG. 4 after the second display driving circuit 1202 receives the first sync signal SSYNC1. The descriptions thereof will be made later with reference to FIGS. 3 to 6.).
Regarding claim 10. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), KIM in view of Iwamoto further discloses wherein the memory stores instructions causing the display driving integrated circuitry to:
based on obtaining the designated request, identify whether obtaining a command indicating that a transmission of frame data from the at least one processor is started (Kim, see par. [0063] Further, through the vertical front porch periods VFP1, VFP2, and VFP3, the first command CMD1 is inputted to the first display driving circuit (hereinafter called a “master IC”) 1201, and the second command CMD2 is inputted to the second display driving circuit (hereinafter called a “slave IC”) 1202. As illustrated, the first command CMD1 is completely transmitted in the first vertical front porch period VFP1, but the second command CMD2 is transmitted through the first vertical front porch period VFP1 and the second vertical front porch period VFP2 due to the interruption in the AP 1300 of FIG. 1. After the second command CMD2 is completely transmitted, the completion signal EXE is inputted to the first display driving circuit 1201 in the third vertical front porch period VFP3. The first display driving circuit 1201, in response to the completion signal EXE, generates the first sync signal SSYNC1. The first sync signal SSYNC1 is transferred to the second display driving circuit 1202. Accordingly, the first display driving circuit 1201 and the second display driving circuit 1202 may simultaneously perform, in response to the first sync signal SSYNC1, one operation after the third frame Frame3.); and
in response to obtaining the command, provide the second commands to the register (Kim, see at least par. [0055] For example, the first command sync controller 330 receives the completion signal EXE, generates and provides the first sync signal SSYNC1 to the first command pre-buffer 310 and the second interface circuit 340. The first command CMD1 stored in the first command pre-buffer 340 is transferred to the first command register 320 in response to the first sync signal SSYNC1. The second interface circuit 340 transfers the first sync signal SSYNC1 to the fourth interface circuit 342. The second command sync controller 332 receives the first sync signal SSYNC1, and generates the second sync signal SSYNC2. The second command CMD2 stored in the second command pre-buffer 312 is transferred to the second command register 322 in response to the second sync signal SSYNC2. Accordingly, the first command register 320 and the second command register 322 analyze the first command CMD1 and the second command CMD2, and generate the control signals MCNT, IPCNT, and TCNT, respectively.).
Regarding claim 15. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), and KIM in view of Iwamoto further discloses, wherein the memory stores instructions causing the display driving integrated circuitry to:
in response to obtaining third commands from the at least one processor, defer, until obtaining another designated request from the at least one processor, providing the third commands to the register (Iwamoto, see at least par. [0037], In tile based deferred rendering (TBDR) GPU architectures, for example, where graphics rendering may be divided into geometry and pixel phases, there may be one or more vertex data masters, one or more pixel data masters and one or more compute data masters. In immediate mode rendering GPU architectures, where graphics rendering may be grouped by draw commands, different data masters may be used for different objects (wherein each object is responsible for processing its own vertex and pixel data). As such, data masters may be considered heterogeneous in the sense each type of data master can have different characteristics for acquiring resources and being dispatched to a graphics processor.); and
display, by providing the third commands to the register based on obtaining the other designated request from the at least one processor, an image through the display panel controlled using the third commands (Kim, see par. [0063] Further, through the vertical front porch periods VFP1, VFP2, and VFP3, the first command CMD1 is inputted to the first display driving circuit (hereinafter called a “master IC”) 1201, and the second command CMD2 is inputted to the second display driving circuit (hereinafter called a “slave IC”) 1202. As illustrated, the first command CMD1 is completely transmitted in the first vertical front porch period VFP1, but the second command CMD2 is transmitted through the first vertical front porch period VFP1 and the second vertical front porch period VFP2 due to the interruption in the AP 1300 of FIG. 1. After the second command CMD2 is completely transmitted, the completion signal EXE is inputted to the first display driving circuit 1201 in the third vertical front porch period VFP3. The first display driving circuit 1201, in response to the completion signal EXE, generates the first sync signal SSYNC1. The first sync signal SSYNC1 is transferred to the second display driving circuit 1202. Accordingly, the first display driving circuit 1201 and the second display driving circuit 1202 may simultaneously perform, in response to the first sync signal SSYNC1, one operation after the third frame Frame3.).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1), as applied claim 1 above, and further in view of Willt et al. (US 20030140179 A1).
Regarding claim 2. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), but KIM in view of Iwamoto does not disclose wherein the memory stores instructions causing the display driving integrated circuitry to defer providing the second commands to the register by storing the second commands in a buffer in the display driving integrated circuitry before obtaining the designated request. However, Wilt discloses:
wherein the memory stores instructions causing the display driving integrated circuitry to defer providing the second commands to the register by storing the second commands in a buffer in the display driving integrated circuitry before obtaining the designated request (Wilt, see par. [0125], The system must detect cases where a resource is requested that depends on commands earlier in the command buffer having been executed before the resource can become available. When that occurs, the thread must submit the command buffer, and begin composing another command buffer. The second command buffer can simply specify the resource, and the above-described synchronization mechanisms would accommodate the dependency.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein the memory stores instructions causing the display driving integrated circuitry to defer providing the second commands to the register by storing the second commands in a buffer in the display driving integrated circuitry before obtaining the designated request, as provided by Wilt. The modification of system and method for synchronizing timing of processing commands for controlling display pane; thereby to increasing number of applications making simultaneous use of the computational resources of the graphics processors. (Wilt, see par. [0009]).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1), further in view of Willt et al. (US 20030140179 A1), as applied claim 2 above, and further in view of LEE (US 20180217754 A1).
Regarding claim 3. KIM in view of Iwamoto and further in view of Wilt discloses the electronic device of claim 2 (as rejected above), but KIM in view of Iwamoto and further in view of Wilt does not disclose wherein an order of providing the second commands to the register is identified based on order in which the second commands are stored. However,
LEE discloses:
wherein an order of providing the second commands to the register is identified based on order in which the second commands are stored (LEE, see at least par. [0015] The controller may further register the identified dependency and priority order between the first and second commands in a queue list, and may enqueue the queue list in a tail of the queue.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein the memory stores instructions causing the display driving integrated circuitry to defer providing the second commands to the register by storing the second commands in a buffer in the display driving integrated circuitry before obtaining the designated request, as provided by LEE. The modification of system and method for synchronizing timing of processing commands for controlling display pane; thereby provide excellent stability, durability, high information access speed, and low power consumption since they have no moving parts. Examples of memory systems having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces and solid state drives (SSD) (LEE, par. [0004]).
Regarding claim 4. KIM in view of Iwamoto and further in view of Wilt discloses the electronic device of claim 2 (as rejected above), but KIM in view of Iwamoto and further in view of Wilt does not disclose wherein each of the second commands stored in the buffer includes address information, and wherein an order of providing the second commands to the register is identified based on the address information. However,
LEE discloses:
wherein each of the second commands stored in the buffer includes address information, and wherein an order of providing the second commands to the register is identified based on the address information (LEE, see par. [0088] The processor 134 may register addresses of the commands provided from the address check unit 530 in the queue list of the second queue 804, and identifies dependency and priority order among the commands enqueued in the queue list of the second queue 804 according to the identification result of the dependency and priority order of the commands provided from the address check unit 530 as well as the dependency and priority order of the command already enqueued in the queue list of the second queue 804. The addresses of the command provided from the address check unit 530 may be registered and enqueued in a tail of the second queue 804.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein each of the second commands stored in the buffer includes address information, and wherein an order of providing the second commands to the register is identified based on the address information, as provided by LEE. The modification of system and method for synchronizing timing of processing commands for controlling display pane; thereby provide excellent stability, durability, high information access speed, and low power consumption since they have no moving parts. Examples of memory systems having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces and solid state drives (SSD) (LEE, par. [0004]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1) as applied claim 1 above, and further in view of Smith (US 20120154123 A1).
Regarding claim 5. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), but KIM in view of Iwamoto does not disclose wherein each of the first commands includes a flag of a first state, and wherein each of the second commands includes a flag of a second state. However,
Smith discloses:
wherein each of the first commands includes a flag of a first state, and wherein each of the second commands includes a flag of a second state (Smith, see at least par. [0042] FIG. 8 shows a state diagram in one embodiment of a two-state command protocol according to the present invention. The tag IC control logic implements the protocol by reacting to commands received from a reader. The state diagram shows all the states that a tag may take in response to command sets issued from a reader. In the exemplary embodiment of FIG. 8, the command set for State A consists of the commands QuietA, PingIDA and ScrollIDA. Similarly, the command set for State B consists of the commands QuietB, PingIDB and ScrollIDB. These commands, which comprise the basic command set for interrogating and identifying tags, are described in detail below. States A and B are intended to be persistent states, even in the absence of power derived from the reader's RF signal, although in certain embodiments they may be temporary states. After a long period of time, at least 20 seconds but possibly hours, State B will revert to State A. Tags in State A respond to PingIDA and ScrollIDA commands but not PingIDB and ScrollIDB commands. Upon receipt of a QuietA command, a tag in State A will enter into State B. Tags in State B respond to PingIDB and ScrollIDB commands but not PingIDA or ScrollIDA commands. Upon receipt of a QuietB command, a tag in State B will enter into State A.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein each of the first commands includes a flag of a first state, and wherein each of the second commands includes a flag of a second state, as provided by Smith. The modification of system and method for synchronizing timing of processing commands for controlling display pane; thereby [0006] The present invention uses in one exemplary embodiment a protocol with two symmetric inventoried states, and provides advantages over a ready-quiet protocol. The symmetric version effectively has less state dependence by symmetrizing the quiet-ready states into two symmetrical halves, the State A and State B of the protocol. (Smith, see par. [0006]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1), as applied claim 8 above, and further in view of Kawasaki et (US 20020064384 A1).
Regarding claim 9. KIM in view of Iwamoto discloses the electronic device of claim 8 (as rejected above), but KIM in view of Iwamoto does not disclose wherein the memory stores instructions causing the display driving integrated circuitry to:
initiate providing, at a timing before a designated time interval from a start timing of the vertical synchronization signal, the second commands to the register. However,
Kawasaki discloses:
wherein the memory stores instructions causing the display driving integrated circuitry to: initiate providing, at a timing before a designated time interval from a start timing of the vertical synchronization signal, the second commands to the register (Kawasaki, see at least par. [0023] Preferably, the pre-flash emission command device further includes a timer which expires after a predetermined period of time; wherein, in the first pre-flash emission mode, the timer is started, while one of the built-in flash and the at least one external flash device is activated via the second command device to emit the low flash emission serving as the second command signal; the first command signal is transmitted to the at least one external flash device via the first command device upon expiration of the timer; and the one of the built-in flash and at least one external flash device is activated again via the second command device to emit the low flash emission, serving as the second command signal, at the same time the transmission of the first command signal to the at least one external flash device is completed.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with initiate providing, at a timing before a designated time interval from a start timing of the vertical synchronization signal, the second commands to the register, as provided by Kawasaki. The modification of system and method for synchronizing timing of processing commands for controlling display pane that that provide a multi-flash photography system in which the pre-flash emitting operation can be controlled with a high degree of energy efficiency (Kawasaki, see par. [0005]).
Claims 12, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1), as applied claim 1 above, and further in view of BAE et al. (US 20210082330 A1).
Regarding claim 12. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), but KIM in view of Iwamoto does not disclose wherein the memory stores instructions causing the display driving integrated circuitry to: provide the second commands to the register, after a designated time elapses from a timing obtaining the designated request. However,
BAE discloses:
wherein the memory stores instructions causing the display driving integrated circuitry to: provide the second commands to the register, after a designated time elapses from a timing obtaining the designated request (BAE, see at least par. [0218] In operation 1475, the display-driving circuit 320 may display the second content on the basis of the stored frame data. According to various embodiments, since the display-driving circuit 320 stores the frame data received from the first processor 310 on the basis of identification that the predetermined time has elapsed and displays the second content on the basis of the stored frame data, the display-driving circuit 320 may concurrently display all of the second content. Although not illustrated in FIG. 14, the display-driving circuit 320 may receive third content related to the second content from the first processor 310 and store the third content by further performing operation similar to operations 1440 to 1475 through interworking with the first processor 310. The third content may be displayed after the second content so as to provide animation.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein the memory stores instructions causing the display driving integrated circuitry to: provide the second commands to the register, after a designated time elapses from a timing obtaining the designated request, as provided by BAE. The modification of system and method for synchronizing timing of processing commands for controlling display pane, thereby to display content having enhanced quality by controlling the time at which frame data of the content is stored in a memory within a display-driving circuit. (BAE, see par. [0012]).
Regarding claim 16. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), and KIM in view of Iwamoto does not disclose wherein the memory stores instructions causing the display driving integrated circuitry to: provide, in response to obtaining the designated request, the second commands to the register; and provide, after a designated time elapses from obtaining the other designated request, the third commands to the register. However,
BAE discloses:
wherein the memory stores instructions causing the display driving integrated circuitry to: provide, in response to obtaining the designated request, the second commands to the register; and provide, after a designated time elapses from obtaining the other designated request, the third commands to the register (BAE, see at least par. [0218] In operation 1475, the display-driving circuit 320 may display the second content on the basis of the stored frame data. According to various embodiments, since the display-driving circuit 320 stores the frame data received from the first processor 310 on the basis of identification that the predetermined time has elapsed and displays the second content on the basis of the stored frame data, the display-driving circuit 320 may concurrently display all of the second content. Although not illustrated in FIG. 14, the display-driving circuit 320 may receive third content related to the second content from the first processor 310 and store the third content by further performing operation similar to operations 1440 to 1475 through interworking with the first processor 310. The third content may be displayed after the second content so as to provide animation.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein the memory stores instructions causing the display driving integrated circuitry to: provide, in response to obtaining the designated request, the second commands to the register; and provide, after a designated time elapses from obtaining the other designated request, the third commands to the register, as provided by BAE. The modification of system and method for synchronizing timing of processing commands for controlling display pane, thereby to display content having enhanced quality by controlling the time at which frame data of the content is stored in a memory within a display-driving circuit. (BAE, see par. [0012]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1), as applied claim 1 above, and further in view of SCHUETZ (US 20110276775 A1).
Regarding claim 14. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), and KIM in view of Iwamoto does not disclose wherein the memory stores instructions causing the display driving integrated circuitry to: defer providing the second commands to the register while providing the first commands to the register. However,
SCHUETZ discloses:
wherein the memory stores instructions causing the display driving integrated circuitry to: defer providing the second commands to the register while providing the first commands to the register (see at least par. [0014] In an embodiment of the second aspect, issuing page read commands includes issuing a first page read command to the first page buffer source, followed by issuing a second page read command to the second page buffer source after a predetermined latency period, such that the first page buffer source reads a page of data from a memory array and transfers the page of data to the data buffer of the bridge device in response to the first page read command. The bridge device sets a deferred status for the second page buffer source when the transfer of the page of data to the data buffer is initiated. In another embodiment of the second aspect, determining includes reading status registers of the bridge device indicating the ready state and the non-deferred state corresponding to each of the first page buffer source and the second page buffer source. In yet another embodiment, re-issuing includes reading the status registers of the bridge device to determine if the second page buffer source is in the ready state and in the deferred state where the second page buffer source reads a page of data from a memory array and transfers the page of data to the data buffer of the bridge device in response to the page read command. In this embodiment, the status registers of the bridge device are read to determine if the second page buffer source is in a ready state for indicating that data of the second page buffer source is stored in a data buffer of the bridge device.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein the memory stores instructions causing the display driving integrated circuitry to: defer providing the second commands to the register while providing the first commands to the register, as provided by SCHUETZ. The modification of system and method for synchronizing timing of processing commands for controlling display pane that that provides improved performance and storage capacity relative to the previously shown memory systems (SCHUETZ, see par. [0054]).
Regarding claim 19. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above), and KIM in view of Iwamoto does not disclose wherein the memory stores instructions causing the processor to: identify a request changing a resolution of an image displayed through the display panel, and
provide, based on the identification, the second commands to the display driving integrated circuitry. However,
BAE discloses:
wherein the memory stores instructions causing the processor to:
identify a request changing a resolution of an image displayed through the display panel (BAE, see at least par. [0055], The DDI 230 may also store at least part of the received image information in the memory 233, for example, on a frame by frame basis. The image processing module 235 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) with respect to at least part of the image data. According to an embodiment, the pre-processing or post-processing may be performed, for example, based at least in part on one or more characteristics of the image data or one or more characteristics of the display 210. ); and
provide, based on the identification, the second commands to the display driving integrated circuitry (BAE, see at least par. [0090] According to various embodiments, the display-driving circuit 320 may change the counter value in response to reception of the frame data from the first processor 310. For example, the display-driving circuit 320 may decrease (or increase) the counter value on the basis of identification of a predetermined command (for example, a record start command (the command of 2Ch in the MIPI standard)) on the basis of the frame data received from the first processor 310.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein the memory stores instructions causing the processor to: identify a request changing a resolution of an image displayed through the display panel, and provide, based on the identification, the second commands to the display driving integrated circuitry., as provided by BAE. The modification of system and method for synchronizing timing of processing commands for controlling display pane, thereby to display content having enhanced quality by controlling the time at which frame data of the content is stored in a memory within a display-driving circuit. (BAE, see par. [0012]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over KIM et al. (US 20160078833 A1) et al. (US 20160078833 A1) in view of Iwamoto et al. (US 20180349146 A1), as applied claim 1 above, further in view of BAE et al. (US 20210082330 A1), and further in view of Hammerstone et al. (US 10157443 B1).
Regarding claim 17. KIM in view of Iwamoto discloses electronic device of claim of claim 1 (as rejected above), and KIM in view of Iwamoto further discloses
wherein the display driving integrated circuitry (Kim, see at least par. [0029] FIG. 2 is a block diagram of a first display driving circuit and a first region of a display panel of FIG. 1 according to an exemplary embodiment of the present inventive concept) includes:
a buffer (Kim, see at least par. [0028] To implement the above-described operation, the first display driving circuit 1201 includes a first command pre-buffer 310, shown in FIG. 4, that temporarily stores the first command CMD1.); but
KIM in view of Iwamoto does not disclose a control circuit configured to identify whether a command is provided from the at least one processor to the register or to the buffer, wherein the memory stores instructions causing the display driving integrated circuitry to: provide the first commands obtained from the at least one processor to the register; and using the control circuit, defer, by storing the second commands obtained from the at least one processor in the buffer, providing the second commands to the register. However,
BAE discloses:
a control circuit configured to identify whether a command is provided from the at least one processor to the register or to the buffer, wherein the memory stores instructions causing the display driving integrated circuitry (BAE, see pars.[0104] According to various embodiments, the display-driving circuit 320 may identify the command of 2Ch from the frame data 425. The display-driving circuit 320 may change the counter value from 0 to 1 on the basis of the identification.
[0105] According to various embodiments, the display-driving circuit 320 may maintain the recording activation signal in the inactive state on the basis of identification that the counter value (1) has not reached the predetermined value (2). The display-driving circuit 320 may limit storage of the frame data 425 on the basis of maintenance of the inactive state of the recording activation signal. According to various embodiments, the display-driving circuit 320 may limit storage of the frame data 425 by discarding the frame data 425 on the basis of maintenance of the inactive state of the recording activation signal. Meanwhile, the internal memory 322 included in the display-driving circuit 320 may maintain storage of the frame data including the first content 410 due to the limit.) to: use the control circuit (BAE, see par. [0036])
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with a control circuit configured to identify whether a command is provided from the at least one processor to the register or to the buffer, wherein the memory stores instructions causing the display driving integrated circuitry to: use the control circuit, as provided by BAE. The modification of system and method for synchronizing timing of processing commands for controlling display pane, thereby to display content having enhanced quality by controlling the time at which frame data of the content is stored in a memory within a display-driving circuit. (BAE, see par. [0012]).
Kim in view of Iwamoto, and further in view of BAE does not disclose wherein the memory stores instructions causing the display driving integrated circuitry to: use the control circuit provide the first commands obtained from the at least one processor to the register; and using the control circuit, defer, by storing the second commands obtained from the at least one processor in the buffer, providing the second commands to the register. However,
Hammerstone discloses:
wherein the memory stores instructions causing the display driving integrated circuitry to: use the control circuit, provide the first commands obtained from the at least one processor to the register (Hammerstone, see col. 10, lines 55-61, Command processor 52 of GPU 14 may be configured to determine a first command in command buffer 46 during a binning operation is configured to update constant values (400). The command may include instructions to update the value of a constant, e.g., a lightweight constant. Rather than performing the update immediately and update snapshot values in state buffer 48 or in register file 50); and
using the control circuit,
defer, by storing the second commands obtained from the at least one processor in the buffer, providing the second commands to the register (Hammerstone, see col. 8, lines 34-49, GPU 14 (e.g., via command processor 52) may process the next command in command buffer 46, command 60A. Command 60A includes a deferred state load mechanism that, when processed, loads a snapshot of lightweight constant values from register file 50, including constants 0-7. The size field may include the number of constants (e.g., dwords) in the state buffer 48 and as shown is equal to eight. Further, command 60A includes an address of where the deferred state constants will be loaded. As shown in FIG. 2, this may be an address of state buffer 48. GPU 14 may then process the next command in command buffer 46, command 60B. Command 60B, when processed, is a draw command to render a graphical element. Command processor 52 of GPU 14 may determine whether the draw command is live (e.g. visible) or dead (e.g. not visible). GPU 14 may determine that there are no deferred constant updates to process.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method and apparatus of Kim, with wherein the memory stores instructions causing the display driving integrated circuitry to: use the control circuit provide the first commands obtained from the at least one processor to the register; and using the control circuit, defer, by storing the second commands obtained from the at least one processor in the buffer, providing the second commands to the register, as provided by Hammerstone. The modification of system and method for synchronizing timing of processing commands for controlling display pane, that provides efficient processing of complex graphic-related operations (Hammerstone, see col. 4, lines 36-38).
Allowable Subject Matter
Claims 6, 11, 13, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6. KIM in view of Iwamoto discloses electronic device of claim of claim 1 (as rejected above). However, limitation:
“wherein the memory stores instructions causing the display driving integrated circuitry to:
defer, while a state of a signal for controlling a timing providing the second commands to the register is a first state, providing the second commands to the register;
switch, in response to obtaining the designated request while deferring providing the second commands, the state of the signal from the first state to a second state; and
provide, in response to switching the state of the signal from the first state to the second state, the second commands to the register.”, that taken as a whole render the claims patentably distinct over prior arts.
Regarding claim 11. KIM in view of Iwamoto discloses the electronic device of claim 1 (as rejected above). However, the limitations:
wherein the memory stores instructions causing the display driving integrated circuitry to:
based on obtaining the designated request, identify whether a number of commands indicating that a transmission of frame data is started reaches a designated number,
obtaining the command from the at least one processor; and
provide, based on a start timing of a vertical synchronization signal following a timing identifying that the number of commands reaches the designated number, the second commands to the register.”, that taken as a whole render the claims patentably distinct over prior arts.
Regarding claim 13. KIM in view of Iwamoto discloses electronic device of claim of claim 1 (as rejected above). However, the limitations: wherein the memory stores instructions causing the display driving integrated circuitry to:
based on obtaining the designated request, identify whether a number of commands indicating that a transmission of frame data is started reaches a designated number,
obtaining the command from the at least one processor; and
provide, after a designated time elapses from identifying that the identified number reaches the designated number, the second commands to the register.”, that taken as a whole render the claims patentably distinct over prior arts.
Regarding claim 18. KIM discloses electronic device of claim of claim 18 (as rejected above). However, the limitations:
“wherein the memory stores instructions causing the display driving integrated circuitry to:
provide a command provided from the at least one processor or a command provided from the buffer to the register,
wherein each of the first commands is provided through the control circuit and the other control circuit from the at least one processor to the register, wherein each of the second commands obtained from the at least one processor is stored in the buffer through the control circuit, and
wherein the each of the second commands stored in the buffer is provided through the other control circuit to the register, based on the designated request.”, that taken as a whole render the claims patentably distinct over prior arts.
Regarding claim 20. KIM discloses electronic device of claim of claim 1 (as rejected above). However, the limitations:
“wherein the memory stores instructions causing the display driving integrated circuitry to:
defer, by storing the second commands in a buffer in the display driving integrated circuitry before obtaining the designated request, providing the second commands to the register;
provide, based on obtaining the designated request, the second commands stored in the buffer to the register;
provide, in response to obtaining the designated request, a first signal indicating ceasing obtaining commands to be stored in the buffer from the at least one processor, to the at least one processor; and
provide, in response to identifying that providing the second commands to the register is completed, a second signal indicating resuming obtaining the commands to be stored in the buffer from the at least one processor, to the at least one processor.”, that taken as a whole render the claims patentably distinct over prior arts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM THANH THI TRAN whose telephone number is (571)270-1408. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/KIM THANH T TRAN/Examiner, Art Unit 2615
/JAMES A THOMPSON/Primary Examiner, Art Unit 2615
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