CTNF 18/437,906 CTNF 101406 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings 06-36 The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the fourth semiconductor region must be shown or the feature(s) canceled from the claim 7. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Katou et al. (US 11127854 B2) in view of Ichinoseki et al. (US 11322612 B2) and Fujino (US 20210296454 A1) . Regarding claim 1 , Katou et al. disclose a semiconductor device (1), comprising: a first electrode (20, Fig. 1A); a first semiconductor region (11, Fig. 1A) located on the first electrode, the first semiconductor region being of a first conductivity type (n-type, paragraph 14); a second semiconductor region (13, Fig. 1A) located on the first semiconductor region (11), the second semiconductor region being of a second conductivity type (p-type, paragraph 14); a third semiconductor region (15, Fig. 1A) located on the second semiconductor region (13), the third semiconductor region being of the first conductivity type (n-type, paragraph 14); a second electrode (40, Fig. 1A) located on the third semiconductor region (13), the second electrode being electrically connected with the third semiconductor region; a third electrode (40, Fig. 1A, same electrode but different view) including a first electrode region (region of electrode 40) extending along a second direction (Y) perpendicular to a first direction (Z), the first electrode region being arranged with the second semiconductor region (13) in a third direction, the first direction being from the first electrode toward the second electrode, the third direction (X) being perpendicular to the first direction and crossing the second direction (Fig. 1A), a second electrode region (region of electrode 40, can be oriented differently based on claim) extending along the third direction, the second electrode region being arranged with the second semiconductor region in the second direction, and a third electrode region (region of 40, corresponds to same region as in the claim but different orientation, Fig. 1) connecting the first electrode region and the second electrode region (Fig. 3A, Fig. 5A, electrode regions are connected, corresponds to Fig. 2 of the application); a first insulating part (43) including a first insulating region including a first insulating portion (left portion of 43, Fig. 1A) located between the second semiconductor region (13) and the first electrode region (40) in the third direction, and a second insulating portion (bottom part of 43, Fig. 1A) located between the first semiconductor region (11) and the first electrode region (40) in the first direction, a second insulating region (43, corresponds to same region as in the claim but different orientation) including a third insulating portion (43, corresponds to same region as in the claim, but different orientation) located between the second semiconductor region (13) and the second electrode region (40, different electrode but same structure as in the claimed invention) in the second direction, and a fourth insulating portion (bottom of 43, corresponds to same region as in the claim, but different orientation) located between the first semiconductor region (11) and the second electrode region (40, different electrode but same structure as in the claimed invention) in the first direction, and a third insulating region (bottom portion of 43) connecting the first insulating region (right region of 43 separating the p-type area from the electrode) and the second insulating region (bottom region 43 separating the n-type area from the electrode, Fig. 1A), the third insulating region including a fourth electrode (50, Fig. 1A) arranged with the first semiconductor region (11) and the third electrode (40) in the second and third directions; and a second insulating part (53, Fig. 1A) located between the fourth electrode (50) and the first semiconductor region (11) and between the fourth electrode (50) and the third electrode (40) in the second and third directions. However, Katou et al. do not disclose a fifth insulating portion located between the second semiconductor region and the second electrode region in a fourth direction, the fourth direction being perpendicular to the first direction and crossing the second and third directions, and a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction; a lower end of the sixth insulating portion being positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion. However, Ichinoseki et al disclose a fifth insulating portion (10a, right side of insulating portion, Fig. 3) located between the second semiconductor region (2) and the second electrode region (10) in a fourth direction (D4), the fourth direction being perpendicular to the first direction and crossing the second and third directions (Fig. 4). Neither Katou nor Ichinoseki disclose sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction, and a lower end of the sixth insulating portion being positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion. However, Fujino disclose sixth insulating portion (22, Fig. 2) located between the first semiconductor region (12) and the third electrode region (24) in the first direction, and a lower end of the sixth insulating portion (bottom of insulating portion 22, Fig.2) being positioned lower than a lower end of the second insulating portion (26a1) and a lower end of the fourth insulating portion (26b1. Fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou in view of Ichinoseki and Fujino such that a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction, and a lower end of the sixth insulating portion being positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion. Doing so would optimize electric field distribution, improve breakdown voltage, and reduce parasitic capacitance. Regarding claim 2 , Katou and Ichinoseki are discussed above. Neither reference discloses a thickness in the first direction of the sixth insulating portion is greater than a thickness in the first direction of the second insulating portion and a thickness in the first direction of the fourth insulating portion. However, Fujino discloses a thickness in the first direction of the sixth insulating portion (22, Fig. 2 )is greater than a thickness in the first direction of the second insulating portion (26a1) and a thickness in the first direction of the fourth insulating portion (26b1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou in view of Ichinoseki and Fujino such that a thickness in the first direction of the sixth insulating portion is greater than a thickness in the first direction of the second insulating portion and a thickness in the first direction of the fourth insulating portion. Doing so would optimize electric field distribution, improve breakdown voltage, and reduce parasitic capacitance. Regarding claim 3 , Katou, Ichinoseki, and Fujino are discussed above. Ichonoseki discloses a fourth direction (D4, Fig. 3). Fujino further discloses the thickness in the first direction (Z) of the sixth insulating portion (22, Fig. 1) is greater than a thickness in the fourth direction of the fifth insulating portion (34, Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou in view of Ichinoseki and Fujino such that the thickness in the first direction of the sixth insulating portion is greater than a thickness in the fourth direction of the fifth insulating portion. Doing so would maintain device reliability and control electric fields. Regarding claim 4 , Katou and Ichinoseki are discussed above. None of these references disclose the thickness in the first direction of the sixth insulating portion is greater than half of a length in the first direction of the third electrode region. However, Fujino discloses the thickness in the first direction (Z) of the sixth insulating portion (22, Fig. 1) is greater than half of a length in the first direction (Fig. 1 visibly shows that sixth insulating region is longer in length than the third electrode region, 62a) of the third electrode region (region of 62a, Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou and Ichinoseki in view of Fujino such that the thickness in the first direction of the sixth insulating portion is greater than half of a length in the first direction of the third electrode region. Doing so would ensure sufficient electrical isolation and control electric field intensity. Regarding claim 5 , Katou discloses a lower end of the third electrode (region of 40, corresponds to same region as in the claim but different orientation, Fig. 1) region is positioned lower than a lower end of the first electrode region (region of electrode 40) and a lower end of the second electrode region (region of electrode 40, can be oriented differently based on claim). It is within ordinary skill for one in the art to rearrange the third electrode region such that it is positioned lower than a lower end of the first and second electrode region. In re Japikse, 181 F.2d 2019, 86 USPQ70 (CCPA 1950). Regarding claim 6 , the lower end of the third electrode region (region of 40, Fig. 1A) is positioned higher than a lower end of the fourth electrode (50, Fig. 1A). Regarding claim 8 , Katou discloses a first connection part (SC, Fig. 1) located between the third insulating region (right region of 43) and the second insulating part (53) in the second and third directions, the first connection part electrically connecting the second electrode and the second semiconductor region. However, neither Katou, Ichinoseki, nor Fujino disclose a second connection part located between the third insulating region and the first connection part in the fourth direction, the second connection part electrically connecting the second electrode and the second semiconductor region. However, it is within the routine skill level for one in the art to duplicate a second connection part. The mere duplication of parts has no patentable significance unlcess a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Regarding claim 11 , Katou discloses a lower end of the second insulating portion (bottom part of 43, Fig. 1A), a lower end of the fourth insulating portion (bottom of 43, corresponds to same region as in the claim, but different orientation). However, Katou does not disclose a lower end of the sixth insulating portion each are positioned higher than a center between an upper end of the fourth electrode and a lower end of the fourth electrode. Ichinoseki discloses an insulating portion (bottom part of 10a, Fig. 2) positioned higher than a center between an upper end of the fourth electrode (12) and a lower end of the fourth electrode (Fig. 2). Fujino discloses sixth insulating portion (22, Fig. 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou and Ichinoseki in view of Fujino such that the insulating portion each are positioned higher than a center between an upper end of the fourth electrode and a lower end of the fourth electrode. Doing so would enhance breakdown voltage and reduce on-resistance . 07-21-aia AIA Claim s 7, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Katou et al. (US 11127854 B2) in view of Ichinoseki et al. (US 11322612 B2) and Fujino (US 20210296454 A1) as applied to claim 1 above, in further view of Kiyosawa (US 20240332415 A1) . Regarding claim 7 , Katou, Ichinoseki, and Fujino are discussed above. Fujino discloses the sixth insulating portion (22, Fig. 1). However, none of the prior references disclose a fourth semiconductor region located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type. However, Kiyosawa disclose a fourth semiconductor region (55, Fig. 1) located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type (p-type, Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou, Ichinoseki, Fujino in view of Kiyosawa such that a fourth semiconductor region is located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type. Doing so would reduce breakdown voltage in the depletion layer. Regarding claim 9 , Katou, Ichinoseki, and Fujino are discussed above. Katou discloses a third electrode region (40, Fig. 1A). Ichinoseki discloses a fourth direction (D4). None of the prior references disclose a width in the fourth direction of the sixth insulating portion is less than a width in the fourth direction of the third electrode region. However, Kiyosawa disclose a fourth semiconductor region (55, Fig. 1) located under the sixth insulating portion. It is within the routine skill level for one in the art to adjust the sixth insulating portion such that the width is less than a width in the fourth direction of the third electrode region. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou, Ichinoseki, Fujino in view of Kiyosawa such that a width in the fourth direction of the sixth insulating portion is less than a width in the fourth direction of the third electrode region. Doing so would reduce switching losses and optimize trench filling. Regarding claim 10 , Katou, Ichinoseki, and Fujino are discussed above. Katou discloses a third electrode region (40, Fig. 1A). Ichinoseki discloses a fourth direction (D4). None of the prior references disclose a width in the fourth direction of the sixth insulating portion is equal to a width in the fourth direction of the third electrode region. However, Kiyosawa disclose a fourth semiconductor region (55, Fig. 1) located under the sixth insulating portion. It is within the routine skill level for one in the art to adjust the width in the fourth direction of the sixth insulating portion is equal to a width in the fourth direction of the third electrode region. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Katou, Ichinoseki, Fujino in view of Kiyosawa such that a width in the fourth direction of the sixth insulating portion is equal to a width in the fourth direction of the third electrode region. Doing so would optimize field plate shielding and ensure fabrication reliability. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVE PHAN/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/437,906 Page 2 Art Unit: 2817 Application/Control Number: 18/437,906 Page 3 Art Unit: 2817 Application/Control Number: 18/437,906 Page 4 Art Unit: 2817 Application/Control Number: 18/437,906 Page 5 Art Unit: 2817 Application/Control Number: 18/437,906 Page 6 Art Unit: 2817 Application/Control Number: 18/437,906 Page 7 Art Unit: 2817 Application/Control Number: 18/437,906 Page 8 Art Unit: 2817 Application/Control Number: 18/437,906 Page 9 Art Unit: 2817 Application/Control Number: 18/437,906 Page 10 Art Unit: 2817 Application/Control Number: 18/437,906 Page 11 Art Unit: 2817 Application/Control Number: 18/437,906 Page 12 Art Unit: 2817
Prosecution Insights