DETAILED ACTION
Claims 1-3, 5-14, 16-18, 20, 23-27 are pending in the case. Claims 4, 15, 19, 21-22 are canceled claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The replacement drawings for Figures 1–6pm have been reviewed and entered.
Specification
The amendments to the title, abstract, and specification have been reviewed and entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9-10, 12-14, 16-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ferguson (US20220019437A1) in view of Neuman (US7363440B1) in further view of Childers et al (US5790894A, herein Childers).
Regarding Claim 9, Ferguson teaches an electronic processor (FIG. 4), comprising: a register bank, including:
a first plurality of without-reset registers (FIG. 2 and [0043-0044]: a register file in which the individual registers, R0 - Rm, do not have a reset input);
a write input coupled to the first plurality of without-reset registers (FIG. 2: write data input 42);
a write-enable input coupled to the first plurality of without-reset registers (FIG. 2 and [0044]: each register has a write enable input 400 - 40m); and
a write-address input coupled to the first plurality of without-reset registers (FIG. 2 and [0044-0050]: write address is supplied to write logic 180 via "WRITE-ADDRESS", where the address is decoded and sent to switch circuit 47. The switch circuit receives a clock signal 43 and a control value 45. When the control value is set, the switch circuit 47 connects the clock signal to the write enable input of the corresponding registers based on the write-address decoded.), wherein, the register bank has a plurality of operating modes including an initialization mode of operation ([0014]: a data cleansing mode) and a write mode of operation ([0013]: a normal mode of operation; [0050]: information on the write data bus will be written only into the register which is selected by the appropriate write address in normal operation), and
in the initialization mode of operation ([0014]: a data cleansing mode), the register bank responds to receipt of a write-enable signal on the write-enable input (FIG. 2 and [0045]: data is cleansed using a signal (write-enable signal) which causes all of the write enable inputs of the registers to be activated at the same time. This signal may for example be the edge of a clock signal which is controlling operation of the processing unit) by sequentially storing initialization data received on the write input into a register of the first plurality of without-reset registers based on a write-address signal received on the write-address input (FIG. 2 and [0044-0050] teach when the control value 45 is set, the switch circuit 47, connects the clock signal 43 (write-address signal) to the write enable input of each register (based on the write-address input) to cause all registers to read in data (initialization data) from the write data bus 42 (write data input) into the write inputs of the registers.); and
control circuitry (FIGS. 2 and 4: combination of clock 3, control value 45 and switch circuit 47) coupled to a register bank (FIGS. 2 and 4: register file is comprised of registers, R0 - Rm,), wherein the control circuitry, in operation, generates a control signal (FIGS. 2 and 4: control signal generated by the control value 45 and sent to the switch circuit 47), the write-enable signal (FIGS. 2, 4 and [0034]: write enable signals may be simultaneously asserted under the control of a clock signal which is provided from a clock) and the write-address signal (FIGS. 2, 4 and [0045]: when the control value 45 is set, the switch circuit 47 connects the clock signal 43 (write-address signal) to the write enable input of each register).
However, Ferguson does not explicitly teach a multiplexer with a plurality of data inputs, including a first input for operating data signals and a second input for initialization data signals. Ferguson also does not explicitly teach the multiplexer having a control input that receives a control signal. Ferguson also does not explicitly teach the multiplexer having an output coupled to the write input of the register bank where one of the plurality of data inputs of the multiplexer is coupled to the output of the multiplexer.
Neuman teaches a multiplexer (FIG. 4: select multiplexers 436), having:
a plurality of data inputs including:
a first data input, which, in operation, receives sensor data signals (FIG. 4: access address 424, read enable 428, write enable 430, data in 434);
a second data input, which, in operation, receives initialization data signals (FIG. 4: force enable 432);
a control input coupled to the control circuitry, wherein, in operation, the control input receives the control signal (FIG. 4: select access 426 (control signal) which is select enable 408 (control signal) from control scan chain 405 (control circuitry) is shown as an input to the multiplexers 436); and
an output coupled to the write input of the register bank (FIG. 4: data-in 444), wherein the multiplexer, in operation, couples one of the plurality of data inputs of the multiplexer to the output of the multiplexer based on the control signal (FIG. 4: Inputs of the multiplexers 436 are manipulated based on select access 426 (control signal), and outputted to the SRAM 404 (register bank) as the inputs - address 438, byte write enables 440, read access control 442, and data-in 444).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified the electronic processor taught by Ferguson to include a multiplexer with a plurality of data inputs, as well as a control input and an output coupled to the write input of the register bank. Making these modifications would provide the ability for the processor to be able to select and supply input data to the register bank, whether it be initialization data or operating data, based on the control signal supplied.
The combination thus far does not explicitly teach a multiplexer having data inputs coupled to an ALU, and a reference node.
Childers teaches a data input of a multiplexer coupled to a reference node of the electronic processor (FIG. 4: multiplexer 41 takes a data input 43, which is connected to ground 39).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified the electronic processor taught by the combination of Ferguson and Neuman to include a third data input of a multiplexer coupled to a reference node of the electronic processor. Making this modification would allow for the ability to generate the initialization data for the initialization mode of operation from the reference node, ground or power, rather than sending initialization data through a dedicated reset line. Additionally, the presence of ground and power, and the ability to flexibly connect one to an input line of the multiplexer, will allow for initialization data, whether it be 0s or 1s, respectively, to be already incorporated into the processor. This provides the advantage of not needing to send initialization data from another source, or connecting another component to provide initialization data.
The current multiplexer taught by the combination of Ferguson and Neuman and teaches a multiplexer that has a plurality of data inputs which are used to forward data to the register bank. One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified the multiplexer taught by the combination of Ferguson and Neuman to include data inputs to the arithmetic-logic circuitry (ALU), and a reference node. It would have been obvious for one of ordinary skill in the art to take a multiplexer that has a plurality of inputs, and connect components, such as an ALU, which performs operations and outputs data to registers, and a reference node, which can provide initialization data, as additional data inputs. Doing so would allow for use of a foundational piece of hardware, a multiplexer, to select one of multiple sources to write to the register bank, expanding the types of data the electronic processor as a whole can process.
Regarding Claim 1, it’s rejected for the same reasons set forth above in claim 9.
Regarding Claim 2, Ferguson teaches the register bank according to claim 1, wherein in the write mode of operation ([0013]: a normal mode of operation; [0050]: information on the write data bus will be written only into the register which is selected by the appropriate write address in normal operation), the register bank responds to receipt of a write-enable signal on the write-enable input by storing operating data received on the write input into a register of the first plurality of without-reset registers ([0032-0033]: the write enable signal of a respective one of the registers is asserted to cause operational data values to be written to that register from the write data path (write input). An address (write-address) indicated by a computer executable instruction is decoded by the processor for generating the write enable signal in the normal mode of operation, wherein the operational data values are indicated by the computer executable instructions executed by the processor.) based on a write-address signal received on the write-address input (FIG. 2 and [0044-0050] teach when the control value 45 is set, the switch circuit 47, connects the clock signal 43 (write-address signal) to the write enable input of each register based on the write-address decoded (write-address input).
Regarding Claim 3, Ferguson teaches the register bank according to claim 1, comprising:
a first read address input (FIGS. 2, 4 and [0044]: Each register is associated with logic circuitry 48 which receives a decoded read address (See FIG. 4: “RA”) to determine from which register data is to be read on to the read data bus 50.); and
a first read output (FIG. 2 and [0044]: a read data port 460 . . . 46m), wherein
the plurality of operating modes includes a read mode of operation ([0049-0050]: in the normal operation mode, when the read decode logic 182 decodes read addresses indicated in the decoded instruction to access data), and in the read mode of operation, the register bank responds to receipt of a read-address on the first read address input by generating an output on the first read output based on data stored in a register of the first plurality of without-reset registers corresponding to the read-address on the first read address input (FIG. 2 and [0044]: read addresses are supplied from read decode logic 182 and sent to logic circuitry 48 which receives a decoded read address to determine from which register data is to be read on to the read data bus 50.).
Regarding Claim 5, Ferguson teaches the register bank according to claim 1, wherein each register of the first plurality of without-reset registers comprises a plurality of without-reset memory elements ([0041]: a register file comprising registers without reset inputs, which enables the register to be constructed from smaller flip-flops; Flip-flops are basic memory elements of digital circuits).
Regarding Claim 6, Ferguson teaches the register bank of claim 5, wherein the without-reset memory elements comprise without-reset flip-flops ([0041]: a register file comprising registers without reset inputs, which enables the register to be constructed from smaller flip-flops).
Regarding Claim 7, Ferguson teaches the register bank according to claim 1, comprising:
decoding circuitry (FIG. 2: the combination of write logic 180 and switch circuit 47) coupled to the write-address input (FIG. 2 and [0044-0050]: write address is supplied to write logic 180 via "WRITE-ADDRESS", where the address is decoded and sent to switch circuit 47. The switch circuit receives a clock signal 43 and a control value 45. When the control value is set, the switch circuit 47 connects the clock signal to the write enable input of the corresponding registers based on the write-address decoded.) and to a write-enable input (FIG. 2: write enable inputs 400 - 40m receive a write enable signal from the switch circuitry 47),
wherein the decoding circuitry, in operation, selectively enables registers of a first plurality of without-reset registers based on a write-enable signal on a write-enable input and a write-address signal on the write-address input (FIG. 2 and [0044-0045]: each register has a write enable input 400 - 40m which, when enabled (by a write-enable signal), causes data on the write data bus to be written into that register. The write inputs are selectively enabled by write addresses supplied from write logic 180. The control value 45, which may be a single bit, controls the operation of the switch circuit 47. When the control value is set, the switch circuit 47 connects the clock signal 43 (write-address signal) to the write enable input of registers (based on the write-address input)).
Regarding Claim 10, the combination of Ferguson and Neuman teaches the electronic processor according to claim 9 and a multiplexer with a plurality of data inputs.
Ferguson also teaches an instruction register having a plurality of memory registers, wherein the instruction register, in operation, stores instructions executable by the electronic processor (FIG 3: a shared instruction memory 12 common to the plurality of threads; a shared data memory 22 that is also common to the plurality of threads);
load-and-store circuitry (LSU) having a plurality of memory registers, wherein the LSU, in operation, stores operating data (FIG. 4 and [0050]: load store unit 184 holds a result of the operation which has been carried out in the processing pipeline); and
arithmetic-logic circuitry (ALU), which, in operation, performs arithmetic operations (FIG. 4 and [0048]: Other stages in the pipeline may also be able to write values to the register file, for example arithmetic units in the execution pipeline.).
This will result in the electronic processor of claim 9 including an instruction register storing instructions, load-and-store circuitry (LSU) that stores operating data and arithmetic-logic circuitry (ALU) that performs arithmetic operations, as well as a multiplexer that has a plurality of data inputs.
However, the combination thus far does not explicitly teach a multiplexer having data inputs coupled to an ALU, an LSU and a reference node.
Childers teaches a data input of a multiplexer coupled to a reference node of the electronic processor (FIG. 4: multiplexer 41 takes a data input 43, which is connected to ground 39).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified the electronic processor taught by the combination of Ferguson and Neuman to include a third data input of a multiplexer coupled to a reference node of the electronic processor. Making this modification would allow for the ability to generate the initialization data for the initialization mode of operation from the reference node, ground or power, rather than sending initialization data through a dedicated reset line. Additionally, the presence of ground and power, and the ability to flexibly connect one to an input line of the multiplexer, will allow for initialization data, whether it be 0s or 1s, respectively, to be already incorporated into the processor. This provides the advantage of not needing to send initialization data from another source, or connecting another component to provide initialization data.
The current multiplexer taught by the combination of Ferguson and Neuman and teaches a multiplexer that has a plurality of data inputs which are used to forward data to the register bank. One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified the multiplexer taught by the combination of Ferguson and Neuman to include data inputs to the arithmetic-logic circuitry (ALU), the load-and-store circuitry (LSU) and a reference node. It would have been obvious for one of ordinary skill in the art to take a multiplexer that has a plurality of inputs, and connect components, such as an ALU, which performs operations and outputs data to registers, an LSU, which loads data from memory into registers, and a reference node, which can provide initialization data, as additional data inputs. Doing so would allow for use of a foundational piece of hardware, a multiplexer, to select one of multiple sources to write to the register bank, expanding the types of data the electronic processor as a whole can process.
Regarding Claim 12, it’s rejected for the same reasons set forth above in claim 9.
Regarding Claim 13, Ferguson teaches the method according to claim 12, comprising: operating the register bank in the write mode of operation ([0013]: a normal mode of operation; [0050]: information on the write data bus will be written only into the register which is selected by the appropriate write address in normal operation); and
responding to receipt of a write-enable signal by the register bank during the write mode of operation by storing operating data into a register of the plurality of without-reset registers ([0032-0033]: the write enable signal of a respective one of the registers is asserted to cause operational data values to be written to that register from the write data path. An address (write-address signal) indicated by a computer executable instruction is decoded and to be executed by the processor for generating the write enable signal in the normal mode of operation, wherein the operational data values are indicated by the computer executable instructions executed by the processor.) based on a write-address signal received by the register bank (FIG. 2 and [0044-0050] teach when the control value 45 is set, the switch circuit 47, connects the clock signal 43 (write-address signal) to the write enable input of each register based on the write-address decoded.). As for the operating data comprises sensor data or arithmetic logic data, it’s taught by the Childers as showing in Claim 9.
Regarding Claim 14, Ferguson teaches the method of claim 12, wherein the plurality of operational modes includes a read mode of operation ([0049-0050]: in the normal operation mode, when the read decode logic 182 decodes read addresses indicated in the decoded instruction to access data), the method comprising: operating the register bank in the read mode of operation; and
responding to receipt of a read-address by the register bank by generating an output based on data stored in a register of the plurality of without-reset registers corresponding to the read-address (FIG. 2 and [0044]: read addresses are supplied from read decode logic 182 and sent to logic circuitry 48 which receives a decoded read address to determine from which register data is to be read on to the read data bus 50.).
Regarding Claim 16, Ferguson teaches the method of claim 12, comprising: selectively enabling registers of the plurality of without-reset registers based on the write-enable signal and the received write-address (FIG. 2 and [0044-0050]: write address is supplied to write logic 180 via "WRITE-ADDRESS", where the address is decoded and sent to switch circuit 47. The switch circuit receives a clock signal 43 and a control value 45. When the control value is set, the switch circuit 47 connects the clock signal to the write enable input of the corresponding registers based on the write-address decoded. The write inputs are selectively enabled by write addresses supplied from write logic 180.).
Regarding Claim 17, Ferguson teaches the method of claim 12, comprising: receiving a reset signal and responding to the reset signal by operating the register bank in the initialization mode of operation (FIG. 2 and [0045]: to cleanse the data from the registers is achieved by using a signal which causes all of the write enable inputs 400 - 40m of the registers to be activated at the same time. This signal may for example be the edge of a clock signal which is controlling operation of the processing unit. FIG. 2 illustrates a clock 3 which provides a clock signal 43 having rising and falling edges.).
Regarding Claims 18 and 20, they’re rejected for the same reasons set forth above in claim 9.
Claims 23-27 are rejected under 35 U.S.C. § 103 as unpatentable over Ferguson in view of Neuman, further in view of Childers, and additionally in view of Sidman (U.S. Pat. No. 5,680,641).
Regarding Claim 23, Ferguson teaches a clock, which, in operation, generates a clock signal ([0034] and [0045]);
The combination of the prior art did teach implementing a finish state machine (FSM) that generates a write-enable signal, a write-address signal, and a select signal based on a state of the FSM and the clock signal; and controls the multiplexer based on the select signal.
However, Sadman teaches a logic block which can be a simple state machine that controls signals includes write-enable signal, write-address and select signal and controls the multiplexer (see abstract and Fig. 3, 135).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have modified the electronic processor taught by Ferguson, Neuman and Childers to include a logic FSM to controls the signals, for the purpose of implementing efficiency and reliable timing. An FSM yields deterministic timing and clear cycle-by-cycle behavior that facilitate meeting timing closure and synchronous design constraints.
Regarding Claims 24-27, they are rejected for the same reasons set forth above in claim 23.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not explicitly teach the decoder circuitry comprising of a plurality of AND logic gates each having a first input coupled to respective outputs of the address decoder and a second input coupled to the write-enable input of the register bank, and each register of the plurality of without-reset registers has a respective register write-enable input coupled an output of a respective AND logic gate of the plurality of AND logic gates.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not explicitly teach one or more sensors coupled to the LSU, wherein the LSU, in operation, stores data generated by the one or more sensors.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181