DETAILED ACTION
This office action is in response to RCE communication filed on 02/03/2026. Claims 1, 4, 9, and 16 have been amended. Claim 12 has been canceled. Claims 21 and 22 have been added. Claims 1-11 and 13-22 are pending on this application.
Response to Arguments
2. Applicant’s arguments with respect to claims 1, 9 and 20 have been considered but are moot because the new ground of rejection (by Wakamatsu et al. Pub. No. 2005/0104626) does not rely on reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 9-11, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wakamatsu et al. Pub. No. 2005/0104626.
Regarding claim 9. Fig. 2 of Wakamatsu et al. discloses a method, comprising: driving output nodes (OUTP, OUTN) of a latch (M7….M12) in a comparator (Fig. 2; paragraph 0018) to a rail voltage (VDD) during a reset mode (reset mode of M9; M9 is on); providing, during the reset mod (reset mode of M9) an amplified signal (output signal of amplifier stage M1…M6) to the output nodes (OUTP, OUTN nodes) using output transistors (M5 and M6) in a preamplifier (amplifier stage M1…M6) in the comparator (Fig.2), wherein each of the output transistors (M5 and M6) in the preamplifier(M1…M6) is directly connected to a respective one of the output nodes (OUTP, OUTN) , and wherein at least one of the output transistors (M6, M6) is included in a current mirror (M3-M5 and M4-M6) defined in the preamplifier (M1…M6); generating, during an active mode of the latch ( M9 is off), a valid output at the output nodes (OUTP, OUTN nodes ) using latch transistors in the latch (M7…M12) ; and driving the output nodes (OUTP, OUTN) to the valid output using the output transistors (M7…M12) during the active mode (M9 is off).
Regarding claim 10. The method of claim 9, Fig. 2 further discloses wherein generating the valid output (OUTP, OUTN) using the latch transistors (M7….M12) and driving the output nodes (OUTP, OUTN nodes) using the output transistors (M7….M12) is performed at least partially during an overlapping time period (see Fig. 4B).
Regarding claim 11. The method of claim 9, Fig. 2 further discloses wherein, for a time period (CLK) when the latch (M7-M12) is in the active mode (M9 is off) , each of the output nodes (OUTP and OUTN nodes ) of the latch (M7…M12) are charged by two parallel current paths (parallel current paths M11-M7 and M12-M8) formed by one of the output transistors (one of M5 or M6) in the preamplifier (M1…M6) and one of the latch transistors (one of M7, M8, M11, M12) in the latch (M7…M12).
Regarding claim 16. Fig. 2 of Wakamatsu et al. a comparator (paragraph 0018), comprising: an amplifier (M1…M6) configured to convert input voltages (INP, INN) into currents (output currents of M5 and M6); and a latch (M7…M12) configured to store an output (OUTP, OUTN) of the comparator (Fig. 2) based on the currents (currents of M5 and M6) ,wherein a first transistor (M7) in the latch (M7-12) and a second transistor (M6) in the amplifier (M1-M6) work together to drive an output node (OUTN) of the latch (M7-M12) when the latch (M1-M7) is in an active mode (M9 is off) , wherein the second transistor (M6) drives the output node (OUTN node) in both the active mode and a reset mode of the latch (on/off of M9 in M7…M12) , wherein the second transistor (M6) is included in a current mirror (M4-M6) defined in the amplifier (M1…M6), and wherein the second transistor (M6) is directly connected to the output node (OUTN node).
Regarding claim 17. The comparator of claim 16, Fig. 2 further discloses wherein, when the latch enters the active mode (M9 is off), the output node of the latch (OUTN) is charged by two parallel current paths (current paths of M6 and current path of M11) formed by the first transistor (M11) in the latch (M7…M12) and the second transistor (M6) in the amplifier (M1…M6).
Regarding claim 18. The comparator of claim 16, Fig. 2 further discloses wherein a third transistor (M12) in the latch (M7…M12) and a fourth transistor (M5) in the amplifier (M1…M6) work together to drive a second output node (OUTP node) of the latch (M7…M12) when the latch is in the active mode (active mode of M7-M12 when M9 is off).
Regarding claim 19. The comparator of claim 18, Fig. 2 further discloses wherein, when the latch (M9 is off) enters the active mode (active mode of M7…M12 when M9 is off), the second output node (OUTP) of the latch (M7…M12) is charged by two parallel current paths (parallel current paths M5 and M12) formed by the third transistor (M12) in the latch (M7…M12) and the fourth transistor (M5) in the amplifier M1…M6).
Regarding claim 20. The comparator of claim 19, Fig. 2 further discloses wherein the fourth transistor (M5) in the amplifier (M1…M6) is directly connected to the second output node (OUTP node) in the latch (M7…M12).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-6 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wakamatsu et al. Pub. No. 2005/0104626 in view of Agrawal Pub. No. 2019/0207562.
Regarding claim 1. Fig. 2 of Wakamatsu et al. discloses a comparator latch (paragraph 0018) comprising: a preamplifier stage (M1…M6) configured to receive and amplify input signals (INP, INN) ; and a latch stage (M7…M12) configured to store an output (OUTP, OUTN) of the comparator latch (Fig. 2) ,wherein a first transistor (M11) in the latch stage (M7…M12) and a second transistor (M6) in the preamplifier stage (M1…M6) work together to drive an output node (OUTN node) of the latch stage (M7…M12) when the latch stage (M7-M12) is in an active mode (M9 is off), wherein the second transistor (M6) drives the output node (OUTN node) in both the active mode (M9 is off) and a reset mode (M9 is on) of the latch stage (M7…M12) , wherein the second transistor (M6) is included in a current mirror (current mirror of M4 and M6) defined in the preamplifier stage (M1…M6), and wherein the second transistor (M6) is directly connected to the output node (OUTN node).
However, Wakamatsu et al. do not disclose the comparator latch (Fig. 2; paragraph 0018) for an analog to digital converter as claimed
Fig. 3 of Agrawal discloses a comparator latch (301, 312) for an analog to digital converter (paragraph 0015), comprising: a preamplifier stage (301) configured to receive and amplify analog input signals (INP, INM); and a latch stage (312) configured to store an output (OUTP, OUTM) of the comparator latch (301, 312).
Wakamatsu et al. and Agrawal are common subject matter of comparator latch; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Agrawal into Wakamatsu et al. for the purpose of implementing a comparator for analog-to-digital converter as suggested by paragraph 0015 of Agrawal).
Regarding claim 2. Wakamatsu et al. and Agrawal applied to claim 1 above, Fig. 2 of Wakamatsu et al. further discloses when the latch stage (M7…M12) enters the active mode (M9 is off) the output node of the latch stage (OUTN node) is charged by two parallel current paths (two parallel current paths of M6 and M11) formed by the first transistor (M11) in the latch stage (M7…M12) and the second transistor (M6) in the preamplifier stage (200).
Regarding claim 3. Wakamatsu et al. and Agrawal applied to claim 1 above, Fig. 2 of Wakamatsu et al. further discloses wherein a third transistor (M12) in the latch stage (M7…M12) and a fourth transistor (M5) in the preamplifier stage (M1…M6) work together to drive a second output node (OUTP) of the latch stage (M7…M12) when the latch stage (M7…M12) is in the active mode (active mode of M7…M12 when M9 is off).
Regarding claim 4. Wakamatsu et al. and Agrawal applied to claim 3 above, Fig. 2 of Wakamatsu et al. further discloses wherein, when the latch stage (M7…M12) enters the active mode (M9 is off), the second output node (OUTP node) of the latch stage M7…M12) is charged by two parallel current paths (two parallel current path of M5 and M12) formed by the third transistor (M12) in the latch stage (M7…M12) and the fourth transistor (M5) in the preamplifier stage (M1…M6), and wherein the fourth transistor (M5) in the preamplifier stage (M1…M6) is directly connected to the second output node (OUTP node) in the latch stage (S7….S12).
Regarding claim 5. Wakamatsu et al. and Agrawal applied to claim 4 above, Fig. 2 of Wakamatsu et al. further discloses wherein fourth transistor (M5) in the preamplifier stage (M1…M6) is directly connected to the second output node (OUTP) in the latch stage (M7…M12).
Regarding claim 6. Wakamatsu et al. and Agrawal applied to claim 1 above, Fig. 3 of Agrawal further discloses wherein a first clock signal (CLK_LAT) that enables and disables the preamplifier stage (301) is delayed (output timing of CLK_LAT based on timing input CLK; therefore CLK_LAT is delayed relative to CLK; see Fig. 4 {350}; relative to a second clock signal (CLK) that switches modes (switch modes of 332) of the latch stage (312).
Regarding claim 22. Fig. 2 of Wakamatsu et al. combined with Agrawal applied to claim 1 above further discloses wherein the preamplifier stage (M1…M6) includes a third transistor (M2) having a gate (gate of M2) that is connected to an input node (INN node) of the preamplifier stage (M1…M6), and wherein a drain of the second transistor (drain of M6) is directly connected to the output node (OUTN node).
7. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wakamatsu et al. and Agrawal applied to claim 6 above in further view of Bruccoleri et al. US. Patent No. 5,808,488.
Regarding claim 7. Wakamatsu et al. and Agrawal applied to claim 6 above, Fig. 3 of Agrawal further discloses wherein the delay (output timing of CLK_LAT based on timing input CLK; therefore CLK_LAT is delayed relative to CLK) between the first (CLK_LAT) and second (CLK) clock signals results in a time period where the preamplifier stage (301) is enabled and the latch stage is active (active of 312) , wherein the first transistor (MN) in the latch stage (312) and the second transistor (MP0) in the preamplifier stage (301) are configured to work together to drive the output node (OUTM) of the latch stage (312) during the time period (time period of CLK and CLK_LAT).
However, Fig. 3 of Agrawal does not disclose the first (CLK_LAT) and second (CLK) clock signals results in an overlapping time period and to drive the output node (OUTM) of the latch stage (312) during the overlapping time period.
Fig. 4 and Fig. 5 of Bruccoleri et al. discloses a pre-amplifier stage (S1 stage and S2 stage) and a latch stage (INV1, INV2) comprising: delay (see Fig. 5) between a first (Vck) ) and second clock (vckd) signals results in an overlapping time period (overlap period of Vck and Vckd) where the preamplifier stage (S1, S2 stage) is enabled and the latch stage is active (active of INV1 and INV2), wherein a first transistor (transistor of INV1) in the latch stage (INB1 and INV2) and the second transistor (transistor of S1 and S2) in the preamplifier stage (S1 and S2 stage) are configured to work together to drive the output node (Vout) of the latch stage (INV1, INV2) during the overlapping time period (overlapping period of Vck and Vckd in Fig. 5).
Wakamatsu et al./Agrawal and Bruccoleri et al. are common subject matter of time period comparator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Bruccoleri et al. into Wakamatsu et al./Agrawal for the purpose of providing a timed bistable circuit (latch) having a reduced offset which is substantially independent of the timing frequency (Col. 1 lines 63-65 of Bruccoleri et al.).
Regarding claims 8. Wakamatsu et al./Agrawal and Bruccoleri et al. applied to claims 7 above, Fig. 3 of Agrawal further discloses wherein, after the overlapping time period expires (as combined with Bruccoleri applied to claim 7 above), the second transistor (MP0) in the preamplifier stage (312) is configured to stop driving (disable the MP4) the output node (OUTM) but the first transistor MN0) in the latch stage (312) continues to drive the output node (OUTM) until the latch stage (312) is switched into a reset mode (reset switched 314 is on by CLK) .
8. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wakamatsu et al. applied to claim 9 above, in view of Agrawal Pub. No. 2019/0207562.
Wakamatsu et al. applied to claim 9 above, do not disclose wherein a first clock signal that enables and disables the preamplifier is delayed relative to a second clock signal that switches modes of the latch.
Fig. 9 of Agrawal discloses a method, comprising: driving output nodes (OUTP, OUTM nodes ) of a latch (312) in a comparator (300) comprising: a first clock signal (CLK_LAT) that enables and disables the preamplifier (312) is delayed relative ((output timing of CLK_LAT based on timing input CLK; therefore CLK_LAT is delayed relative to CLK; see Fig. 4 {350}) to a second clock signal (CLK) that switches modes (switching of MN2, MN3 and MP5) of the latch (312).
Wakamatsu et al. Agrawal are common subject matter of comparator latch; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Agrawal into Wakamatsu et al. for the purpose of provide a high speed and low power PMOS-based comparator (paragraph 0016 of Agrawal).
9. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wakamatsu et al. and Agrawal applied to claim 13 above in further view of Bruccoleri et al. US. Patent No. 5,808,488.
Fig. 3 of Agrawal applied to claim 13 above does not disclose wherein the delay between the first and second clock signals results in an overlapping time period where the preamplifier is enabled and the latch is active, wherein the latch transistors in the latch and the output transistors in the preamplifier work together to drive the output nodes of the latch during the overlapping time period.
Fig. 4 and Fig. 5 of Bruccoleri et al. discloses a pre-amplifier stage (S1 stage and S2 stage) and a latch stage (INV1, INV2) comprising: delay (see Fig. 5) between a first (Vck) ) and second clock (vckd) signals results in an overlapping time period (overlap period of Vck and Vckd) where the preamplifier stage (S1, S2 stage) is enabled and the latch stage is active (active of INV1 and INV2), wherein a first transistor (transistor of INV1) in the latch stage (INB1 and INV2) and the second transistor (transistor of S1 and S2) in the preamplifier stage (S1 and S2 stage) are configured to work together to drive the output node (Vout) of the latch stage (INV1, INV2) during the overlapping time period (overlapping period of Vck and Vckd in Fig. 5).
Wakamatsu et al./Agrawal and Bruccoleri et al. are common subject matter of time period comparator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Bruccoleri et al. into Wakamatsu et al./Agrawal for the purpose of providing a timed bistable circuit (latch) having a reduced offset which is substantially independent of the timing frequency (Col. 1 lines 63-65 of Bruccoleri et al.).
Regarding claim 15. Wakamatsu et al./Agrawal and Bruccoleri et al. applied to claim 14 above, , Fig. 3 of Agrawal further discloses wherein, after the overlapping time period expires (as combined with Bruccoleri applied to claim 7 above), the second transistor (MP0) in the preamplifier stage (312) is configured to stop driving (disable the MP4) the output node (OUTM) but the first transistor MN0) in the latch stage (312) continues to drive the output node (OUTM) until the latch stage (312) is switched into a reset mode (reset switched 314 is on by CLK) .
10. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Wakamatsu et al. and Agrawal applied to claim 9 above in further view of Santoron et al. U.S. patent No. 8248,108.
Regarding claim 21. Fig. 2 of Wakamatsu et al. combined with Agrawal applied to claim 1 above discloses the second transistor is a PMOS transistor instead of NMOS transistor as claimed.
Fig. 4 of Santoron et al. discloses a comparator latch (100) comprising a preamplifier stage (10) and latch stage (20), a second transistor (M2) is a N- channel Metal-Oxide Semiconductor (NMOS) transistor (NMOS of M2) in preamplifier stage (10) .
Wakamatsu et al./Agrawal and Santoron et al. are common subject matter MOS transistors of comparator latch; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Agrawal into Wakamatsu et al. for the purpose of providing pair of input transistors M1, M2, herein of the NMOS type, having gate terminals connectable respectively to input 11 and input 12 (Col. 4 lines 20-22 of Santoron et al.).
Contact Information
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
03/10/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845