DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This final office action is responsive to the amendments filed on 10/21/2025.
Claims 1-5, 7-25 are pending.
Response to Amendment
Applicant has amended independent claims 1, 23, 24 and dependent claims 2 to include new/old limitations in a form not previously presented necessitating new search and considerations. Claim 6 has been cancelled by the Applicant.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-24 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-18 of US Patent No. 11,907,105 B2 (hereafter ‘105).
Instant Invention
US Patent 11,907,105 B2 (‘105)
1. A device, comprising: one or more processors; a memory coupled to the one or more processors; and
1. A device, comprising: one or more processors including a graphics processing unit (GPU) and a central processing unit (CPU) core; a memory coupled to the one or more processors; and
an operating system (OS) stored in the memory and configured to run on at least a subset of the one or more processors,
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors including the CPU core,
wherein the operating system is configured to selectively run in a timing testing mode
or in a mode of operation other than the
timing testing mode,
wherein the operating system is configured to selectively run in a normal mode or a timing testing mode,
wherein in the timing testing mode, normal operation of the device is suspended, and the device is configured to by shifting a timing of tasks on the one or more processors.
wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and
testing the application for errors in device hardware components synchronization and/or software components synchronization while the device is running in the timing testing mode, wherein disrupting the timing of processing that takes place on the GPU while running an application with the GPU includes the OS replacing the firmware of GPU.
As illustrated in above table, Claim 1 of instant application are rejected on over claim 1 of US Patent ‘105. Claims 1 of the instant application teaches “a mode of operation other than the timing testing mode” and “the timing testing mode the device is configured to attempt to induce skew”, which is missing from claim 1 of the US Patent ‘105. However, US Patent ‘105 discloses “normal mode”, “timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU”, and other limitations which is not specifically recited in claim 1 of the instant invention. In addition, claim 1 of US Patent ‘105 further recites many other claim elements that are missing from the claim 1 of the instant invention.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention that normal mode as recited in claim 1 of the US Patent ‘105 is a specific example as recited in claim 1 of the instant invention. Similarly, disrupting processing as recited in US Patent ‘105 is similar to the claimed elements of inducing skew as recited in claim 1 of instant invention. Therefore, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention that the claim 1 of the instant invention is covered by claim 1 of the US Patent ‘105 and claim 1 is an obvious variation of claim 1 of the US Patent ‘105. Although the claims at issue are not identical, they are not patentably distinct from each other.
Similar claim mappings of the remaining claims would have been obvious to a person having ordinary skill in the art but have been omitted for the sake of brevity.
This is an obviousness-type double patenting rejection.
Claims 1-24 are also rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-26 of US Patent No. 11,042,470 B2 based on similar analysis in view of mapping shown in the table below.
Instant Invention
US Patent 11,042,470 B2 (‘470)
1. A device, comprising: one or more processors; a memory coupled to the one or more processors; and
1. A device, comprising: one or more processors; a memory coupled to the one or more processors; and
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors,
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors,
wherein the operating system is configured to selectively run in a timing testing mode
or in a mode of operation other than the
timing testing mode,
wherein the operating system is configured to selectively run in a normal mode or a timing testing mode,
wherein in the timing testing mode the device is configured to attempt to induce skew.
wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors and
testing the application for errors in device hardware components synchronization and/or software components synchronization while the device is running in the timing testing mode, wherein the one or more processors include a central processing unit (CPU), wherein, in the timing testing mode, the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application on the one or more processors by reducing resources of the CPU that are available to run the application.
Claims 1-24 are also rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1-134 of US Patent No. 9,892,024 B2 based on similar analysis in view of mapping shown in the table below.
Instant Invention
US Patent 9,892,024 B2 (‘024)
1. A device, comprising: one or more processors; a memory coupled to the one or more processors; and
1. A device, comprising: one or more processors; a memory coupled to the one or more processors; and
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors,
an operating system (OS) stored in the memory configured to run on at least a subset of the one or more processors,
wherein the operating system is configured to selectively run in a timing testing mode
or in a mode of operation other than the
timing testing mode,
wherein the operating system is configured to selectively run in a normal mode or a timing testing mode,
wherein in the timing testing mode the device is configured to attempt to induce skew.
wherein in the timing testing mode the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors and
testing the application for errors in device hardware components synchronization and/or software components synchronization while the device is running in the timing testing mode, wherein the one or more processors include a central processing unit (CPU), wherein, in the timing testing mode at least a subset of the one or more CPU cores are configured to operate at one or more frequencies that are higher than a standard operating frequency for the one or more CPU cores in the normal mode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-10, 15-16, 19, and 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelsey et al. (US 7,055,006 B1, hereafter Kelsey) in view of Lin et al. (US 2016/0275123 A1, hereafter Lin), and further in view of MCGOWAN et al. (US 2013/0266082 A1, hereafter Mcgowan), and further in view of Jang et al. (US 2015/0378859 A1, hereafter Jang).
Kelsey and Lin were cited in the last office action.
As per claim 1, Kelsey teaches the invention substantially as claimed a device comprising:
a memory storing an operating system (OS) (col 3 lines 12-14 operating system, host computer fig. 1 to/from memory, processing unit 100); and
one or more processors configured to access the memory and execute the OS to operate the device to perform operations (fig. 1 processing system 100 CPU core 110 to/from memory vol 3 lines 8-20 cpu core, execute, instructions contained in applications and an operating system executed by host computer) comprising selectively executing a plurality of tasks of an application in a timing testing mode or in a mode of operation other than the timing testing mode (col 1 lines 10-30 debugging mode, application / operating system, executed, central processing unit, not reflect the normal operation; col 1 lines 34-45 debugging mode, cache is enabled; col 1 lines 67-col 2 lines 2-3 application and operating system could be executed normally fig. 3 debugging feature invoked 302, enable use of caches 304 i.e. normal mode block use of caches 308 i.e. other than normal mode), wherein:
the mode of operation other than the timing testing mode includes a normal operation of the device (col 1 lines 67-col 2 lines 2-3 application and operating system could be executed normally; fig. 3 enable use of cache i.e. normal mode);
in the normal operation of the device, the operations comprise (col 1 lines 67-col 2 lines 2-3 application and operating system could be executed normally; fig. 3 enable use of cache i.e. normal mode; col 1 lines 10-30 debugging mode, application / operating system, executed, central processing unit, not reflect the normal operation, which indicates there is another mode with non-debugging mode or normal operation):
executing a first task of the plurality of tasks to generate a first data (col 1 lines 65-67 col 2 lines 1-5 application, operating system, executed, normally; col 4 lines 24-26 results of the execution unit stage; col 8 17-22 processing system, write, changed data back to external memory; col 3 lines 54-60 integer unit 115 execute instructions eight stage pipeline, prefetch/pre-decode/decode/…execution unit/writeback stage; col 4 lines 18-24 execution unit stage, data, fed through ALU for ALU operations, execution unit stages, complete); and
executing a second task of the plurality of tasks using the first data (col 3 lines 54-60 integer unit 115 execute instructions eight stage pipeline, instruction pre-fetch state, instruction pre-decode stage, instruction decode stage, instruction queue stage, two address calculation stage, execution state, writeback stage; every subsequent stage uses data from the preceding stage col 4 lines 24-25 execution unit stages, complete, writeback stage, writes, results of the execution unit stage to the register file or data memory), wherein initiating execution of the second task requires the first data (col 4 lines 24-25 writeback stage, writes results of the execution unit stage i.e. using data from the previous stage; col 3 lines 54-60 pipeline i.e. data from the previous stage is required); and
in the timing testing mode, normal operation of the device is suspended (col 1 lines 10-30 debugging mode, application / operating system, executed, central processing unit, not reflect the normal operation i.e. normal operation is suspended; fig. 3 execute instruction in debugging mode i.e. normal operation is suspended) and the operations comprise inducing skew by shifting an execution timing of the second task as the application is executed on the one or more processors (fig. 3 debugging feature invoked, block use of caches 304 308, execute instruction 310 col 4 lines 26-40 FPU, dynamic scheduling, out of order execution, instruction issue rate of one instruction per clock; col 5 lines 49-55 control processor, manages, macro clock, debugging function, processing system i.e. induce skew col 1 lines 10-30 debugging mode, application / operating system, executed, central processing unit, not reflect the normal operation col 4 lines 10-13 microcode, take over the pipeline, inject micro-box, multi-box i.e. time-shift) such that one or more errors are exposed during execution of the second task that would otherwise be missed in the normal operation of the device, wherein shifting the execution timing of the second task includes (col 4 lines 10-13 microcode, take over the pipeline, inject micro-box, multi-box i.e. time-shift col 4 lines 26-40 out of order execution; col 5 lines 49-55 debugging function):
executing the first task to generate the first data (col 3 lines 54-60 integer unit 115 execute instructions eight stage pipeline, prefetch/pre-decode/decode/…execution unit/writeback stage; col 4 lines 18-24 execution unit stage, data, fed through ALU for ALU operations; col 8 17-22 processing system, write, changed data back to external memory i.e. generating data); and
initiating execution of the second task prior to completion of the first task and without the first data that is required to initiate the execution of the second task.
Kelsey doesn’t specifically teach memory storing operating system; initiating execution of second task requires the first data; time shifting such that one or more errors are exposed during execution of the second task that would otherwise be missed in the normal operation of the device, initiating execution of the second task prior to completion of the first task and without the first data that is required to initiate the execution of the second task.
Lin, however, teaches memory storing operating system (fig. 3 memory 304 operating system 324);
initiating execution of second task requires the first data (fig. 1 reduce task 112 requires intermediate data 110; second map-reduce job 104 requires reduce task output data 116 [0038] the second job 104 can start execution and use data produced by the first job 102 [0101] starting pipeline queue, multiple pipeline queue connections);
time shifting such that one or more errors are exposed during execution of the second task that would otherwise be missed in the normal operation of the device, initiating execution of the second task prior to completion of the first task ([0038] second job, begin processing before the first job completes, first job, second job, sequentially ) and without the first data that is required to initiate the execution of the second task ([0099] write operation is not successful [0101] when there is not another pipeline queue connection for receiving reduce task result fig. 1 reduce task 112 requires intermediate data 110; second map-reduce job 104 requires reduce task output data 116 [0038] the second job 104 can start execution and use data produced by the first job 102 [0101] starting pipeline queue, multiple pipeline queue connections).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey with the teachings of Lin of memory storing operating system, second map-reduce task requires output data from the reduce stage of task, begin processing of sequential second job before first job completes to improve efficiency and allow memory storing operating system; initiating execution of second task requires the first data; and initiating execution of the second task prior to completion of the first task to the method of Kelsey as in the instant invention.
The combination would have been obvious because applying the method of storing operating system in the memory, second job requiring first data, and initiating second job before the completion of the first job as taught by Lin to the execution method taught by Kelsey to yield predictable result and is motivated by improved efficiency / reduction in processing time.
Kelsey and Lin, in combination, do not specifically teach time shifting such that one or more errors are exposed during execution of the second task that would otherwise be missed in the normal operation of the device; initiating execution of the second task without the first data that is required to initiate the execution of the second task.
McGowan, however, teaches time shifting such that one or more errors are exposed during execution of the second task that would otherwise be missed in the normal operation of the device ([0009] plurality of carrier processing blocks, generating, error signal, power, time-shifted, input signal, exceeds, peak threshold ).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey and Lin with the teachings of Mcgowan of time shifting the input signal to generate error signal when power exceeds the peak threshold amount to improve reliability and allow time shifting such that one or more errors are exposed during execution of the second task that would otherwise be missed in the normal operation of the device to the method of Kelsey and Lin as in the instant invention.
The combination would have been obvious because applying the method of applying time shift to the input signal to generate error signal as taught by Mcgowan to the method of Kelsey and Lin to yield predictable result and improved reliability.
Kelsey, Lin and Mcgowan, in combination, do not specifically teach initiating execution of the second task without the first data that is required to initiate the execution of the second task.
Jang, however, teaches initiating execution of the second task without the first data that is required to initiate the execution of the second task ([0053] faults injected, file_descriptor fault i.e. unable to access the required data; fig. 6 inject faults S620, perform received fault actions S630).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey, Lin, and Mcgowan with the teachings of Jang of injecting file descriptor_fault and performing fault action to improve reliability and allow initiating execution of the second task without the first data that is required to initiate the execution of the second task to the method of Kelsey, Lin, and Mcgowan as in the instant invention.
The combination would have been obvious because applying the method of injecting fault and performing fault action as taught by Jang to the method of Kelsey, Lin, and Mcgowan to yield predictable result and improved reliability.
As per claim 8, Kelsey teaches wherein in the timing testing mode, inducing skew writing back a processor cache of at least one of the one or more processors (fig. 3 enable use of caches 304 block use of cache 308 i.e. effect of writing back the cache).
As per claim 9, Kelsey teaches wherein, in the timing testing mode, inducing skew includes invalidating a processor cache at least one of the one or more processors (fig. 3 enable use of caches 304 block use of cache 308 i.e. effect of invalidating of cache).
As per claim 10, Kelsey teaches wherein in the timing testing mode inducing skew includes invalidating an instruction cache at least one of the one or more processors (fig. 3 enable use of caches 304 block use of cache 308 i.e. effect of invalidating of cache fig. 1 CPU core 110 instruction cache 111).
As per claim 15, Kelsey teaches wherein in the timing testing mode, inducing skew includes restricting computing resources of a Graphics Processing Unit (fig. 1 CPU core 110 Graphics processor 125 fig. 3 enable use of caches 304 blocking use of caches 308 i.e. restricting resource).
As per claim 16, Kelsey teaches a Graphics Processing Unit (fig. 1 graphics processor 125).
Fung teaches remaining claim elements of wherein in the timing testing mode, inducing skew includes requesting a Processing Unit to perform other processing tasks that reduce a remaining resources available for processing the application ([0064] operations performed by one or more nodes may be shifted to another node, remaining active nodes, node, placed, into inactive mode).
As per claim 19, Kelsey teaches in the timing testing mode, inducing skew includes determining one or more of application stalls, application errors, and anomalous results of the application (fig. 3 debugging feature invoked 302 col 1 lines 15-21 debugging mode, analyze the log, identify potential problem with an application).
Fung teaches remaining claim elements of determining one or more of application stalls, anomalous result of the execution of the application ([0058] diagnostic information, trouble shoot, debug, diagnose problem [0160] 1st mode, 2nd mode, reducing clock frequency /voltage [0163] fig. 14 utilization, time, 1st /2nd /3rd modes).
Claim 23 recites a device for elements similar to claim 1. Therefore, it is rejected for the same rationale.
Claim 24 recites non-transitory computer readable medium having computer readable executable instructions embodied therein, the instructions being configured to cause a device for elements similar to claim 1. Therefore, it is rejected for the same rationale.
As per claim 25, Lin teaches wherein initiating execution timing of the second task prior to completion of the first task ([0038] second job, begin processing before the first job completes, first job, second job, sequentially).
Jang teaches remaining claim elements of execution of task prior to completion of the first task results in a first error of the one or more errors ([0052] timeout fault injected i.e. first task result is not available, fig. 6 inject faults S620 perform fault actions S630 display fault action performance result S640).
Claims 2-5, 7, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelsey in view of Lin, and further in view of MCGOWAN, and further in view of Jang, as applied to above claims, and further in view of Fung et al. (US 2006/0248360 A1, hereafter Fung).
Fung was cited in the last office action.
As per claim 2, Mcgowan teaches wherein shifting the execution time of the second task includes shifting the execution timing of tasks from a first timing found during the normal operation of the device to timings not found in the normal operation of the device ([0009] plurality of carrier processing blocks, generating, error signal, power, time-shifted, input signal, exceeds, peak threshold).
Kelsey, Lin, Mcgowan and Jung, in combination, do not specifically teach shifting to timings not found in the normal operation of the device.
Fung, however, teaches shifting to timings not found in the normal operation of the device([0225] normal operation, CPU clock frequency and core voltage are at their rated maximum values i.e. normal operating conditions; power saving, frequency and voltage reduced, control operating condition of other circuits /peripherals i.e. change in frequency/voltage cause change in processing times [0046] task, performed, one node, shifted to one or more other nodes [0047] clock speed, increased, decreased i.e. time shifted [0180] core voltage, clock frequency, changed, continuously, processor clock frequency reduction i.e. time shifted [0110] core voltage. Raised/lowered. Conjunction with CPU clock frequency, voltage change, desirably, synchronized, time, frequency change i.e. also indicate possibility non-synchronized changes).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey, Lin, Mcgowan and Jang with the teachings of Fung of changing the operating frequency and voltage of to induce shift to improve reliability and allow shifting timing to timings not found in the normal operation of the device to the method of Kelsey, Lin, Mcgowan and Jang as in the instant invention.
The combination would have been obvious because known method of operating at different frequency/voltage to shift time beyond normal processing time as taught by Fung to the method of shifting time as taught by Kelsey, Lin, Mcgowan and Jang to yield predictable results and improved reliability.
As per claim 3, Fung teaches wherein in the timing testing mode, inducing skew includes operating at least one of the one or more processors at a different clock frequency than a standard clock frequency for the one or more processors ([0180] core voltage, clock frequency, changed, continuously, processor clock frequency reduction, first mode 100% nominal rated clock frequency, second mode, clock frequency less than 100%).
As per claim 4, Kelsey teaches wherein, in the timing testing mode, inducing skew includes restricting resources of at least one of the one or more processors to affect timing of the execution of application code (fig. 3 block use of cache 308 - i.e. blocking cache will introduce delay).
Fung teaches remaining claim elements wherein in the timing testing mode the device is configured to affect a timing of an execution of application code on the OS([0160] 1st mode, 2nd mode, reducing clock frequency /voltage [0163] fig. 14 utilization, time, 1st /2nd /3rd modes - will affect time of execution [0329] processor, placed in suspended mode).
As per claim 5, Fung teaches wherein, in the timing testing mode, inducing skew includes the OS temporarily suspending one or more application threads running on at least one of the one or more processors ([0191] number of idle threads being executed, more performance is available than is needed, power consumption may be reduced without sacrificing performance i.e. suspending the idle threads [0135] server module, suspend itself [0329] processor, placed in suspended mode i.e. suspended thread).
As per claim 7, Fung teaches wherein in the timing testing mode, inducing skew includes executing application threads on at least one of the one or more processors different from a processor specified by an application in the mode of operation other than the timing testing mode ([0046] task, performed, one node, shifted to one or more other nodes [0047] clock speed, increased, decreased [0180] core voltage, clock frequency, changed, continuously, processor clock frequency reduction [0225] normal operation, CPU clock frequency and core voltage are at their rated maximum values i.e. normal operating conditions).
As per claim 11, Kelsey teaches wherein, in the timing testing mode, inducing skew includes invalidating a translation lookaside buffer of at least one of the one or more processors (fig. 3 enable use of caches 304 block use of cache 308 i.e. effect of invalidating cache fig. 1 TLB 113).
Fung teaches the remaining claim elements of invalidating a translation lookaside buffer ([0195] CPU, halted and resumed i.e. effectively invalidating the TLB).
As per claim 12, Kelsey teaches wherein in the timing testing mode, inducing skew includes the OS (fig. 3 enable use of caches 304 block use of cache 308 i.e. effecting skew) configuring a Graphics Processing Unit (GPU) (fig. 1 GPU 125)
Fung teaches GPU to run a different frequency than a standard operating frequency for the GPU ([0180] core voltage and clock frequency, changed continuously, frequency reduction, 100% of the nominal rated clock frequency, second mode, frequency less than 100%).
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelsey in view of Lin, and further in view of MCGOWAN, and further in view of Jang, as applied to above claims, and further in view of Novakovsky et al. (US 2014/0281239 A1, hereafter Novakovsky).
Novakovsky was cited in the last office action.
As per claim 14, Kelsey teaches wherein, in the timing testing mode, inducing skew includes modifying a behavior of one or more of caches of a list comprising of L1 I-Caches, L1 D-Caches, Instruction Translation Lookaside Buffers hierarchies, Data Translation Lookaside Buffer hierarchies, and higher level caches (fig. 1 CPU core 110 instruction cache 111 data cache 112 TLB 113 fig. 3 enable use of caches 304 block use of caches 308), wherein modifying a behavior of one or more caches comprises at least one of: modifying whether the one or more caches is exclusive, or inclusive (fig. 3 enable use of caches 304 block use of caches 308) or modifying a lookup behavior of the one or more caches.
Kelsey, Lin, Mcgowan, and Jang , in combination, do not specifically teach modifying whether the one or more caches is exclusive, or inclusive or modifying a lookup behavior of the one or more caches.
Novakovsky, however, teaches modifying whether the one or more caches is exclusive, or inclusive or modifying a lookup behavior of the one or more caches ([0013] selecting inclusive / non-inclusive or exclusive policy as inclusion policy for the cache).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey, Lin, Mcgowan, and Jang of introducing deviation in the execution time with the teachings of selecting cache inclusion policy as inclusive or exclusive to improve flexibility in introducing / removing time delay and allow modifying whether the one or more caches is exclusive, or inclusive or modifying a lookup behavior of the one or more caches to the method of Kelsey, Lin, Mcgowan, and Jang as in the instant invention. The combination would have been obvious because applying cache inclusion policy as taught by Novakovsky to the method of Kelsey, Lin, Mcgowan, and Jang to yield predictable results of introducing / removing time delay i.e. flexibility of execution with reasonable expectation of success and improved testability.
Claim 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelsey in view of Lin, and further in view of MCGOWAN, and further in view of Jang, as applied to above claims, and further in view of Kumar et al. (US 2003/0188083 A1, hereafter Kumar).
Kumar was cited in the last office action.
As per claim 17, Fung teaches wherein, in the timing testing mode, inducing skew includes configuring one or more of a memory clock and an internal bus clock to each run at a frequency different than a standard operating frequency of one or more of the memory clock and the internal bus clock for the device in the mode of operation other than the timing testing mode ([0047] clock speed, increased, decreased [0180] core voltage, clock frequency, changed, continuously, processor clock frequency reduction [0180] 100% of nominal rated clock frequency for the processor, clock frequency less than 100%).
Kelsey, Lin, Mcgowan, and Jang, in combination, do not specifically teach frequency of one or more of the memory clock and the internal bus clock .
Kumar, however, teaches frequency of one or more of the memory clock ([0031] timing parameters, memory, clock speed that memory can support, set a memory controller ) and the internal bus clock ([0019] timing parameter, internal clock, clock speed of bus).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey, Lin, Mcgowan, and Jang of introducing deviation in the execution time with the teachings of setting clock speed that memory can support and clock speed of bus to improve flexibility and efficiency and allow configuring frequency of one or more of the memory clock and the internal bus clock to the method of Kelsey, Lin, Mcgowan, and Jang as in the instant invention. The combination would have been obvious because applying setting clock speed for the memory and bus as taught by Kumar to the method of Kelsey, Lin, Mcgowan, and Jang to yield predictable results of changing the memory clock speed or internal bus clock speed with reasonable expectation of success and improved efficiency and flexibility.
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelsey in view of Lin, and further in view of MCGOWAN, and further in view of Jang, as applied to above claims, and further in view of Steinberg (US 8,595,680 B1).
Steinberg was cited in the last office action.
As per claim 20, Kelsey teaches wherein in the timing testing mode inducing skew includes configuring a memory controller to simulate random failures to read external memory (col 5 lines 62-67 memory controller facilitates access to one or more external memories).
Kelsey, Lin, Mcgowan, and Jang, in combination, do not specifically teach simulating random failures.
Steinberg, however, teaches controller to simulate random failures (fig. 4 determining, simulated, memory circuit, generate a memory error 406 generating the memory error as a result of memory access 408 col 13 lines 35-44 simulated memory circuit, memory access, error probability, random value, memory error to be generated).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey, Lin, Mcgowan, and Jang of introducing deviation in the execution time with the generating error based on random values by the simulated memory circuit as taught by Steinberg as in the instant invention. The combination would have been obvious because applying the method of random error generated by simulated memory circuit to induce skew to the method of Kelsey, Lin, Mcgowan, and Jang with reasonable expectation of success and is motivated by improved efficiency.
Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelsey in view of Lin, and further in view of MCGOWAN, and further in view of Jang, as applied to above claims, and further in view of Blake et al. (US 2016/0314078 A1, hereafter Blake).
Blake was cited in the last office action.
As per claim 21, Kelsey teaches wherein in the timing testing mode inducing skew includes configuring a memory controller to increase latency of memory accesses by the memory controller (fig. 1 memory controller 165 col 5 lines 62-67 facilitates access to one or more external memories fig. 3 enable/block use of caches 304 308).
Kelsey, Lin, Mcgowan, and Jang, in combination, do not specifically teach memory controller to increase latency of memory accesses.
Blake, however, teaches configuring a memory controller to increase latency of memory accesses by the memory controller ([0033] memory controller, power down, bank bit, DRAM, increase in latency for accessing data).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey, Lin, Mcgowan, and Jang of introducing deviation in the execution time with the teachings of memory controller increasing latency of memory access as taught by Blake to improve efficiency and allow memory controller to induce skew by increasing latency using memory controller to the method of Kelsey, Lin, Mcgowan, and Jang with reasonable expectation of success.
Claim 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelsey in view of Lin, and further in view of MCGOWAN, and further in view of Jang, as applied to above claims, and further in view of Li et al. (US 2016/0034195 A1, hereafter Li).
Li was cited in the last office action.
As per claim 22, Kelsey teaches wherein in the timing testing mode inducing skew includes configuring a memory controller to prioritize types of memory accesses different from the prioritization of types of memory accesses during the mode of operation other than the timing testing mode (col 1 lines 25-30 operating system, configured, use, external memory, instead of cache, modified, behavior of operating system, normal operation of the operating system col 1 lines 35-45 fig. 3 304 308 310).
Kelsey, Lin, Mcgowan, and Jang, in combination, do not specifically teach inducing skew includes configuring a memory controller to prioritize types of memory accesses different from the prioritization of types of memory accesses during the mode of operation other than the timing testing mode.
Li, however, teaches induce skew by configuring a memory controller to prioritize types of memory accesses different from the prioritization of types of memory accesses ([0021] memory controller, tag memory requests with priority, memory requests, return as soon as possible, or can be delayed).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Kelsey, Lin, Mcgowan, and Jang of introducing deviation in the execution time with the teachings of memory controller prioritizing memory access as taught by Li to improve efficiency and allow memory controller to induce skew by tagging memory access with priority to the method of Kelsey, Lin, Mcgowan, and Jang with reasonable expectation of success.
Examiners Note
Applicant is further reminded of that the cited paragraphs and in the references as applied to the claims above for the convenience of the applicant(s) and although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider all of the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Allowable Subject Matter
Claims 13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form to overcome the rejections set forth in this office action and including all of the limitations of the base claim and any intervening claims.
Response to Arguments
The previous double patenting rejections have been maintained as requested by the Applicant.
Some of the previous 112(b) rejections have been withdrawn.
The previous 35 USC 101 rejections have been withdrawn.
Applicant argument filed on 10/21/2025 have been fully considered, but they are moot in view of new grounds of rejection.
Authorization for Internet Communication
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“Recognizing that internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABU ZAR GHAFFARI whose telephone number is (571)270-3799. The examiner can normally be reached on Monday-Thursday 9:00 - 17:00 Hrs.
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/ABU ZAR GHAFFARI/Primary Examiner, Art Unit 2195