DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-11 in the “Response To Restriction Requirement” filed on June 9, 2026 (hereinafter the “Reply”) is acknowledged. The Reply did not indicate whether the election was with or without traverse and Applicant did not distinctly and specifically point out the supposed errors in the Restriction Requirement dated April 9, 2026 (hereinafter the “Restriction Requirement”). Accordingly, Applicant’s election has been treated as an election without traverse pursuant to paragraph eight (8) of the Restriction Requirement and MPEP § 818.01(a). Also, claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim.
Information Disclosure Statement
The Information Disclosure Statements (IDSs) filed on February 9, 2024 and February 3, 2025 have been considered by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0131273 A1 (Chen) in view of US 2015/0294940 A1 (Fay).
Regarding claim 1, Chen discloses, A semiconductor package (semiconductor package (4); FIG. 4; [0038]), comprising:
PNG
media_image1.png
540
772
media_image1.png
Greyscale
a lower redistribution substrate (lower redistribution substrate (RDL1); FIG. 4; [0014]);
a module structure (first annotated FIG. 4, above) on the lower redistribution substrate (RDL1);
a connection substrate (first annotated FIG. 4, above) on the lower redistribution substrate (RDL1) and at sides of the module structure (first annotated FIG. 4, above);
a dielectric member (dielectric member (E1); FIG. 4; [0021]) on the lower redistribution substrate (RDL1) between the connection substrate (first annotated FIG. 4, above) and the module structure (first annotated FIG. 4, above); and
an upper redistribution substrate (upper redistribution substrate (RDL2); FIG 4; [0022]) on the dielectric member (E1),
wherein the module structure (first annotated FIG. 4, above) includes:
an interposer substrate (interposer substrate (100e); FIG. 4; [0039]);
a first semiconductor chip (first semiconductor chip (101); FIG. 4; [0038]); and
a molding layer (molding layer (100c); FIG. 4; [0018]) on the interposer substrate (100e) and covering the first semiconductor chip (101),
wherein the molding layer (100c) and the dielectric member (E1) include different materials ([0018]—molding layer (100c) may include polybenzoxazole and [0021]—dielectric member (E1) may include a resin such as epoxy; these are different materials), and
wherein a first via (first via (100d); FIG. 4; [0018]) in a first vertical hole (first annotated FIG. 4, above) vertically penetrates the dielectric member (E1) and the molding layer (100c) ([0018]), the first via (100d) connecting a wiring pattern (first annotated FIG. 4, above) of the upper redistribution substrate (RDL2) to a top surface (top surface (100b); FIG. 4; [0018]) of the first semiconductor chip (101).
But, Chen does not appear to explicitly disclose, that the first semiconductor chip is wire-bonded to the interposer substrate.
However, in analogous art, Fay discloses that it was well-known by one of ordinary skill in the art before the effective filing date of the claimed invention that wire-bonding may be predicably utilized to electrically connect a semiconductor chip to a supporting substrate such as an interposer ([0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen and Fay before him/her that first semiconductor chip (101) of Chen may be wire-bonded to the interposer substrate (100e) to electrically connect semiconductor chip (101) to interposer substrate (100e). Please see, MPEP 2143(B) or 2143(G).
Regarding claim 6, Chen in view of Fay discloses, The semiconductor package (4) of claim 1, wherein the dielectric member (E1) fills a space between the connection substrate (Chen, first annotated FIG. 4, above) and the module structure (Chen, first annotated FIG. 4, above) and covers the connection substrate (Chen, first annotated FIG. 4, above) and the module structure (Chen, first annotated FIG. 4, above), and
a portion of the dielectric member (E1) extends between the first via (100d) and the molding layer (100c).
Regarding claim 7, Chen in view of Fay discloses, The semiconductor package (4) of claim 6, wherein
a bottom surface1 (second annotated FIG. 4, below) of the portion of the dielectric member (E1) is level with a bottom surface (second annotated FIG. 4, below) of the first via (100d), and
the portion of the dielectric member (E1) separates the molding layer (100c) from the first via (100d).
PNG
media_image2.png
471
692
media_image2.png
Greyscale
Regarding claim 8, Chen in view of Fay discloses, The semiconductor package (4) of claim 6, wherein an inner lateral surface of the first vertical hole (first annotated FIG. 4, above) is perpendicular to the top surface (100b) of the first semiconductor chip (101).
Regarding claim 9, Chen in view of Fay discloses, The semiconductor package (4) of claim 1, wherein
the molding layer (100c) includes an epoxy molding compound (EMC) (Chen, [0018]—molding layer (100c) may include a polymer material and it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that an epoxy molding compound (EMC) is a polymer. Please see, MPEP 2144(I) and paragraph [0055] of US 2022/0199529 A1 (Kim)), and
the dielectric member (E1) includes a thermosetting film (Chen, [0021]—dielectric member (E1) may include polybenzoxazole and it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that polybenzoxazole is a thermosetting film. Please see, MPEP 2144(I) and paragraph [0061] of US 2021/0191264 A1 (Tanigaki)) or a photo-imageable dielectric.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Fay and further in view of US 2023/0307304 A1 (Rho).
Regarding claim 2, Chen in view of Fay does not appear to explicitly disclose, wherein the first vertical hole includes:
a first hole that penetrates the molding layer; and
a second hole that penetrates the dielectric member, and
wherein a first inner lateral surface of the first hole and a second inner lateral surface of the second hole are coplanar with each other and inclined to the top surface of the first semiconductor chip.
However, in analogous art, Rho discloses that it was well known to one of ordinary skill in the art before the effective filing date of the claimed invention that a first vertical hole (annotated FIG. (5a), below) may be predicably fabricated to include a first hole (first hole (CV1); FIG. 5(a); [0089]) that penetrates a layer (layer (21); FIG. 5(a); [0055]) and a second hole (second hole (CV2); FIG. 5(a); [0089]) that penetrates layer (21). Rho also discloses that a first inner lateral surface (annotated FIG. 5(a), below) of first hole (CV1) and a second inner lateral surface (annotated FIG. 5(a), below) of second hole (CV2) may also be predicably fabricated to be coplanar with each other and inclined to a top surface (top surface (213); FIG. 5(a); [0055]).
PNG
media_image3.png
476
687
media_image3.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen, Fay, and Rho before him/her that the first vertical hole (Chen, first annotated FIG. 4, above) of Chen in view of Fay may be predicably fabricated to include: a first hole that penetrates the molding layer (100c); and a second hole that penetrates the dielectric member (E1), as taught by Rho, and that a first inner lateral surface of the first hole and a second inner lateral surface of the second hole are coplanar with each other and inclined to the top surface (100b) of the first semiconductor chip (101) of Chen in view of Fay, as also taught by Rho, with no change in the function of the first vertical hole of Chen in view of Fay because it would still provide an opening for first via (100d) of Chen in view of Fay in molding layer (100c) and dielectric member (E1) thereof. Please see, MPEP 2143(A).
Regarding claim 3, Chen in view of Fay does not appear to explicitly disclose, wherein
the first vertical hole includes: a first hole that penetrates the molding layer; and
a second hole that penetrates the dielectric member, and
wherein a first inner lateral surface of the first hole and a second inner lateral surface of the second hole are inclined to each other.
However, in analogous art, Rho discloses that it was well known to one of ordinary skill in the art before the effective filing date of the claimed invention that a first vertical hole (annotated FIG. 5(b), below) may be predicably fabricated to include a first hole (first hole (CV1); FIG. 5(b); [0089]) that penetrates a layer (layer (21); FIG. 5(b); [0055]) and a second hole (second hole (CV2); FIG. 5(b); [0089]) that penetrates layer (21). Rho also discloses that a first inner lateral surface (annotated FIG. 5(b), below) of first hole (CV1) and a second inner lateral surface (annotated FIG. 5(b), below) of second hole (CV2) may also be predicably fabricated to be inclined to each other.
PNG
media_image4.png
577
771
media_image4.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen, Fay, and Rho before him/her that the first vertical hole (Chen, first annotated FIG. 4, above) of Chen in view of Fay may be predicably fabricated to include: a first hole that penetrates the molding layer (100c); and a second hole that penetrates the dielectric member (E1), as taught by Rho, and that a first inner lateral surface of the first hole and a second inner lateral surface of the second hole are inclined to each other, as also taught by Rho, with no change in the function of the first vertical hole of Chen in view of Fay because it would still provide an opening for first via (100d) of Chen in view of Fay in molding layer (100c) and dielectric member (E1) thereof. Please see, MPEP 2143(A).
Regarding claim 4, Chen in view of Fay and further in view of Rho discloses, The semiconductor package (4) of claim 3, wherein
the first inner lateral surface (Rho, annotated FIG. 5(b), above) of the first hole (CV1) is inclined to the top surface (Rho, annotated FIG. 5(b), above, and (100b)) of the first semiconductor chip (101) at a first angle (Rho, annotated FIG. 5(b), above), and
the second inner lateral surface (Rho, annotated FIG. 5(b), above) of the second hole (CV2) is inclined to the top surface (Rho, annotated FIG. 5(b), above, and (100b)) of the first semiconductor chip (101) at a second angle (Rho, annotated FIG. 5(b), above).
But, Chen in view of Fay and further in view of Rho does not appear to explicitly disclose the solution to the design problem of, the second angle is different than the first angle.
However, one of ordinary skill in the art before the effective date of the claimed invention having the teachings of Chen, Fay, and Rho before him/her would have recognized that there are a finite number of predicable solutions regarding the second angle relative to the first angle—i.e., the second angle can be: (i) the same as the first angle or (ii) different than the first angle, as recited in claim 4, and, absent unexpected results, it would have been obvious to try each of these predicable solutions. Please see, MPEP 2143(E).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Fay and further in view of US 2022/0045010 A1 (Shin).
Regarding claim 10, Chen in view of Fay does not appear to explicitly disclose, wherein the module structure further includes a thermal radiation member on the top surface of the first semiconductor chip, and
wherein the first via is coupled to a top surface of the thermal radiation member.
However, in analogous art, Shin discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor package (semiconductor package (1006); FIG. 15; [0087]) may be predicably fabricated to include a thermal radiation member (thermal radiation member (HS); FIG. 15; [0033]) made of metal ([0034]) on a top surface of a semiconductor chip package (semiconductor chip package (200); FIG. 15; [0087]) that functions as a heat sink ([0034]). Shin also discloses that a via (via (203); FIG. 15; [0089]) is coupled to thermal radiation member (HS) via a thermal interface material (thermal interface material (750); FIG. 15; [0051]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen, Fay, and Shin before him/her that the module structure (Chen, first annotated FIG. 4, above) of Chen in view of Fay further includes a thermal radiation member on the top surface (100b) of the first semiconductor chip (101) to function as a heat sink, as taught by Shin, and that first via (100d) of Chen in view of Fay could be predicably fabricated to be coupled to a top surface of the thermal radiation member, as also taught by Shin, with no change in the function of first via (100d) of Chen in view of Fay because it could still connect to wiring pattern (Chen, first annotated FIG. 4, above) of upper redistribution substrate (RDL2) because the thermal radiation member is made of metal, as additionally taught by Shin.
Allowable Subject Matter
Claims 5 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, Chen in view of Fay and further in view of Rho does not appear to explicitly disclose that the second inner lateral surface of the second hole is perpendicular to the top surface of the first semiconductor chip.
Regarding claim 11, Chen in view of Fay discloses a second semiconductor chip (Chen, second semiconductor chip (201); FIG. 4; [0038]) and a second via (second via (200d); FIG. 4; [0019]) in a second vertical hole that vertically penetrates dielectric member (E1) to connect to the wiring pattern (Chen, first annotated FIG. 4, above) of upper redistribution layer (RDL2). However, Chen in view of Fay does not appear to explicitly disclose a module structure where the second semiconductor chip is face-down disposed on interposer structure (100e) of the module structure and that second via (200d) vertically penetrates molding layer (100c) of the module structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2010/0327419 A1 (Muthukumar)—Discloses a semiconductor package (104; FIG. 1e) having a lower redistribution substrate (110), a module structure (150 and 158) having an interposer substrate (152; FIG. 1c), a connection substrate (130) on lower redistribution layer substrate (110) and at sides of module structure (150 and 158), a dielectric member (162; FIG. 1d) on lower redistribution substrate (110) between connection substrate (130) and module structure (150 and 158), and an upper redistribution substrate (164; FIG. 1e).
US 2022/0199529 A1 (Kim)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that an epoxy molding compound (EMC) is a polymer ([0055]).
US 2021/0191264 A1 (Tanigaki)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that polybenzoxazole is a thermosetting film ([0061]).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-centerf for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see paragraph [0028] of Applicant’s specification regarding the” relative concept” of the meaning of bottom with respect to “one element’s relationship to another element”.
Prosecution Insights