DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/06/2026 has been entered.
Response to Amendment
This office action is in response to the amendment filed on 04/06/2026. Claims 1-16 and 21-22 are pending. Claims 1 and 10 are amended. Claims 17-20 are canceled.
Response to Arguments
Applicant's arguments filed 04/06/2026 have been fully considered but they are not persuasive.
On pages 7-8 of the Remarks, Applicant argues:
The Examiner's reasoning appears to rest on the premise that queueing a speculative prefetch request is itself the same as starting to fetch data elements from the cache memory. However, queuing a fetch request that may or may not ultimately be performed is not itself a fetch from the cache memory. To put it differently, the cited Hill disclosure concerns cancellation of a speculative request while the request is still pending in a queue. That is, no data elements associated with that request have actually been fetched. Moreover, the Final Office Action does not identify any disclosure in Hill showing cancellation after cache retrieval has already commenced and instead alleges that the Examiner's interpretation of queuing a request as equating to "starting" to fetch data elements from a cache memory is permissible under broadest reasonable interpretation (BRI) approach.
Although Applicant strongly disagrees with the interpretation taken by the Examiner, in the interest of advancing prosecution, Applicant has amended claim 1 to further clarify the claimed subject matter. For instance, claim 1, as presently amended, recites that the stream circuit is configured to cancel the retrieving of the first set of data is performed after the stream circuit has begun fetching the data elements of the first data set from the cache memory such that at least one data element of the first data set has been retrieved from the cache memory as a result of the fetching. Thus, claim 1 now recites that the cancellation occurs at a point where at least one data element of the first data set has been read out (retrieved) from the cache memory. When the cancellation occurs when the request is merely queued, as disclosed in Hill, this is clearly not the case.
However, this argument is not persuasive because the rejection has been updated to cite to Hill [0025] which discloses that the queue registers of the external transaction queue 114 are cleared when the status field identifies that the transaction has been completed, otherwise the status field may identify that the transaction has been posted to the external bus. This indicates that a speculative request may stay in the external transaction queue after it has been posted to the external bus and begun fetching data elements of the transaction until the transaction has been completed and all the elements have been fetched. Thus, the speculative request in the external transaction queue that is removed by the kill mechanism (as disclosed in Hill [0050]) may be a speculative request that has already posted to the external bus and fetched at least one data element from the memory.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16 and 21-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “the stream circuit is configured to determine, in response to the second stream open instruction and based on whether the first stream open instruction is associated with a speculative mode, whether to cancel retrieving of the first data set after the stream circuit has begun fetching the data elements of the first data set from the cache memory such that at least one data element of the first data set has been retrieved from the cache memory as a result of the fetching” in lines 14-19. However, the specification does not describe the stream circuit determining whether to cancel retrieving data of the first data set after the stream circuit has begun fetching the data elements of the first data set from the cache memory such that at least one data element of the first data set has been retrieved from the cache memory as a result of the fetching. While [0047] of the specification describes beginning acquisition of a first stream after the stream engine receives a first set of stream parameters and canceling acquisition of the first stream upon receipt of a second set of stream parameters when the speculative mode was specified for the first stream, beginning acquisition of the first stream is broader than beginning fetching “such that at least one data element of the first data set has been retrieved from the cache memory as a result of the fetching”. [0047] does not describe the stream circuit canceling retrieving the first data set after having already retrieved/fetched at least one data element of the first data set from the cache memory. No other portions of the specification was found to describe that at least one data element of the first data set is retrieved from cache memory before the stream circuit determines whether to cancel retrieving of the first data set from the cache memory.
Claim 10 recites the same limitation and is rejected for the same reasons.
The dependent claims are rejected based on their dependence from rejected base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Diefendorff US 2011/0040941 in view of Hill US 2003/0188107.
Regarding claim 1, Diefendorff teaches:
1. A circuit device comprising:
a decoder (Fig. 1, decode unit 122);
a cache memory (Fig. 1, memory subsystem 104) configured to store a first data set ([0048]: the data that a stream prefetch instruction prefetches is a first data set) and a second data set ([0047]: the data that a load instruction loads is a second data set);
a stream circuit coupled to the cache memory (Fig. 1, load/store unit 116 and stream prefetch unit 118 are together a stream circuit), wherein:
the decoder is configured to:
receive a first stream open instruction associated with the first data set ([0042]-[0043]: the decode unit receives the stream prefetch instruction from the fetch unit);
cause the stream circuit to retrieve the first data set based on the first stream open instruction by fetching data elements of the first data set ([0043] and [0048]: by dispatching the decoded stream prefetch instruction to the stream prefetch unit (also shown in Fig. 1), the decode unit causes the stream prefetch unit to retrieve the first data set by fetching the data elements of the first data set);
receive a second stream open instruction associated with the second data set ([0042]-[0043]: the decode unit receives the load instruction (i.e., a second stream open instruction) from the fetch unit); and
cause the stream circuit to retrieve the second data set based on the second stream open instruction by fetching data elements of the second data set ([0043] and [0047]: by dispatching the load instruction to the load/store unit, the decode unit causes the load/store unit to retrieve the second data set by fetching the data elements of the second data set);
Diefendorff does not teach:
wherein the second stream open instruction is subsequent to the first stream open instruction;
the stream circuit is configured to determine, in response to the second stream open instruction and based on whether the first stream open instruction is associated with a speculative mode, whether to cancel retrieving of the first data set after the stream circuit has begun fetching the data elements of the first data set from the cache memory such that at least one data element of the first data set has been retrieved from the cache memory as a result of the fetching.
However, Hill teaches to determine, in response to the second stream open instruction and based on whether the first stream open instruction is associated with a speculative mode, whether to cancel retrieving of the first data set after the stream circuit has started fetching the data elements of the first data set from the memory such that at least one data element of the first data set has been retrieved from the memory as a result of the fetching, wherein the second stream open instruction is subsequent to the first stream open instruction (Hill [0050]: a transaction queue cancels/removes a speculative prefetch request (which occurs after having placed the speculative prefetch request in the queue to start fetching data elements of the first data set) in response to a subsequent non-speculative read request and based on the speculative prefetch request being speculative (i.e., associated with a speculative mode), which cancels the retrieving of the first data set after starting fetching the data elements; further, [0025] discloses that the queue registers of the external transaction queue 114 are cleared when the status field identifies that the transaction has been completed, otherwise the status field may identify that the transaction has been posted, which indicates that a speculative request in the external transaction queue that is removed by the kill mechanism may be a speculative request that has posted and retrieved at least one data element but not yet completed).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the stream prefetch unit of Diefendorff with a transaction queue that determines whether to cancel a prefetch request in response to a subsequent non-speculative read request based on the prefetch request being speculative as taught by Hill. One of ordinary skill in the art would have been motivated to make this modification to enable prioritizing higher priority load instructions which may be needed more urgently that lower priority prefetch instructions, thus reducing stalls in the processor.
Regarding claim 3, Diefendorff in view of Hill teaches:
3. The circuit device of claim 1, wherein the first stream open instruction includes a flag that specifies whether the first stream open instruction is associated with the speculative mode (Diefendorff [0089]: speculative_stream_hit_policy field 822 is a bit/flag that specifies whether the prefetch instruction is associated with the speculative mode, see also [0048] describing that the stream prefetch instruction includes the stream descriptor 600 that includes field 822 as one of its parameters 614).
Regarding claim 4, Diefendorff in view of Hill teaches:
4. The circuit device of claim 1 further comprising a register configured to store an indication of whether the first stream open instruction is associated with the speculative mode (Diefendorff [0089]: speculative_stream_hit_policy field 822 is an indication of whether the prefetch instruction is associated with the speculative mode, see also [0069] describing an embodiment in which the operand field of the stream prefetch instruction identifies a register holding the stream descriptor that includes field 822 as one of its parameters 614).
Regarding claim 5, Diefendorff in view of Hill teaches:
5. The circuit device of claim 4, wherein:
the register is configured to store a stream template that includes the indication of whether the first stream open instruction is associated with the speculative mode (Diefendorff [0069]: the stream descriptor is a stream template (see also [0059]) that includes parameters 614 which includes field 822); and
the first stream open instruction specifies the register (Diefendorff [0069]: the stream prefetch instruction specifies the register, see also Fig. 5 504).
Regarding claim 6, Diefendorff in view of Hill teaches:
6. The circuit device of claim 1, wherein the stream circuit is configured to delay retrieving of the second data set until completion of the retrieving of the first data set based on the first stream open instruction not being associated with the speculative mode (Hill [0025] teaches that the queue registers of the external transaction queue 114 are cleared when its transaction has completed and Hill [0050] teaches only removing speculative requests from the queue registers to free up space of a non-speculative request when the queue is full, this indicates that when the queue is full and there are no speculative requests in the queue (i.e., if the prefetch instruction is not speculative), the stream circuit will wait for completion of the prefetch instruction before clearing its queue register to make space for the load instruction).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Diefendorff US 2011/0040941 in view of Hill US 2003/0188107 and Amerson US 5,778,219.
Regarding claim 2, Diefendorff in view of Hill teaches:
2. The circuit device of claim 1,
Diefendorff in view of Hill does not explicitly teach:
wherein an opcode of the first stream open instruction specifies whether the first stream open instruction is associated with the speculative mode.
However, Amerson teaches opcodes that identify whether an operation is non-speculative or speculative, see col 8 lines 14-18.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the opcode of the stream prefetch instruction to specify whether it is speculative or non-speculative as taught by Amerson. One of ordinary skill in the art would have been motivated to make this modification to enable compiler optimizations for speculative instructions, which would improve instruction level parallelism (Amerson col 2 lines 16-40)
Claims 7-10, 12-16, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Diefendorff US 2011/0040941 in view of Hill US 2003/0188107 and Ray US 2004/0044847.
Regarding claim 7, Diefendorff in view of Hill teaches:
7. The circuit device of claim 1, wherein the stream circuit includes an address generator configured to generate a first set of addresses associated with the first data set (control logic 334 in the stream prefetch engine, see Fig. 3, is an address generator since it updates the prefetch address register 324, see [0096], with a set of addresses that the prefetch instruction prefetches from, see [0048]).
Diefendorff in view of Hill does not explicitly teach:
an address generator configured to generate a second set of addresses associated with the second data set.
However, Ray teaches an address generator in a load/store unit that generates addresses for load instructions, see [0021] and Fig. 1 AGEN 110.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the load/store unit of Diefendorff to include an address generator as taught by Ray. In this combination, the AGEN of the load store unit would generate addresses for load instructions, and the AGEN/control logic 334 are collectively an address generator. One of ordinary skill in the art would have been motivated to make this modification because combining an address generator, which is a known element, with a load store unit would yield the predictable result of enabling addresses to be generated for load instructions in the load store unit.
Regarding claim 8, Diefendorff in view of Hill and Ray teaches:
8. The circuit device of claim 7, wherein the stream circuit includes a memory interface coupled to the address generator (Diefendorff Fig. 1: the interface between the memory subsystem 104 and 116/118) and configured to:
retrieve the second data set from the cache memory using the second set of addresses (Diefendorff [0047]: the load instruction loads/retrieves data from the memory subsystem, which would use addresses generated by the address generator in the combination).
Diefendorff in view of Hill and Ray does not explicitly teach:
retrieve the first data set from the cache memory using the first set of addresses
However, Ray further teaches prefetching from L2 cache to a cache reload buffer CRB, see [0022].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Diefendorff to prefetch from L2 cache to a CRB as taught by Ray such that the combination would retrieve the prefetch data from L2 cache using the addresses generated by the control logic of Diefendorff. One of ordinary skill in the art would have been motivated to make this modification to enable prefetching large amounts of streaming data from L2 without displacing data in L1 (Ray [0008]-[0009]), which would improve performance by allowing faster access to data in L2 while allowing L1 to retain useful data.
Regarding claim 9, Diefendorff in view of Hill and Ray teaches:
9. The circuit device of claim 8, wherein:
the circuit device further comprises a level-one (L1) cache memory (Diefendorff Fig. 1, 158);
the cache memory is a level-two (L2) cache memory (Diefendorff Fig. 1, 154); and
the stream circuit is configured to:
retrieve the first data set and the second data set from the L2 cache memory via a data path that does not include the L1 cache memory (Ray [0022]: demand loads and prefetch loads retrieve data from L2 to a CRB via L2 cache line bus 144 (i.e., a data path that does not include L1); in the combination, the load and stream prefetch instructions of Diefendorff would retrieve their data from L2 to a CRB via a data path that does not include L1); and
provide the first data set and the second data set via a data path that does not include the L1 cache memory (Ray [0022]: the CRB forwards the data to registers bypassing L1; in the combination, the load and prefetch data of Diefendorff would be provided from the CRB to registers via a data path that does not include L1).
Regarding claim 10, Diefendorff teaches:
10. A circuit device comprising:
a processor core (Fig. 1, components except for 102, 104, 116, and 118);
a level-one (L1) cache coupled to the processor core (Fig. 1, 158);
a level-two (L2) cache (Fig 1, 154);
a stream circuit coupled between the L2 cache and the processor core (Fig. 1, 116/118 is a stream circuit coupled to L2 and the decode unit of the processor), wherein:
the processor core is configured to:
receive a first stream open instruction associated with the data set ([0042]-[0043]: the decode unit receives the stream prefetch instruction from the fetch unit);
cause the stream circuit to retrieve the data set based on the first stream open instruction by fetching data elements of the data set ([0043] and [0048]: by dispatching the decoded stream prefetch instruction to the stream prefetch unit (also shown in Fig. 1), the decode unit causes the stream prefetch unit to retrieve the first data set by fetching data elements of the data set); and
receive a second stream open instruction ([0042]-[0043]: the decode unit receives the load instruction (i.e., a second stream open instruction) from the fetch unit)
Diefendorff does not teach:
the L2 cache configured to store a data set that the stream prefetch instruction retrieves;
a stream circuit coupled between the L2 cache and the processor core via a data path that does not include the L1 cache
the second stream open instruction is subsequent to the first stream open instruction; and
the stream circuit is configured to determine, in response to the second stream open instruction and based on whether the first stream open instruction is associated with a speculative mode, whether to cancel retrieving of the data set after the stream circuit has already started fetching the data elements of the data set.
However, Hill teaches to determine, in response to the second stream open instruction and based on whether the first stream open instruction is associated with a speculative mode, whether to cancel retrieving of the data set after the stream circuit has started fetching the data elements of the data set such that at least one data element of the data set has been retrieved from the memory as a result of the fetching, wherein the second stream open instruction is subsequent to the first stream open instruction (Hill [0050]: a transaction queue cancels/removes a speculative prefetch request (which occurs after having placed the speculative prefetch request in the queue to start fetching data elements of the first data set) in response to a subsequent non-speculative read request and based on the speculative prefetch request being speculative (i.e., associated with a speculative mode), which cancels the retrieving of the first data set after starting fetching the data elements; further, [0025] discloses that the queue registers of the external transaction queue 114 are cleared when the status field identifies that the transaction has been completed, otherwise the status field may identify that the transaction has been posted, which indicates that a speculative request in the external transaction queue that is removed by the kill mechanism may be a speculative request that has posted and retrieved at least one data element but not yet completed).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the stream prefetch unit of Diefendorff with a transaction queue that determines whether to cancel a prefetch request in response to a subsequent non-speculative read request based on the prefetch request being speculative as taught by Hill. One of ordinary skill in the art would have been motivated to make this modification to enable prioritizing higher priority load instructions which may be needed more urgently that lower priority prefetch instructions, thus reducing stalls in the processor.
The combination of Diefendorff and Hill does not teach:
the L2 cache configured to store a data set that the stream prefetch instruction retrieves;
a stream circuit coupled between the L2 cache and the processor core via a data path that does not include the L1 cache,
However, Ray teaches prefetching from L2 cache to a cache reload buffer CRB, see [0022], via a datapath that does not include the L1 cache (Fig. 1, L2 cache line bus is a data path that does not include L1 cache)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the stream circuit of Diefendorff (Fig. 1, 116/118) to include the CRB of Ray such that the stream circuit of the combination would be coupled between L2 and the processor core via a data path that does not include L1 and would prefetch data from L2 cache to the CRB as taught by Ray. One of ordinary skill in the art would have been motivated to make this modification to enable prefetching large amounts of streaming data from L2 without displacing data in L1 (Ray [0008]-[0009]), which would improve performance by allowing faster access to data in L2 while allowing L1 to retain useful data.
Regarding claim 12, Diefendorff in view of Hill and Ray teaches:
12. The circuit device of claim 10, wherein the first stream open instruction includes a flag that specifies whether the first stream open instruction is associated with the speculative mode (Diefendorff [0089]: speculative_stream_hit_policy field 822 is a bit/flag that specifies whether the prefetch instruction is associated with the speculative mode, see also [0048] describing that the stream prefetch instruction includes the stream descriptor 600 that includes field 822 as one of its parameters 614).
Regarding claim 13, Diefendorff in view of Hill and Ray teaches:
13. The circuit device of claim 10 further comprising a register configured to store an indication of whether the first stream open instruction is associated with the speculative mode (Diefendorff [0089]: speculative_stream_hit_policy field 822 is an indication of whether the prefetch instruction is associated with the speculative mode, see also [0069] describing an embodiment in which the operand field of the stream prefetch instruction identifies a register holding the stream descriptor that includes field 822 as one of its parameters 614).
Regarding claim 14, Diefendorff in view of Hill and Ray teaches:
14. The circuit device of claim 13, wherein:
the register is configured to store a stream template that includes the indication of whether the first stream open instruction is associated with the speculative mode (Diefendorff [0069]: the stream descriptor is a stream template (see also [0059]) that includes parameters 614 which includes field 822); and
the first stream open instruction specifies the register (Diefendorff [0069]: the stream prefetch instruction specifies the register, see also Fig. 5 504).
Regarding claim 15, Diefendorff in view of Hill and Ray teaches:
15. The circuit device of claim 10, wherein:
the data set is a first data set (the data in L2 that the stream prefetch instruction of the combination prefetches is the first data set);
the L2 cache is configured to store a second data set (Diefendorff [0047] and Ray [0022]: the data that the load instruction loads from L2 is a second data set);
the second stream open instruction is associated with the second data set (Diefendorff [0047] and Ray [0022]: the data that the load instruction loads from L2 is a second data set); and
the stream circuit is configured to delay retrieving of the second data set by fetching data elements of the second data set until completion of the retrieving of the first data set based on the first stream open instruction not being associated with the speculative mode (Hill [0025] teaches that the queue registers of the external transaction queue 114 are cleared when its transaction has completed and Hill [0050] teaches only removing speculative requests from the queue registers to free up space of a non-speculative request when the queue is full, this indicates that when the queue is full and there are no speculative requests in the queue (i.e., if the prefetch instruction is not speculative), the stream circuit will wait for completion of the prefetch instruction before clearing its queue register to make space for the load instruction to retrieve data by fetching data elements).
Regarding claim 16, Diefendorff in view of Hill and Ray teaches:
16. The circuit device of claim 10, wherein the stream circuit includes an address generator configured to generate a set of addresses associated with the data (control logic 334 in the stream prefetch engine, see Fig. 3, is an address generator since it updates the prefetch address register 324, see Diefendorff [0096], with a set of addresses that the prefetch instruction prefetches from, see Diefendorff [0048]).
Regarding claim 21, Diefendorff in view of Hill and Ray teaches:
21. The circuit device of claim 10, wherein the processor core is configured to cause the stream circuit to retrieve the data set based on the first stream open instruction by fetching data elements of the data set from the L2 cache (Ray [0022]: prefetch loads retrieve data from L2; in the combination, the stream prefetch instruction of Diefendorff would retrieve data by fetching data elements from L2).
Regarding claim 22, Diefendorff in view of Hill and Ray teaches:
22. The circuit device of claim 15, wherein:
retrieving of the first data set by fetching the data elements of the first data set includes fetching the data elements of the first data set from the L2 cache (Ray [0022]: prefetch loads retrieve data from L2; in the combination, the stream prefetch instruction of Diefendorff would retrieve data by fetching data elements from L2); and
retrieving of the second data set by fetching the data elements of the second data set includes fetching the data elements of the second data set from the L2 cache (Ray [0022]: demand loads retrieve data from L2; in the combination, the load instruction of Diefendorff would retrieve data by fetching data elements from L2).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Diefendorff US 2011/0040941 in view of Hill US 2003/0188107, Ray US 2004/0044847, and Amerson US 5,778,219.
Regarding claim 11, Diefendorff in view of Hill and Ray teaches:
11. The circuit device of claim 10,
Diefendorff in view of Hill and Ray does not teach:
wherein an opcode of the first stream open instruction specifies whether the first stream open instruction is associated with the speculative mode.
However, Amerson teaches opcodes that identify whether an operation is non-speculative or speculative, see col 8 lines 14-18.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the opcode of the stream prefetch instruction to specify whether it is speculative or non-speculative as taught by Amerson. One of ordinary skill in the art would have been motivated to make this modification to enable compiler optimizations for speculative instructions, which would improve instruction level parallelism (Amerson col 2 lines 16-40).
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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