DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 20, 2024 is being considered by the examiner.
Drawings
The drawings were received on February 12, 2024. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimura et al. (U.S. Patent 6,785,447, hereinafter referred to as Yoshimura). Yoshimura anticipates claims:
1 and 17. A method for forming an electro-optical assembly (see figures 1-32; includes the device made), comprising:
providing a module (one of the substrates 10, 10’ or 10” is interpreted as the module) having a module substrate (base substrate 12 is interpreted as the module substrate), the module substrate having a module waveguide (waveguides 24a-24h are interpreted as the module waveguide);
providing a circuit board (backplane/motherboard 210 is interpreted as the circuit board, see figure 31) having a circuit board substrate (212), the circuit board substrate having a circuit board waveguide (waveguides 224a-224g are interpreted as the circuit board waveguide);
assembling at least one integrated circuit (one of the I.C. chips 1a-1d is interpreted as the at least one integrated circuit) on the module; and
assembling the module to the circuit board so that the module waveguide is aligned with the circuit board waveguide for optical coupling (see figures 31 and 32).
2 and 18. The method of claim 1, wherein the at least one integrated circuit includes at least one photonic integrated circuit and an application specific integrated circuit (see figures 1 and 31, one of the chips is interpreted as the at least one photonic integrated circuit, another is interpreted as the application specific integrated circuit).
3 and 19. The method of claim 2, wherein the at least one photonic integrated circuit is provided on a first side (the upper half of the module substrate is interpreted as an upper side which is interpreted as the first side) of the module substrate and the application specific integrated circuit is provided on a second side (the bottom half of the module substrate is interpreted as a lower side which is interpreted as the second side) of the module substrate, wherein the module substrate includes a via (see column 14, line 60 – column 15, line 9, the vias are interpreted as the via) that extends through the module substrate, wherein the via is configured to conduct electricity between at least two of the circuit board, the at least one photonic integrated circuit, and the application specific integrated circuit (see figures 1-32).
4. The method of claim 3, wherein the module further comprises electrical bumps (see figures 1 and 6 where the bumps are clearly shown), wherein the electrical bumps are configured to contact the at least one photonic integrated circuit or the application specific integrated circuit, wherein the electrical bumps are configured to conduct electricity between at least two of the circuit board, the at least one photonic integrated circuit, and the application specific integrated circuit (see figures 1 and 6).
5. The method of claim 3, wherein the at least one photonic integrated circuit includes two photonic integrated circuits (see figure 31).
6 and 20. The method of claim 2, wherein the at least one photonic integrated circuit is provided on a first side of the module substrate and the application specific integrated circuit is also provided on the first side of the module substrate (see figure 31, two integrated circuits are shown on the same upper/lower/front side of the module substrate), wherein the module further comprises electrical bumps (see figures 1 and 6 which show the bumps) and a redistribution layer (see column 14, line 60 – column 15, line 9, the metallization layer is interpreted as the redistribution layer), wherein the electrical bumps are configured to contact the at least one photonic integrated circuit or the application specific integrated circuit, wherein the redistribution layer is configured to contact the electrical bumps, wherein the redistribution layer and the electrical bumps are configured to conduct electricity to or from at least two of the circuit board, the at least one photonic integrated circuit, and the application specific integrated circuit (see figures 1-32 and column 14, line 60 – column 15, line 9).
7. The method of claim 2, wherein the circuit board substrate defines a mounting plane (the generally horizontal plane containing the backplane 210 is interpreted as the mounting plane), wherein the module is assembled to the circuit board so that the module substrate is provided at a different plane (one of the generally vertical planes containing one of the module substrates is interpreted as the different plane) than the mounting plane.
8. The method of claim 7, wherein the circuit board substrate and the module substrate form a recess (the space in the receptacle 225 and 235 is interpreted as the recess), wherein the recess is formed in the mounting plane (it is so interpreted), wherein the at least one photonic integrated circuit is provided in the recess (see figure 32).
9. The method of claim 1, wherein assembling the module to the circuit board includes edge coupling the module substrate to the circuit board substrate (see figure 32, the elements are coupled at their edges).
10. The method of claim 9, wherein the edge coupling results in an edge optical interface contacting an end face of the circuit board waveguide and an end face of the module waveguide (see figure 32).
11. The method of claim 1, wherein the at least one integrated circuit includes a photonic integrated circuit waveguide (see column 10, lines 45-67; the optical links forming the intra-chip connections are interpreted as the photonic integrated circuit waveguides), wherein assembling at least one integrated circuit on the module results in the module waveguide being aligned with the photonic integrated circuit waveguide (see figures 1-32).
12. The method of claim 1, wherein the circuit board is separated into an electrical layer (the receptacle 225 is interpreted as the electrical layer) and an optical layer (the receptacle 235 is interpreted as the optical layer), wherein a gap (the recesses and space between the receptacle is interpreted as the gap) is provided between the electrical layer and the optical layer, and wherein assembling the module to the circuit board results in the module being placed in the gap (see figure 32).
13. The method of claim 1, further comprising providing a transitional substrate having a transitional waveguide (see figure 31, another of the elements 10” is interpreted as the transitional substrate with transitional waveguide).
14. The method of claim 13, further comprising assembling the transitional substrate to the module and the circuit board (see figure 31), wherein the circuit board substrate defines a mounting plane, wherein the module substrate is provided in the mounting plane, wherein the transitional substrate is not provided in the mounting plane (see figure 31, the generally vertical plane containing the elements interpreted as the module is interpreted as the mounting plane defined by the circuit board substrate, the transitional substrate is not contained within this plane), wherein the transitional waveguide is aligned with both the module waveguide and the circuit board waveguide (see figure 31, all the elements of the device are shown to be aligned in some fashion within at least one frame of reference).
15. The method of claim 1, wherein the module waveguide and the circuit board waveguide are glass waveguides (see column 71, lines 28-45)
16. The method of claim 1, wherein the module substrate and the circuit board substrate is a glass substrate (see column 31, line 48 – column 32, line 8).
17. An electro-optical assembly, comprising: a module having a module substrate, the module substrate having a module waveguide; a circuit board having a circuit board substrate, the circuit board substrate having a circuit board waveguide; and at least one integrated circuit proximate to the module, wherein the module is assembled to the circuit board so that the circuit board waveguide is aligned with the module waveguide for optical coupling.
18. The electro-optical assembly of claim 17, wherein the at least one integrated circuit includes at least one photonic integrated circuit and an application specific integrated circuit.
19. The electro-optical assembly of claim 18, wherein the at least one photonic integrated circuit is provided on a first side of the module substrate and the application specific integrated circuit is provided on a second side of the module substrate, wherein the module substrate includes a via that extends through the module substrate, wherein the via is configured to conduct electricity to or from at least two of the circuit board, the at least one photonic integrated circuit, and the application specific integrated circuit.
20. The electro-optical assembly of claim 18, wherein the at least one photonic integrated circuit is provided on a first side of the module substrate and the application specific integrated circuit is also provided on the first side of the module substrate, wherein the module further comprises electrical bumps and a redistribution layer, wherein the electrical bumps are configured to contact the at least one photonic integrated circuit or the application specific integrated circuit, wherein the redistribution layer is configured to contact the electrical bumps, wherein the redistribution layer and the electrical bumps are configured to conduct electricity to or from at least two of the circuit board, the at least one photonic integrated circuit and the application specific integrated circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M BEDTELYON whose telephone number is (571)270-1290. The examiner can normally be reached 8:00am - 4:30pm.
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/John Bedtelyon/Primary Examiner, Art Unit 2874
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