DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 7, 2026, has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-11, 13, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Publication 2012/0188682) in view of Masunari (US Publication 2019/0157007).
In re claim 1, Sato discloses a multilayer ceramic capacitor, comprising:
a ceramic body (22 – Figure 3, Figure 6, ¶36) comprising a first surface (31 – Figure 3, Figure 6, ¶35) and a second surface (32 – Figure 3, Figure 6, ¶35) facing each other in a first direction (Figure 6), a third surface (29 – Figure 1, Figure 3, Figure 6, ¶35) and a fourth surface (30 – Figure 1, Figure 3, Figure 6, ¶35) facing each other in a second direction (Figure 1) and connecting the first surface and the second surface (Figure 1, Figure 3, Figure 6), a fifth surface (27 – Figure 1, Figure 3, Figure 6, ¶35) and a sixth surface (28 – Figure 1, Figure 3, Figure 6, ¶35) facing each other in a third direction and connecting the first surface and the second surface (Figure 1, Figure 3, Figure 6);
a plurality of first internal electrodes (25 – Figure 3, Figure 6, ¶34) and a plurality of second internal electrodes (26 – Figure 3, Figure 6, ¶34) disposed inside the ceramic body (22 – Figure 3, Figure 6);
a first external electrode (23 – Figure 3, Figure 6, ¶34) disposed outside the ceramic body (Figure 6); and
a second external electrode (24 – Figure 3, Figure 6, ¶34) disposed outside the ceramic body (Figure 6),
wherein the first external electrode (23 – Figure 3, Figure 6) includes (i) a first metal layer (35 – Figure 5, ¶44) disposed on the first surface and the sixth surface of the ceramic body and electrically connected to the plurality of first internal electrodes (25 – Figure 3, Figure 6) on the first surface (Figure 1, Figure 3, Figure 5, Figure 6), and (ii) a first plated layer disposed on the first metal layer (¶44); and
wherein the second external electrode (24 – Figure 6) includes (i) a second metal layer (35 – Figure 5, ¶44) disposed on the second surface and the sixth surface of the ceramic body and electrically connected to the plurality of second internal electrodes (26 – Figure 3, Figure 6) on the second surface (Figure 1, Figure 3, Figure 5, Figure 6), and (ii) a second plated layer disposed on the second metal layer (¶44).
Sato does not disclose an insulation layer disposed on the first external electrode, wherein the insulation layer includes a gap that exposes a first portion of an outer surface of the first external electrode, wherein the first portion of the outer surface of the first external electrode opposes the sixth surface of the ceramic body, and wherein the gap has at least one surface that is exposed, and wherein the insulation layer covers a portion of the first external electrode on the first surface of the ceramic body.
Masunari discloses an insulation layer (combination of 40, 42 – Figure 12, ¶58) disposed on the first external electrode (22a – Figure 12, ¶41), wherein the insulation layer includes a gap (gap between 86, 90 – Figure 13, ¶99), that exposes a first portion of an outer surface of the first external electrode (Figure 12), wherein the first portion of the outer surface of the first external electrode opposes the sixth surface of the ceramic body (12b – Figure 12, ¶35), and wherein the gap has at least one surface that is exposed (Figure 12, Figure 13), and wherein the insulation layer (40, 42 – Figure 12) covers a portion of the first external electrode (22a – Figure 12) on the first surface of the ceramic body (12e – Figure 12, ¶35).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Masunari to prevent the occurrence of short-circuiting between mounted chip-type components (¶4-5: Masunari).
In re claim 2, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato does not disclose wherein the insulation layer covers a portion of the first external electrode on the sixth surface of the ceramic body and a portion of the second external electrode on the sixth surface of the ceramic body.
Masunari discloses wherein the insulation layer (40, 41 – Figure 12) covers a portion of the first external electrode (22a – Figure 12) on the sixth surface of the ceramic body (12b – Figure 12) and a portion of the second external electrode (22b – Figure 12, ¶41) on the sixth surface of the ceramic body (12b – Figure 2, Figure 12, Figure 13).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Masunari to prevent the occurrence of short-circuiting between mounted chip-type components (¶4-5: Masunari).
In re claim 7, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 2, as explained above. Sato does not disclose wherein the insulation layer covers the first external electrode on the first surface of the ceramic body, and covers the second external electrode on the second surface of the ceramic body.
Masunari discloses wherein the insulation layer (40, 41 – Figure 12) covers the first external electrode (22a – Figure 12) on the first surface of the ceramic body (12e – Figure 12; Note that since the first external electrode covers a portion of the first surface, as required by claim 1, the first external electrode covers the first surface.), and covers the second external electrode (22b – Figure 12) on the second surface of the ceramic body (12f – Figure 12, ¶35; Note that portions 88 and 92 of the insulation layer wrap around to the end surfaces of the ceramic body [¶99].).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Masunari to prevent the occurrence of short-circuiting between mounted chip-type components (¶4-5: Masunari).
In re claim 8, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein the first plated layer comprises:
a first layer that covers the first metal layer;
a second layer that covers the first layer; and
a third layer that covers the second layer (¶49). Note that each of the plating layers cover one another from different directions.
In re claim 9, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 8, as explained above. Sato further discloses the first layer includes nickel (Ni);
the second layer includes copper (Cu);
and the third layer includes tin (Sn) (¶49; Note that each of the plating layers cover one another from different directions.).
In re claim 10, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein the second plated layer comprises:
a first layer that covers the first metal layer;
a second layer that covers the first layer; and
a third layer that covers the second layer (¶49). Note that each of the plating layers cover one another from different directions.
In re claim 11, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 10, as explained above. Sato further discloses the first layer includes nickel (Ni);
the second layer includes copper (Cu);
and the third layer includes tin (Sn) (¶49). Note that each of the plating layers cover one another from different directions.
In re claim 13, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein each of the first plated layer and the second plated layer includes (i) a layer including nickel (Ni), and a layer including tin (Sn), (ii) a first layer including tin (Sn), a layer including nickel (Ni), and a second layer including tin (Sn), or (iii) a layer including nickel (Ni), a layer including copper (Cu), and a layer including tin (Sn) (¶49).
In re claim 15, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein the first metal layer (35 of 23 – Figure 5) is disposed only on the first surface (31 – Figure 6, Figure 1) and the sixth surface (28 – Figure 1, Figure 6) of the ceramic body (22 – Figure 1, Figure 6).
In re claim 18, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 15, as explained above. Sato further discloses wherein the first plated layer (36 of 23 – Figure 5, Figure 1, Figure 6) is disposed only on the first surface (31 – Figure 1, Figure 6) and the sixth surface (28 – Figure 1, Figure 6) of the ceramic body (22 – Figure 6).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Publication 2012/0188682) in view of Masunari (US Publication 2019/0157007) and in further view of Fuji (US Publication 2017/0181288).
In re claim 12, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato does not disclose wherein each of the first plated layer and the second plated layer includes either (i) a layer including nickel (Ni), a layer including titanium (Ti), and a layer including copper (Cu), or (ii) a layer including titanium (Ti), and a layer including chromium (Cr).
Fuji discloses wherein each of the first metal layer and the second metal layer includes a nickel (Ni) layer, a layer including titanium (Ti), and a layer including copper (Cu) (¶57), or a layer including titanium (Ti), and a layer including chromium (Cr).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the outer electrode material of Fuji to achieve a device having desired conductivity.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Publication 2012/0188682) in view of Masunari (US Publication 2019/0157007).
In re claim 14, Sato in view of Masunari discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato does not disclose wherein a thickness of the first internal electrode is 100 nm or more and 300 nm or less, and a thickness of the second internal electrode is 100 nm or more and 300 nm or less. However, it is well-known in the art that adjusting the thickness of the internal electrodes is correlated with the ESR characteristics of the electronic component. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the internal electrodes to achieve a device having a desired balance between miniaturization and ESR characteristics, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the insulation layer covers a remaining portion of the first and second external electrodes.
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the insulation layer covers includes a photosensitive resin.
Claims 21-22 are allowed. The prior art does not teach nor suggest (in combination with other claim limitations) the insulation layer comprising a photosensitive resin includes a gap that exposes a first portion of an outer surface of the first external electrode, and the gap has at least one surface that is exposed. The insulation layer covers a portion of the first external electrode on the sixth surface of the ceramic body and a remaining portion of the first external electrode.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US Patent 11,817,271) Figure 2, Figure 6
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/ARUN RAMASWAMY/ Primary Examiner, Art Unit 2847
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