Prosecution Insights
Last updated: October 23, 2026
Application No. 18/439,154

MULTILAYER CERAMIC CAPACITOR

Final Rejection §103
Filed
Feb 12, 2024
Priority
Nov 02, 2023 — RE 10-2023-0149958
Examiner
RAMASWAMY, ARUN
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
4 (Final)
85%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
694 granted / 818 resolved
+16.8% vs TC avg
Moderate +12% lift
Without
With
+12.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
34 currently pending
Career history
867
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
59.7%
+19.7% vs TC avg
§102
29.7%
-10.3% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 818 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5, 7-11, 13-15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Publication 2012/0188682) in view of Yang et al. (US Publication 2020/0066444). In re claim 1, Sato discloses a multilayer ceramic capacitor, comprising: a ceramic body (22 – Figure 3, Figure 6, ¶36) comprising a first surface (31 – Figure 3, Figure 6, ¶35) and a second surface (32 – Figure 3, Figure 6, ¶35) facing each other in a first direction (Figure 6), a third surface (29 – Figure 1, Figure 3, Figure 6, ¶35) and a fourth surface (30 – Figure 1, Figure 3, Figure 6, ¶35) facing each other in a second direction (Figure 1) and connecting the first surface and the second surface (Figure 1, Figure 3, Figure 6), a fifth surface (27 – Figure 1, Figure 3, Figure 6, ¶35) and a sixth surface (28 – Figure 1, Figure 3, Figure 6, ¶35) facing each other in a third direction and connecting the first surface and the second surface (Figure 1, Figure 3, Figure 6); a plurality of first internal electrodes (25 – Figure 3, Figure 6, ¶34) and a plurality of second internal electrodes (26 – Figure 3, Figure 6, ¶34) disposed inside the ceramic body (22 – Figure 3, Figure 6); a first external electrode (23 – Figure 3, Figure 6, ¶34) disposed outside the ceramic body (Figure 6); and a second external electrode (24 – Figure 3, Figure 6, ¶34) disposed outside the ceramic body (Figure 6), wherein the first external electrode (23 – Figure 3, Figure 6) includes (i) a first metal layer (35 – Figure 5, ¶44) disposed on the first surface and the sixth surface of the ceramic body and electrically connected to the plurality of first internal electrodes (25 – Figure 3, Figure 6) on the first surface (Figure 1, Figure 3, Figure 5, Figure 6), and (ii) a first plated layer disposed on the first metal layer (¶44); and wherein the second external electrode (24 – Figure 6) includes (i) a second metal layer (35 – Figure 5, ¶44) disposed on the second surface and the sixth surface of the ceramic body and electrically connected to the plurality of second internal electrodes (26 – Figure 3, Figure 6) on the second surface (Figure 1, Figure 3, Figure 5, Figure 6), and (ii) a second plated layer disposed on the second metal layer (¶44). Sato does not disclose an insulation layer disposed on the first external electrode, wherein the insulation layer covers a portion of the first external electrode on the first surface of the ceramic body, a portion of the first external electrode on the sixth surface of the ceramic body, and a portion of the second external electrode on the sixth surface of the ceramic body, wherein the insulator layer includes a first gap that exposes a first portion of an outer surface of the first external electrode opposing the sixth surface of the ceramic body, wherein the insulation layer includes a second gap that exposes a second portion of an outer surface of the second electrode opposing the sixth surface of the ceramic body, and wherein the insulation layer covers the sixth surface of the ceramic body between the first gap and the second gap. Yang discloses an insulation layer (141, 142, 143 – Figure 1, Figure 2, Figure 3, ¶26) disposed on the first external electrode (131 and 151 – Figure 3, ¶26), wherein the insulation layer covers a portion of the first external electrode on the first surface of the ceramic body (3 – Figure 1, Figure 2, Figure 3, ¶26), a portion of the first external electrode (131 and 151 – Figure 3) on the sixth surface of the ceramic body (1 – Figure 1, Figure 2, Figure 3, ¶26), and a portion of the second external electrode (132 and 152 – Figure ¶26) on the sixth surface of the ceramic body (1 – Figure 2, Figure 3), wherein the insulator layer includes a first gap (where 151 exists – Figure 3) that exposes a first portion of an outer surface of the first external electrode opposing the sixth surface of the ceramic body (Figure 2, Figure 3), wherein the insulation layer (141, 142, 143 – Figure 2, Figure 3) includes a second gap (where 152 exists – Figure 2, Figure 3) that exposes a second portion of an outer surface of the second electrode (152 – Figure 2, Figure 3) opposing the sixth surface of the ceramic body (1 – Figure 2, Figure 3), and wherein the insulation layer (143 – Figure 2, Figure 3) covers the sixth surface of the ceramic body between the first gap and the second gap (Figure 2, Figure 3). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Yang to improve the humidity resistance of the electronic component. In re claim 3, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato does not disclose the insulation layer covers all of the outer surface of the first external electrode except the first portion of the outer surface of the first external electrode, and wherein the insulation layer covers all of the outer surface of the second external electrode except the second portion of the outer surface of the second external electrode. Yang discloses the insulation layer (141, 142, 143 – Figure 2, Figure 3) covers all of the outer surface of the first external electrode (131 and 151 – Figure 2, Figure 3) except the first portion of the outer surface of the first external electrode (portion where 151 exists – Figure 2, Figure 3), and wherein the insulation layer (141, 142, 143 – Figure 2, Figure 3) covers all of the outer surface of the second external electrode (132 and 152 – Figure 2, Figure 3) except the second portion of the outer surface of the second external electrode (portion where 152 exists – Figure 2, Figure 3). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Yang to improve the humidity resistance of the electronic component. In re claim 4, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 3, as explained above. Sato does not disclose the insulation layer wherein the first portion of the outer surface of the first external electrode that is exposed by the insulation layer has a rectangular shape including four edges surrounded by the insulation layer, as viewed in a cross-section of the multilayer ceramic capacitor. Yang discloses the insulation layer (141, 142, 143 – Figure 2, Figure 3) wherein the first portion of the outer surface of the first external electrode (portion where 151 exists – Figure 2, Figure 3) that is exposed by the insulation layer has a rectangular shape (Figure 2) including four edges surrounded by the insulation layer (Figure 2), as viewed in a cross-section of the multilayer ceramic capacitor (Figure 2). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Yang to improve the humidity resistance of the electronic component. In re claim 5, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 4, as explained above. Sato does not disclose the insulation layer wherein the second portion of the outer surface of the second external electrode that is exposed by the insulation layer has a rectangular shape including four edges surrounded by the insulation layer, as viewed in a cross-section of the multilayer ceramic capacitor. Yang discloses the insulation layer (141, 142, 143 – Figure 2, Figure 3) wherein the first portion of the outer surface of the second external electrode (portion where 152 exists – Figure 2, Figure 3) that is exposed by the insulation layer has a rectangular shape (Figure 2) including four edges surrounded by the insulation layer (Figure 2), as viewed in a cross-section of the multilayer ceramic capacitor (Figure 2). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Yang to improve the humidity resistance of the electronic component. In re claim 7, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 2, as explained above. Sato does not disclose wherein the insulation layer covers the second external electrode on the second surface of the ceramic body. Yang discloses wherein the insulation layer (141, 142, 143 – Figure 2, Figure 3) covers the second external electrode (132 and 152 – Figure 2, Figure 3) on the second surface of the ceramic body (4 – Figure 1, Figure 2). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the insulation layer of Yang to improve the humidity resistance of the electronic component. In re claim 8, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein the first plated layer comprises: a first layer that covers the first metal layer; a second layer that covers the first layer; and a third layer that covers the second layer (¶49). Note that each of the plating layers cover one another from different directions. In re claim 9, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 8, as explained above. Sato further discloses the first layer includes nickel (Ni); the second layer includes copper (Cu); and the third layer includes tin (Sn) (¶49; Note that each of the plating layers cover one another from different directions.). In re claim 10, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein the second plated layer comprises: a first layer that covers the first metal layer; a second layer that covers the first layer; and a third layer that covers the second layer (¶49). Note that each of the plating layers cover one another from different directions. In re claim 11, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 10, as explained above. Sato further discloses the first layer includes nickel (Ni); the second layer includes copper (Cu); and the third layer includes tin (Sn) (¶49). Note that each of the plating layers cover one another from different directions. In re claim 13, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein each of the first plated layer and the second plated layer includes (i) a layer including nickel (Ni), and a layer including tin (Sn), (ii) a first layer including tin (Sn), a layer including nickel (Ni), and a second layer including tin (Sn), or (iii) a layer including nickel (Ni), a layer including copper (Cu), and a layer including tin (Sn) (¶49). In re claim 14, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato does not disclose wherein a thickness of the first internal electrode is 100 nm or more and 300 nm or less, and a thickness of the second internal electrode is 100 nm or more and 300 nm or less. However, it is well-known in the art that adjusting the thickness of the internal electrodes is correlated with the ESR characteristics of the electronic component. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the internal electrodes to achieve a device having a desired balance between miniaturization and ESR characteristics, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). In re claim 15, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato further discloses wherein the first metal layer (35 of 23 – Figure 5) is disposed only on the first surface (31 – Figure 6, Figure 1) and the sixth surface (28 – Figure 1, Figure 6) of the ceramic body (22 – Figure 1, Figure 6). In re claim 18, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 15, as explained above. Sato further discloses wherein the first plated layer (36 of 23 – Figure 5, Figure 1, Figure 6) is disposed only on the first surface (31 – Figure 1, Figure 6) and the sixth surface (28 – Figure 1, Figure 6) of the ceramic body (22 – Figure 6). Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Publication 2012/0188682) in view of Yang et al. (US Publication 2020/0066444) and in further view of Fuji (US Publication 2017/0181288). In re claim 12, Sato in view of Yang discloses the multilayer ceramic capacitor of claim 1, as explained above. Sato does not disclose wherein each of the first plated layer and the second plated layer includes either (i) a layer including nickel (Ni), a layer including titanium (Ti), and a layer including copper (Cu), or (ii) a layer including titanium (Ti), and a layer including chromium (Cr). Fuji discloses wherein each of the first metal layer and the second metal layer includes a nickel (Ni) layer, a layer including titanium (Ti), and a layer including copper (Cu) (¶57), or a layer including titanium (Ti), and a layer including chromium (Cr). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the outer electrode material of Fuji to achieve a device having desired conductivity. Allowable Subject Matter Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the insulation layer covers includes a photosensitive resin. Claims 21-22 are allowed. The prior art does not teach nor suggest (in combination with other claim limitations) the insulation layer comprising a photosensitive resin includes a gap that exposes a first portion of an outer surface of the first external electrode. The insulation layer covers a portion of the first external electrode on the sixth surface of the ceramic body and a remaining portion of the first external electrode. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Han et al. (US Publication 2022/0093337) Figure 2 Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARUN RAMASWAMY/ Primary Examiner, Art Unit 2847
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Prosecution Timeline

Show 1 earlier event
Sep 22, 2025
Non-Final Rejection mailed — §103
Dec 19, 2025
Response Filed
Feb 11, 2026
Final Rejection mailed — §103
May 07, 2026
Request for Continued Examination
May 13, 2026
Response after Non-Final Action
Jun 03, 2026
Non-Final Rejection mailed — §103
Jul 28, 2026
Response Filed
Oct 06, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
85%
Grant Probability
97%
With Interview (+12.3%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 818 resolved cases by this examiner. Grant probability derived from career allowance rate.

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