DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/12/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Farhoodfar et al (US 2019/0052513) in view of Tanaka et al (US 2021/0126707).
1). With regard to claim 1, Farhoodfar et al discloses a communication device (Figures 1-2 etc.) comprising:
a plurality of communication pipelines (Figure 1, “n receive lane”) configured to receive respective input data streams ([0008], “to receive a first plurality of data streams from a first plurality of data lanes. The first plurality of data lanes includes n data lanes, where n is greater than 1”, and [0024], [0032], “In FIG. 1, n is four, but it is to be understood that n can be 2, 4, 8, 16, 32, or other numbers. For example, when n is four as shown in FIG. 1, the communication lanes can operate in various modes (e.g., a single lane with combined 200 Gbps data rate from four lanes or four individual 50 Gbps lanes”); and
a multiplexer (Figures 2 and 4-6, and function blocks 101 to 110 in Figure 1) the combination of coupled to the plurality of communication pipelines and configured to:
generate an output data stream by combining the input data streams ([0024], “In multi-link data communication systems, an important step is multiplexing, where data from two or more data lanes are combined and then redistributed”; [0061]-[0062]; Figures 2 and 4-6); and
insert one or more special characters into the output data stream ([0046], “At the state “MASTER_INIT”, the SM initiates and generates a signal “send_patt”, which is used to for transmitting a fixed data pattern. For example, the data pattern is selectable from predetermined patterns “Idles”, “Local Fault”, and “Remote Fault””; [0051], “These FIFO buffers prevent data underflows and overflows when AMs are deleted or inserted. In various operations, the output of the buffers can be replaced with a known PCS pattern (e.g., Idles, Remote Fault, or Local Fault used in SM in FIG. 3) for pattern generation, or as a fill pattern when the “AM/rate adjust” buffers undergo re-centering process when switching-over from one data path to the other”; [0061], “a set of valid 200G Idle or Remote-Fault data is generated locally while switch-over occurs.”).
But, Farhoodfar et al does not expressly state that the one or more special characters are inserted into the output data stream in response to a fault with one of the communication pipelines.
However, first, as disclosed by Farhoodfar et al, the system has a monitoring block (105), and “Rx SM blocks 105A and 105B monitor codeword streams for coding errors, and they respectively indicate errors to the link integrity FOM (Figure of Merit) calculation blocks 104A and 104B. Link integrity FOM calculation blocks are configured to determine quality and/or stat of the communication links. For example, link integrity FOM calculation blocks generate FOM values for data path A and data path B” ([0034]; and [0010]); that is, the quality of links are determined, and the link consists of data lanes ([0023]-[0024] and [0032]); then it is obvious to one skilled in the art that the Remote Fault or Local Fault can be associated with fault of the receive lanes. Second, Tanaka et al discloses a signaling scheme, in which specific bits can be used to indicate a signal quality of a physical link (Figure 6, p Bits; [0052] - [0062]; and Abstract, “signal quality information representing signal quality calculated for a physical link in each of the sections through which the relay data is transmitted”; and Figure 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanaka et al with Farhoodfar et al so that the fault information can be convey to the subsequent device or node; and the functions of the system/method is enhanced.
2). With regard to claim 2, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. And the combination of Farhoodfar et al and Tanaka et al further discloses wherein the multiplexer is configured to maintain independence of the respective input data streams from the plurality of communication pipelines in the output data stream (Farhoodfar: [0032], “In FIG. 1, n is four, but it is to be understood that n can be 2, 4, 8, 16, 32, or other numbers. For example, when n is four as shown in FIG. 1, the communication lanes can operate in various modes (e.g., a single lane with combined 200 Gbps data rate from four lanes or four individual 50 Gbps lanes)”, [0038], “In operation, both PCS slices provide generalized PCS functions for single or multi-lane protocols up to 200 Gbps. These functions include FEC decoding and encoding, rate adjustment, and AM generation for conversion between protocols with and without AMs (or with different AM rates).”; [0052], “The “100/50/40/25G AM gen” block generates the specified AM sequences for the required protocol in conjunction with the “BIP calc” block. The “BIP calc” block calculates the “AM Bit Interleaved” parity fields used in 40 and 100G Ethernet protocols. The AMs generated by the “100/50/40/25G AM gen” block are inserted into the 4*64b66b codeword stream, which is ready for lane distribution for non-FEC protocols. In various embodiments, RS-FEC based protocols convert the 4*64b66b codeword stream into 256b257 words in the “4*64b->257b Transcode” block before calculating and adding FEC parity in the “FEC Encode” block”; [0062], “For data transferring with 25/50/100G Ethernet, data rate adjustment and/or AM buffering are performed. Fill data are generated for the multiplexer switchover process, if data transfer needs to switch from one set of data paths to another. New AMs are then generated (with bit interface parity if need), and data are scrambled”; that is, the multiplexer maintains independence of the respective input data streams from the plurality of communication pipelines in the output data stream).
3). With regard to claim 3, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. And the combination of Farhoodfar et al and Tanaka et al further discloses wherein each of the communication pipelines is configured to receive the respective input data stream at a first data rate (e.g., 50 Gbps, [0032], or [0024], 25 G, or 50 G, or 100 G) and wherein the multiplexer is configured to generate the output data stream for transmission at a second data rate (e.g., 200 Gbps, [0032], [0038] and [0061]) that is greater than the first data rate.
4). With regard to claim 4, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. And the combination of Farhoodfar et al and Tanaka et al further discloses wherein each of the communication pipelines is configured to receive the respective input data stream comprising first data blocks having a first format compatible for transmission at a first data rate (Farhoodfar: the input data stream can be a data rate of 10 G, 25 G, 50 G or 100 G, [0024], [0032] and [0042] etc. “For example, at 10G and 25G rates, the “Rx SM” blocks implement the Clause 49 PCS receive State diagram as specified according to the IEEE P802.3-2015 standard. For operating modes at 40G, 50G & 100G rates, the block operates according to the Clause 82 PCS receive State diagram specified under IEEE P802.3-2015”; and the data streams are in data blocks or codewords, [0033]-[0036] and [0039]-[0041], and “As shown in FIG. 2, each slice has two input sources/formats: 320-bit wide aligned data for RS-FEC encoded Ethernet protocols, and 4*64b66b data for non RS-FEC protocols. RS-FEC encoded Ethernet protocols are decoded and corrected in the “FEC decode and correct” block, then transcoded into 4*64b66b codewords in the “257b->4*64b Transcode” block, thereby allowing all subsequent processes to operate on 4*64b66b codewords.”; therefore, it is obvious that the input data stream at each input lane comprises data blocks that have a first format compatible for transmission at a first data rate, e.g., 25G, 50G or 100G), and wherein the multiplexer is configured to generate the output data stream comprising second data blocks having a second format compatible for transmission at a second data rate that is greater than the first data rate (Farhoodfar: the output data stream can be 200 Gbps, [0032], [0038] and [0061]; then it is obvious that the output data stream comprises second data blocks having a second format compatible for transmission at a second data rate, e.g., 200G, that is greater than the first data rate, e.g., 25G, 50G or 100G).
5). With regard to claim 6, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. And the combination of Farhoodfar et al and Tanaka et al further discloses wherein the communication pipelines receive the respective input data streams with matching data rates (Farhoodfar: [0032], “from four lanes or four individual 50 Gbps lanes”).
6). With regard to claim 18, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. And the combination of Farhoodfar et al and Tanaka et al further discloses wherein the multiplexer is configured to insert alignment markers delineating boundaries of data blocks in the output data stream (Farhoodfar: [0024], alignment marker AM is used, “a communication system performs RS FEC and uses AMs for lane identification and de-skew. Additionally, the system also uses AMs to identify FEC block boundaries.”, [0061], “AMs and FEC blocks are generated locally, which is to ensure that FEC boundary and AM location do not change on switch-over”).
7). With regard to claim 19, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. And the combination of Farhoodfar et al and Tanaka et al further discloses the communication device of claim 1 further comprising an encoder configured to implement a parity scheme to increase a data rate of the output data stream relative to the input data streams (Farhoodfar: [0036], “at block 109 data are transcoded into the FEC frame format, and FEC parity information is generated”, [0052], “The “BIP calc” block calculates the “AM Bit Interleaved” parity fields used in 40 and 100G Ethernet protocols. The AMs generated by the “100/50/40/25G AM gen” block are inserted into the 4*64b66b codeword stream, which is ready for lane distribution for non-FEC protocols. In various embodiments, RS-FEC based protocols convert the 4*64b66b codeword stream into 256b257 words in the “4*64b->257b Transcode” block before calculating and adding FEC parity in the “FEC Encode” block”, and [0062]; and as discussed in claim 1 rejection, Farhoodfar discloses that the data rate of the output data stream is higher than the data rates of the input data streams).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Farhoodfar et al and Tanaka et al as applied to claim 1 above, and further in view of Cheng et al (US 6,151,336) and Sheth et al (US 2004/0202205).
Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the communication pipelines receive the respective input data streams with data rates offset from each other.
However, first, Farhoodfar discloses “In multi-link data communication systems, an important step is multiplexing, where data from two or more data lanes are combined and then redistributed. During the process of combining and redistributing data, alignment markers (AM) are used. Among other things, AMs are used to remove static inter-lane skew and reconstruct the original order of data words. For example, AMs are inserted into the data streams sent on each lane to identify the lane and allow data to be re-aligned to remove any differential skews between lanes” ([0024]), and Farhoodfar also discloses that the input data streams can have data rates: 10 G, 25 G, 50 G and 100 G etc.; therefore, the communication pipelines can receive the respective input data streams with data rates offset from each other. Another prior art, Cheng et al, discloses a similar communication device (Figures 1-2 and 4-6 etc.) “allowing for the time division multiplexed transmission of lower speed information-bearing signals without regard to data rate or transmission format”, that is, the input data steams can have data rates offset from each other. Sheth et al discloses a system/method for “multiplexing and transparent transportation of multiple Gigabit Ethernet, Fibre Channel and other packet based data streams without protocol conversion over a high-speed data channel with Forward Error Correction” ([0002]); and “At ingress block 145, there is a timing uncertainty of approximately +/-100 parts per million (ppm) from the received nominal GBE of 1.25 Gbps from each data stream. The timing uncertainty is tracked and corrected in the ingress block 145” ([0048]) and “Multiple plesiochronous Gigabit Ethernet data streams are aggregated onto an independent clock source at an ingress circuit through the use of transparent IDLE character insertion. The independent clock is selected such that the output data rate is greater than the composite input data rate of all the plesiochronous data streams” (Abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cheng et al and Sheth et al to the system/method of Farhoodfar et al and Tanaka et al so that data steams with different rates or with rate offset can be multiplexed/combined, and then sent with higher transmission speed.
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Farhoodfar et al and Tanaka et al as applied to claim 1 above, and further in view of Azizoglu et al (US 6,430,201) and Humphrey et al (US 6,396,853).
1). With regard to claim 7, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the communication pipelines operate asynchronously with the output data stream.
However, Azizoglu et al discloses a system/method for “accept and multiplex multiple GbE/FC signals into a synchronous format signal such as a SONET signal, in order to provide for multiplexing, adding/dropping, and monitoring LAN traffic in an optical backbone” (column 2 lines 59-63) and “The transmitter converts sequential data blocks of each non-encoded signal into corresponding packets, and asynchronously interleaves the packets of the non-encoded signals to create the multiplexed data signal” (column 3 lines 25-39) and “The rate-reduced streams are supplied to multiplexing and framing logic 26, which multiplexes the streams together using an asynchronous statistical multiplexing technique described below, and maps the multiplexed streams into synchronous frames in the OC-48 signa” (column 4 lines 38-62), and “[t]he method described here is also applicable when one of the inputs is a Gbe signal and the other is a FC signal. Since the two inputs operate on separate clocks, the appropriate clock rates (one at 1.25 GHz and one at 1.0625 GHz) enable the operation with hybrid GbE/FC inputs without any modifications to the transmitter/receiver hardware” (column 6 line 19-24); that is, the input low speed data operate asynchronously with the output data stream. Another prior art, Humphrey et al, discloses a similar signal multiplexing scheme “by multiplexing one or more plesiochronous packet data channels together with lower priority asynchronous traffic into a single composite data stream for transmission over the loop” (Abstract); as shown in Figure 6, “Bytes of incoming data are clocked into the FIFO by the input clock signal, which is derived from the incoming plesiochronous data stream and is therefore not, in general, synchronous with any other local clock signal. As each input byte arrives, the value of the byte counter increases by one. At the scheduled transmission time, bytes are clocked out of the FIFO at the multiplexed transmission byte clock rate. Each time a byte is clocked out of the FIFO the value of the byte counter decreases by one. The local transmit clock source 102 drives a counter 103 which indicates local `time` in clock pulse increments”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Azizoglu et al and Humphrey et al to the system/method of Farhoodfar et al and Tanaka et al so that data steams with different rates or plesiochronous traffic can be multiplexed/combined, and then sent with higher transmission speed.
2). With regard to claim 13, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the multiplexer is configured to multiplex the input data streams asynchronously to generate the output data stream.
However, Azizoglu et al discloses a system/method for “accept and multiplex multiple GbE/FC signals into a synchronous format signal such as a SONET signal, in order to provide for multiplexing, adding/dropping, and monitoring LAN traffic in an optical backbone” (column 2 lines 59-63) and “The transmitter converts sequential data blocks of each non-encoded signal into corresponding packets, and asynchronously interleaves the packets of the non-encoded signals to create the multiplexed data signal” (column 3 lines 25-39) and “The rate-reduced streams are supplied to multiplexing and framing logic 26, which multiplexes the streams together using an asynchronous statistical multiplexing technique described below, and maps the multiplexed streams into synchronous frames in the OC-48 signa” (column 4 lines 38-62), and “[t]he method described here is also applicable when one of the inputs is a Gbe signal and the other is a FC signal. Since the two inputs operate on separate clocks, the appropriate clock rates (one at 1.25 GHz and one at 1.0625 GHz) enable the operation with hybrid GbE/FC inputs without any modifications to the transmitter/receiver hardware” (column 6 line 19-24); that is, the input low speed data operate asynchronously with the output data stream. Another prior art, Humphrey et al, discloses a similar signal multiplexing scheme “by multiplexing one or more plesiochronous packet data channels together with lower priority asynchronous traffic into a single composite data stream for transmission over the loop” (Abstract); as shown in Figure 6, “Bytes of incoming data are clocked into the FIFO by the input clock signal, which is derived from the incoming plesiochronous data stream and is therefore not, in general, synchronous with any other local clock signal. As each input byte arrives, the value of the byte counter increases by one. At the scheduled transmission time, bytes are clocked out of the FIFO at the multiplexed transmission byte clock rate. Each time a byte is clocked out of the FIFO the value of the byte counter decreases by one. The local transmit clock source 102 drives a counter 103 which indicates local `time` in clock pulse increments”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Azizoglu et al and Humphrey et al to the system/method of Farhoodfar et al and Tanaka et al so that the multiplexer can multiplex the input data streams asynchronously to generate the output, and data stream data steams with different rates or plesiochronous traffic can be multiplexed/combined.
Claims 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Farhoodfar et al and Tanaka et al as applied to claim 1 above, and further in view of Cheng et al (US 6,151,336) and Nicholson et al (US 2002/0080809).
1). With regard to claim 8, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the communication pipelines operate synchronously with the output data stream.
However, Cheng et al discloses a system/method to “transmit multiple channels of information on a single channel of a Dense Wavelength Division Multiplexing (DWDM) system, and accommodates a variety of data formats and data rate” (column 1 lines 5-9), as shown in Figure 2, “[t]he clock generator 240 receives the data speed of the input signal from the data buffers (e.g., 202, 204 and 206) and generates a main system clock, in the form of synchronous pulses, based upon the speed of the input signal, to control that time division multiplexer (e.g., 200-A). The synchronous pulses are sent to the encoders (212, 214, and 216), the data scramblers (222, 224 and 226), the channel ID generator 250, and the time division multiplexing unit 230. The synchronous pulses sent to the various components may be a different speeds, depending upon the component. For example, because the encoders add a data bit to the signals (see below) a faster pulse is required to that component. In a preferred embodiment, the clock will initially read data speed from data buffer 202. If a data speed is readable from that buffer, the clock will transmit the synchronous pulse described above.”; the clock generator 240 obtains the clock information from terminals 102-106 and then generates a main system clock, “in the form of synchronous pules” (column 5 line 49 to column 6 line 18); that is, the input terminal signals operate synchronously with the output data stream. Another prior art, Nicholson et al, discloses a similar multiplexing scheme, as shown in Figure 5, “Each digital data input 502 may be operable to receive a synchronous digital data stream from a digital source, such as a digital camera, while the corresponding clock input 504 concurrently receives a corresponding clock signal” ([0055]; also refer [0049]) and “Each clock signal may be transmitted to the clock MUX 512 which may be operable to select one of the MUXed clock signals and transmit the selected clock signal to the data MUX 510, the FIFOs 506, and the transition state machine 514. In one embodiment, a plurality of clock multiplexers 512 may be used to receive clock signals from the plurality of clock inputs 504 and to select the single selected clock signal for transmittal to other components of the system” ([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cheng et al and Nicholson et al to the system/method of Farhoodfar et al and Tanaka et al so that the input data streams operate synchronously with the output data stream, and a synchronous data stream multiplexing system can be obtained.
2). With regard to claim 14, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the multiplexer is configured to multiplex the input data streams synchronously to generate the output data stream.
However, Cheng et al discloses a system/method to “transmit multiple channels of information on a single channel of a Dense Wavelength Division Multiplexing (DWDM) system, and accommodates a variety of data formats and data rate” (column 1 lines 5-9), as shown in Figure 2, “[t]he clock generator 240 receives the data speed of the input signal from the data buffers (e.g., 202, 204 and 206) and generates a main system clock, in the form of synchronous pulses, based upon the speed of the input signal, to control that time division multiplexer (e.g., 200-A). The synchronous pulses are sent to the encoders (212, 214, and 216), the data scramblers (222, 224 and 226), the channel ID generator 250, and the time division multiplexing unit 230. The synchronous pulses sent to the various components may be a different speeds, depending upon the component. For example, because the encoders add a data bit to the signals (see below) a faster pulse is required to that component. In a preferred embodiment, the clock will initially read data speed from data buffer 202. If a data speed is readable from that buffer, the clock will transmit the synchronous pulse described above.”; the clock generator 240 obtains the clock information from terminals 102-106 and then generates a main system clock, “in the form of synchronous pules” (column 5 line 49 to column 6 line 18); that is, the input terminal signals operate synchronously with the output data stream. Another prior art, Nicholson et al, discloses a similar multiplexing scheme, as shown in Figure 5, “Each digital data input 502 may be operable to receive a synchronous digital data stream from a digital source, such as a digital camera, while the corresponding clock input 504 concurrently receives a corresponding clock signal” ([0055]; also refer [0049]) and “Each clock signal may be transmitted to the clock MUX 512 which may be operable to select one of the MUXed clock signals and transmit the selected clock signal to the data MUX 510, the FIFOs 506, and the transition state machine 514. In one embodiment, a plurality of clock multiplexers 512 may be used to receive clock signals from the plurality of clock inputs 504 and to select the single selected clock signal for transmittal to other components of the system” ([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cheng et al and Nicholson et al to the system/method of Farhoodfar et al and Tanaka et al so that the multiplexer can multiplex the input data streams synchronously to generate the output data stream, and a synchronous data stream multiplexing system can be obtained
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Farhoodfar et al and Tanaka et al as applied to claim 1 above, and further in view of Azizoglu et al (US 6,430,201) and Cheng et al (US 6,151,336).
1). With regard to claim 9, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the communication pipelines are configured to operate based on one or more first clocks and wherein the multiplexer is configured to operate based on a second clock different from the first clock.
However, it is common in the art that a specific data rate is related to a specific clock rate. Since Farhoodfar et al discloses than the input data stream has a data rate of 10 G, 25 G and 50 G and output data stream has a data rate of 200 G, it is obvious to one skilled in the art that input lanes are configured to operate based on one or more first clocks and wherein the multiplexer is configured to operate based on a second clock (e.g. 200 G) different from the first clock. E.g., Azizoglu et al discloses a multiplexing scheme, the input data rate is 1.25 Gb/s, and multiplexed signal has a 2.488 Gb/s, and “Since the two inputs operate on separate clocks, the appropriate clock rates (one at 1.25 GHz and one at 1.0625 GHz) enable the operation with hybrid GbE/FC inputs without any modifications to the transmitter/receiver hardware” (column 6 line 19-24). And another prior art, Another prior art, Cheng et al, discloses a similar communication device (Figures 1-2 and 4-6 etc.), as shown in Figure 2, the multiplexer 230 operates based on a second clock (claim 1, “form a respective encoded data signal having a faster data rate than said respective input data speed” and “a multiplexing clock for outputting at least one synchronizing pulse at said faster data rate for use within said first station”) different from the first clock (Abstract: “an expansion subsystem for dense wavelength division multiplexing systems allowing for the time division multiplexed transmission of lower speed information-bearing signals without regard to data rate or transmission format.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Azizoglu et al and Cheng et al to the system/method of Farhoodfar et al and Tanaka et al so that data streams with different rates can be multiplexed and transmitted properly.
2). With regard to claim 10, Farhoodfar et al and Tanaka et al Azizoglu et al and Cheng et al disclose all of the subject matter as applied to claims 1 and 9 above. And the combination of Farhoodfar et al and Tanaka et al Azizoglu et al and Cheng et al discloses wherein the one or more first clocks are based on the first data rate (Azizoglu eand Cheng disclose that the clocks of the input data streams are based on the first data rate) and wherein the second clock is based on the second data rate (Azizoglu eand Cheng: based on the multiplexed signal).
3). With regard to claim 11, Farhoodfar et al and Tanaka et al Azizoglu et al and Cheng et al disclose all of the subject matter as applied to claims 1 and 9-10 above. And the combination of Farhoodfar et al and Tanaka et al Azizoglu et al and Cheng et al discloses wherein the second clock is derived from the one or more first clocks (Cheng: Figure 2, the clock generator 240 is based on the one or more first clocks).
4). With regard to claim 12, Farhoodfar et al and Tanaka et al Azizoglu et al and Cheng et al disclose all of the subject matter as applied to claims 1 and 9 above. And the combination of Farhoodfar et al and Tanaka et al Azizoglu et al and Cheng et al discloses wherein the second clock is independent of the one or more first clocks (Farhoodfar: the multiplexed signal can be 200 G, which does not depend on the input data rate 10 G, 25 G or 50 G etc.).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Farhoodfar et al and Tanaka et al as applied to claim 1 above, and further in view of Tiruvur et al (US 2017/0187555) and Laksono et al (US 2003/0095594) and Levinson et al (US 2008/0019706).
1). With regard to claim 15, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claims 1 and 3 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the communication pipelines are configured to insert or delete one or more characters in the respective input data streams to compensate for a difference between the first data rate and the second data rate.
However, first, Farhoodfar et al discloses “Alignment markers are inserted into the data transmitted through the selected set of data links” ([0021]), “AMs are inserted into the data streams sent on each lane to identify the lane and allow data to be re-aligned to remove any differential skews between lanes” ([0024]), and “The “100/50/40/25G AM gen” block generates the specified AM sequences for the required protocol in conjunction with the “BIP calc” block. The “BIP calc” block calculates the “AM Bit Interleaved” parity fields used in 40 and 100G Ethernet protocols. The AMs generated by the “100/50/40/25G AM gen” block are inserted into the 4*64b66b codeword stream, which is ready for lane distribution for non-FEC protocols” ([0052]); that is, the AM can be used as a type of compensation. Another prior art, Tiruvur et al, discloses a communication system (Figure 1 etc.), in which a plurality of input signals (120) are received and a multiplexed signal is output (130), and the virtual line lock and buffer (e.g., 102/103) also performs “locking, which is used to achieve block synchronization (block locking) and virtual lane lock, and to write the code-word to the alignment and deskew FIFO” ([0060]) and “align data signal received from the four input lanes” ([0064]) and “The deskew FIFO modules are needed to account for the skew and skew variations across the physical lanes in 40G mode and virtual and physical lanes in 100G mode” ([0066]); that is, the virtual line lock and buffer provide a type of process/function that determines a rate difference and compensates the decoded first data stream at the first buffer if the difference is non-zero. And, Laksono et al, discloses data rate processing system/method, in which a fullness of a buffer can be determined based on a difference between an input rate and a output rate (claims 8, 28 and 59). And another prior art, Levinson et al discloses that some idle data (e.g., “I” in Figure 6B) can be inserted in a data stream (Figure 6), and “The control logic circuit 227 operates in this mode when the amount of data stored in the memory devices is below the threshold fullness level …, the control logic will insert four idles after the end of the next B frame when the fullness value has a value indicating the memory devices are below the threshold fullness level”. That is, the combination of Farhoodfar et al and Tanaka et al and Tiruvur et al and Laksono et al and Levinson et al teaches/suggests to determine a difference between an input rate and output rate, and to insert or delete one or more characters in the respective input data streams to compensate for a difference between the first data rate and the second data rate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tiruvur et al and Laksono et al and Levinson et al to the system/method of Farhoodfar et al and Tanaka et al so that the difference between an input rate and an output rate can be determined, and compensation processing (adding idle bit etc.) can be performed, and the system function is enhanced.
2). With regard to claim 16, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claims 1 and 3 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the communication pipelines are configured to insert or delete one or more characters in the respective input data streams in response to a variation in the first data rate.
However, first, Farhoodfar et al discloses that the input data streams can have different data rate (10 G, 25 G, 50 G or 100 G), and Farhoodfar et al discloses “Alignment markers are inserted into the data transmitted through the selected set of data links” ([0021]), “AMs are inserted into the data streams sent on each lane to identify the lane and allow data to be re-aligned to remove any differential skews between lanes” ([0024]), and “The “100/50/40/25G AM gen” block generates the specified AM sequences for the required protocol in conjunction with the “BIP calc” block. The “BIP calc” block calculates the “AM Bit Interleaved” parity fields used in 40 and 100G Ethernet protocols. The AMs generated by the “100/50/40/25G AM gen” block are inserted into the 4*64b66b codeword stream, which is ready for lane distribution for non-FEC protocols” ([0052]); that is, the AM can be inserted in response to a variation in the first data rate. Another prior art, Tiruvur et al, discloses a communication system (Figure 1 etc.), in which a plurality of input signals (120) are received and a multiplexed signal is output (130), and the virtual line lock and buffer (e.g., 102/103) also performs “locking, which is used to achieve block synchronization (block locking) and virtual lane lock, and to write the code-word to the alignment and deskew FIFO” ([0060]) and “align data signal received from the four input lanes” ([0064]) and “The deskew FIFO modules are needed to account for the skew and skew variations across the physical lanes in 40G mode and virtual and physical lanes in 100G mode” ([0066]); that is, the virtual line lock and buffer provide a type of process/function that determines a rate difference and compensates the decoded first data stream at the first buffer if the difference is non-zero. And, Laksono et al, discloses data rate processing system/method, in which a fullness of a buffer can be determined based on a difference between an input rate and a output rate (claims 8, 28 and 59). And another prior art, Levinson et al discloses that some idle data (e.g., “I” in Figure 6B) can be inserted in a data stream (Figure 6), and “The control logic circuit 227 operates in this mode when the amount of data stored in the memory devices is below the threshold fullness level …, the control logic will insert four idles after the end of the next B frame when the fullness value has a value indicating the memory devices are below the threshold fullness level”. That is, the combination of Farhoodfar et al and Tanaka et al and Tiruvur et al and Laksono et al and Levinson et al teaches/suggests to insert or delete one or more characters in the respective input data streams in response to a variation in the first data rate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tiruvur et al and Laksono et al and Levinson et al to the system/method of Farhoodfar et al and Tanaka et al so that the differences between among the input rates and an output rate can be determined, and characters can be insert or delete in the respective input data streams in response to a variation in the first data rate, and the signal multiplexing can be made easier, and the system function is enhanced.
3). With regard to claim 17, Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claims 1 and 3 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the communication pipelines are configured to insert or delete one or more characters in the respective input data streams to compensate for a variation in the first data rate.
However, first, Farhoodfar et al discloses “Alignment markers are inserted into the data transmitted through the selected set of data links” ([0021]), “AMs are inserted into the data streams sent on each lane to identify the lane and allow data to be re-aligned to remove any differential skews between lanes” ([0024]), and “The “100/50/40/25G AM gen” block generates the specified AM sequences for the required protocol in conjunction with the “BIP calc” block. The “BIP calc” block calculates the “AM Bit Interleaved” parity fields used in 40 and 100G Ethernet protocols. The AMs generated by the “100/50/40/25G AM gen” block are inserted into the 4*64b66b codeword stream, which is ready for lane distribution for non-FEC protocols” ([0052]); that is, the AM can be used as a type of compensation. Another prior art, Tiruvur et al, discloses a communication system (Figure 1 etc.), in which a plurality of input signals (120) are received and a multiplexed signal is output (130), and the virtual line lock and buffer (e.g., 102/103) also performs “locking, which is used to achieve block synchronization (block locking) and virtual lane lock, and to write the code-word to the alignment and deskew FIFO” ([0060]) and “align data signal received from the four input lanes” ([0064]) and “The deskew FIFO modules are needed to account for the skew and skew variations across the physical lanes in 40G mode and virtual and physical lanes in 100G mode” ([0066]); that is, the virtual line lock and buffer provide a type of process/function that determines a rate difference and compensates the decoded first data stream at the first buffer if the difference is non-zero. And, Laksono et al, discloses data rate processing system/method, in which a fullness of a buffer can be determined based on a difference between an input rate and a output rate (claims 8, 28 and 59). And another prior art, Levinson et al discloses that some idle data (e.g., “I” in Figure 6B) can be inserted in a data stream (Figure 6), and “The control logic circuit 227 operates in this mode when the amount of data stored in the memory devices is below the threshold fullness level …, the control logic will insert four idles after the end of the next B frame when the fullness value has a value indicating the memory devices are below the threshold fullness level”. That is, the combination of Farhoodfar et al and Tanaka et al and Tiruvur et al and Laksono et al and Levinson et al teaches/suggests to insert or delete one or more characters in the respective input data streams to compensate for a variation in the first data rate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Tiruvur et al and Laksono et al and Levinson et al to the system/method of Farhoodfar et al and Tanaka et al so that the variation in the first data rate can be determined, and compensation processing (adding idle bit etc.) can be performed, and the system function is enhanced.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Farhoodfar et al and Tanaka et al as applied to claim 1 above, and further in view of Levinson et al (US 2008/0019706).
Farhoodfar et al and Tanaka et al disclose all of the subject matter as applied to claim 1 above. But, Farhoodfar et al and Tanaka et al do not expressly disclose wherein the multiplexer is configured to receive the respective input data streams from the communication pipelines using a round robin scheme.
However, for multiplexing multiple lanes of low speed into one channel of higher speed, it is common in the art that a multiplexer receives the respective input data streams from the input lanes using a round robin scheme. E.g., Levinson et al teaches “When the number of data channels is N (e.g., eight), the data channel whose data is included in each data word is rotated in round robin fashion” ([0136]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the round-robin scheme as taught by Levinson et al to the system/method of Farhoodfar et al and Tanaka et al so that the data signals in multiple lanes can be conveniently and properly and more uniformly multiplexed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7734183 B2
US 20030192006 A1
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/LI LIU/Primary Examiner, Art Unit 2634 February 21, 2026