Prosecution Insights
Last updated: October 27, 2026
Application No. 18/439,531

LIGHT-EMITTING ELEMENT PACKAGE, DISPLAY DEVICE USING THE SAME, AND METHOD FOR MANUFACTURING DISPLAY DEVICE

Non-Final OA §102
Filed
Feb 12, 2024
Priority
May 11, 2023 — RE 10-2023-0061145
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Electronics Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1534 granted / 1675 resolved
+23.6% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
46 currently pending
Career history
1706
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
43.1%
+3.1% vs TC avg
§102
39.5%
-0.5% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1675 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of claims 1, 8-13, and 28-29 in the reply filed on 6/8/26 is acknowledged. The traversal is on the ground(s) that SEE ELECTION DATED 6/8/26. This is not found persuasive because the consideration (interpretation and weight assignment) and searches are not co-extensive. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hashimoto et al. (US pat 12604529). With respect to claim 1, Hashimoto et al. teach a light-emitting element package comprising (see figs. 1-26, particularly fig. 6 and associated text): a first layer (layer around 9) including a terminal 10; a second layer (a driving layer) (layer around 8) located adjacent to the first layer and including a driving chip 8; a third layer (a light-emitting layer) 3 located adjacent to the second layer, wherein the third layer includes light-emitting elements 2, wherein each light-emitting element at least partially overlaps the driving chip in a connection direction (vertical) of the first layer and the second layer and constitutes a unit subpixel 2; and a fourth layer 5 located adjacent to the third layer, wherein light emitted from the light-emitting elements passes through the fourth layer, wherein a first electrode 6 (of middle chip 2) of each of the light-emitting elements is connected to a first end (left, bottom) of the driving chip and a second end (right, top) of the driving chip is connected to the terminal 10. Claim(s) 28 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hashimoto et al. (US pat 12604529). With respect to claim 28, Hashimoto et al. teach a light-emitting element package comprising (see figs. 1-26, particularly fig. 6 and associated text): a transparent substrate 5; a light-emitting layer (layer around 2) located on the transparent substrate and including light-emitting elements 2 respectively constituting unit subpixels 2; a driving layer (layer around 8) located on the light-emitting layer and at least partially overlapping the light-emitting layer, wherein the driving layer includes a driving chip 8 electrically connected to the light-emitting elements and configured to drive the light-emitting elements; and a terminal layer (layer around 9) located on the driving layer and including a terminal 10 connected to the driving chip. Claim(s) 29 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hashimoto et al. (US pat 12604529). With respect to claim 29, Hashimoto et al. teach a display device comprising (see figs. 1-26, particularly fig. 6 and associated text): a light-emitting element package defining an individual pixel, wherein the light-emitting element package includes: a transparent substrate 5; a light-emitting layer (layer around 2) located on the transparent substrate and including light-emitting elements 2 respectively constituting unit subpixels; a driving layer (layer around 8) located on the light-emitting layer and at least partially overlapping the light-emitting layer, wherein the driving layer includes a driving chip 8 electrically connected to the light-emitting elements and configured to drive the light-emitting elements; and a terminal layer (layer around 9) located on the driving layer and including a terminal 10 connected to the driving chip. Allowable Subject Matter Claims 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having stacked light emitting structure and driving circuit structure and connectors for connecting driving circuit structure, light emitting structure and external terminals as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Feb 12, 2024
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12765420
SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD
3y 9m to grant Granted Oct 13, 2026
Patent 12760145
POLYMER COMPOUND, AND ELECTROLUMINESCENT DEVICE MATERIAL AND ELECTROLUMINESCENT DEVICE INCLUDING POLYMER COMPOUND
3y 0m to grant Granted Oct 13, 2026
Patent 12765378
SEMICONDUCTOR APPARATUS
2y 4m to grant Granted Oct 13, 2026
Patent 12757762
WIRING BOARD, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
3y 7m to grant Granted Oct 06, 2026
Patent 12751320
CHIP-ON-WAFER-ON-BOARD STRUCTURE USING SPACER DIE AND METHODS OF FORMING THE SAME
4y 3m to grant Granted Sep 29, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1675 resolved cases by this examiner. Grant probability derived from career allowance rate.

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