DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 includes a limitation describing “detecting of a pattern of randomly storing data.” It is unclear what the applicant means by randomly storing data in a deterministic system including address management and cache coherency mechanisms. For the purposes of examination randomly will be given its standard meaning: without method or conscious decision; indiscriminately.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over HORWICH et al. (US PGPub No. 2021/0374080), hereinafter referred to as HORWICH, in view of Sharifie et al. (US PGPub No. 2017/0060422), hereinafter referred to as SHARIFIE.
Consider Claim 1,
HORWICH teaches a method, comprising:
attaching, by a memory sub-system over a connection from a host interface of the memory sub-system to a host system (HORWICH, e.g., Fig 1(105);Fig 3A(305), CXL bus.), a first portion of memory resources of the memory sub-system as a memory device accessible to the host system over the connection using a first protocol of cache-coherent memory access (HORWICH, e.g., Fig 3A(130,140), memory;Fig 3A(300), coherent interconnect fabric.);
attaching, by the memory sub-system over the connection, a second portion of the memory resources of the memory sub-system as a storage device accessible to the host system over the connection using a second protocol of storage access (HORWICH, e.g., Fig 3A(130,140), NVM connected via cNVMe Controller (322) provides storage access.);
receiving, by the memory sub-system over the connection according to the first protocol of cache-coherent memory access, a first request to read data at a memory address in the memory device (HORWICH, e.g., Fig 11A(1102), receive request from host; Fig 3A(1112,1113), coherency elements.);
generating, by the memory sub-system, a command according to the first request (HORWICH, e.g., Fig 11A(1108), SDM generates request.);
entering, by the memory sub-system, the command into a queue (HORWICH, e.g., ¶0017 describes placing commands in CMB submission queues.); and
executing, by the memory sub-system, the command from the queue to read the data at the memory address in the memory device (HORWICH, e.g., Fig 10A, read command from submission queue and execute command.).
HORWICH describes both read and write commands (HORWICH, e.g., ¶0087), but fails to expressly describe system operation for write commands. SHARIFIE describes systems and methods for managing an external memory apparatus and is considered analogous prior art. SHARIFIE does describe both reading and writing data using a command queue (SHARIFIE, e.g., ¶0050-0052). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of HORWICH to use store commands along with read commands in a buffer as taught by SHARIFIE because it is ubiquitous in the art and offers the clear benefit of storing information into the memory for retrieval.
Consider Claim 2,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the connection is according to a standard of compute express link (HORWICH, e.g., Fig 3A(305), CXL bus.).
Consider Claim 3,
The system of HORWICH and SHARIFIE, as combined, further teaches buffering the data in the queue, wherein execution of the command writes the data from the queue into the memory device (HORWICH, e.g., Fig 6(615); ¶0087, submission identifies memory location of cache used for transfer to/from storage. The memory location identifies part of the cache as an extension of the submission queue (i.e., incorporation by reference).).
Consider Claim 4,
The system of HORWICH and SHARIFIE, as combined, further teaches:
allocating, by the memory sub-system, a first portion of a volatile random access memory of the memory sub-system as a cache memory (HORWICH, e.g., Fig 2(230);¶0075, local memory acts as a cache for the NVM.), wherein the first portion of memory resources of the memory sub-system includes a non-volatile random access memory slower than the volatile random access memory (HORWICH, e.g., Fig 3A, NVM is slower the DRAM.);
configuring, by the memory sub-system, the cache memory to cache one or more pages of a memory space provided by the memory device (HORWICH, e.g., ¶0075, data is moved between a local memory (cache) and NVM.);
receiving, in the memory sub-system from the host system over the connection using the first protocol of cache-coherent memory access, one or more second requests to store data into the memory device (HORWICH, e.g., ¶0114, receive one or more commands.); and
processing, by the memory sub-system, the one or more second requests via operating on one or more pages of the memory device cached in the cache memory (HORWICH, e.g., Fig 17(1710-1750); ¶0114, process commands.).
Consider Claim 5,
The system of HORWICH and SHARIFIE, as combined, describes the method of claim 4, above, and further describes that the submission (i.e., command) includes a field for specifying a memory location (HORWICH, e.g., Fig 6(615)) and that the memory location specifies cache lines in a coherent memory space where the payload is to be transferred to or from (HORWICH, e.g., ¶0087). HORWICH fails to expressly describe wherein the generating of the command according to the first request is in response to a determination that the cache memory has insufficient capacity to cache a page of the memory device at the memory address at a time of receiving the first request. The examiner takes official notice of the fact that checking a container for fullness before deciding to add something to the container is ubiquitous in the art and general human experience. It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of HORWICH and SHERIFIE, as combined, such that the generating of the command according to the first request is in response to a determination that the cache memory has insufficient capacity to cache a page of the memory device at the memory address at a time of receiving the first request because it improves memory usage and avoids errors associated with specifying a memory location that cannot accommodate the request (see, e.g., HORWICH:Fig 6(615)).
Consider Claim 7,
The system of HORWICH and SHARIFIE, as combined, further teaches:
allocating, by the memory sub-system, a second portion of the volatile random access memory of the memory sub-system as a buffer memory that is separate from the memory device and the cache memory (HORWICH, e.g., Fig 1(127); ¶0074, Device Cache includes SRAM (i.e., a second portion of the volatile RAM), which is separate from the memory device (e.g., Fig 1(130,140)) and cache memory (e.g., Fig 1(130)); and
configuring, by the memory sub-system, the queue in the buffer memory (HORWICH, e.g., Fig 7(327A);¶0078, device memory (127) includes queues.).
Consider Claim 8,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the queue is configured in the cache memory (HORWICH, e.g., Fig 3A(328); ¶0096, local memory (130) includes CMB (420); Fig 5(420), includes CMB Space (430);Fig 4(430), includes queues. In other words, the queue is configured in the cache.).
Consider Claim 9,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the first portion of memory resources of the memory sub-system includes a third portion of the volatile random access memory; and the queue is configured in third portion of the volatile random access memory implementing a predetermined portion of the memory space (HORWICH, e.g., Fig 3A(328); ¶0096, local memory (130) includes CMB (420); Fig 5(420), includes CMB Space (430);Fig 4(430), includes queues. In other words, the queue is configured in a subset of the local memory (i.e., a third portion of volatile RAM).).
Consider Claim 10,
HORWICH teaches memory sub-system, comprising:
a host interface operable on a connection to a host system according to a storage access protocol and a cache-coherent memory access protocol (HORWICH, e.g., Fig 1(105);Fig 3A(305), CXL bus.);
a first memory configured to provide a non-volatile storage capacity of the memory sub-system, wherein at least a portion of the first memory is configured to implement a memory device attached via the connection to the host system (HORWICH, e.g., Fig 3A(130,140), NVM subsystem.);
a second memory faster than the first memory (HORWICH, e.g., Fig 3A(130), DRAM is faster than NVM.); and
a controller configured to:
retrieve, from a queue, a command configured to identify a memory address in the memory device (HORWICH, e.g., Fig 10A(1002), read command from submission queue.); and
execute the command to read data from the memory device at the memory address (HORWICH, e.g., Fig 10A(1010,1020,730), execute command.).
HORWICH describes both read and write commands (HORWICH, e.g., ¶0087), but fails to expressly describe system operation for write commands. SHARIFIE describes systems and methods for managing an external memory apparatus and is considered analogous prior art. SHARIFIE does describe both reading and writing data using a command queue (SHARIFIE, e.g., ¶0050-0052). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of HORWICH to use store commands along with read commands in a buffer as taught by SHARIFIE because it is ubiquitous in the art and offers the clear benefit of storing information into the memory for retrieval.
Consider Claim 11,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the controller is further configured to:
receive, over the connection from the host system using the cache-coherent memory access protocol, a request to store data at the memory address (HORWICH, e.g., Fig 11A(1102), receive request from host; Fig 3A(1112,1113), coherency elements.);
generate the command in response to a request (HORWICH, e.g., Fig 11A(1108), SDM generates request.); and
enter the command in the queue (HORWICH, e.g., ¶0017 describes placing commands in CMB submission queues.).
Consider Claim 12,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the controller is further configured to: identify a plurality of commands in the queue having addresses in a memory page in the memory device; consolidate data of the plurality of commands to generate a content of the memory page; and program a page of memory cells in the first memory to store the content for the plurality of commands (SHARIFIE, e.g., ¶0050-0051, describes searching for related address, combining the data, and writing to at least a single page.).
Consider Claim 13,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the connection is a compute express link (CXL) connection (HORWICH, e.g., Fig 3A(305), CXL bus.).
Consider Claim 14,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the queue is configured in the portion of the first memory configured to implement the memory device attached via the connection to the host system (HORWICH, e.g., Fig 7(328); ¶0078, the combination of NVM media controller, its associated NVM command queues and NVM is sometimes referred to herein as an NVM subsystem. In other words, the queues are configured in the memory space associated with the NVM subsystem.); and the controller is further configured to: receive, over the connection from the host system using the cache-coherent memory access protocol, the command in the queue (HORWICH, e.g., ¶0114, commands may be sent as an NVM submission; ¶0020, controller reads submissions in the submission queue. The command must be received in the queue for it to be read from the queue.).
Consider Claim 15,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the queue is configured in a memory of the host system (SHARIFIE, e.g., Fig 1, memory command queue may exist in a memory of the host system.); and the controller is configured to retrieve the command over the connection from the host system using the storage access protocol (SHARIFIE, ¶0044, memory device reads commands from host command queue.).
Consider Claim 16,
HORWICH teaches a non-transitory computer storage medium storing instructions which, when executed in a computing system, cause the computing system to perform a method, comprising:
establishing a connection between a host system and a memory sub-system, the connection operable according to a storage access protocol and a cache-coherent memory access protocol (HORWICH, e.g., Fig 1(105);Fig 3A(305), CXL bus.);
attaching a first memory of the memory sub-system over the connection to the host system as a memory device accessible via the cache-coherent memory access protocol (HORWICH, e.g., Fig 3A(130,140), memory;Fig 3A(300), coherent interconnect fabric.);
entering, in a storage access queue, a command configured to identify a memory address in the memory device (HORWICH, e.g., ¶0017 describes placing commands in CMB submission queues.); and
executing, by the memory sub-system, the command to read data from the memory device at the memory address (HORWICH, e.g., Fig 10A, read command from submission queue and execute command.).
HORWICH describes both read and write commands (HORWICH, e.g., ¶0087), but fails to expressly describe system operation for write commands. SHARIFIE describes systems and methods for managing an external memory apparatus and is considered analogous prior art. SHARIFIE does describe both reading and writing data using a command queue (SHARIFIE, e.g., ¶0050-0052). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the system of HORWICH to use store commands along with read commands in a buffer as taught by SHARIFIE because it is ubiquitous in the art and offers the clear benefit of storing information into the memory for retrieval.
Consider Claim 17,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the method further comprises:
receiving, in the memory sub-system over the connection from the host system using the cache-coherent memory access protocol, a request to store data at the memory address (HORWICH, e.g., Fig 11A(1102), receive request from host; Fig 3A(1112,1113), coherency elements.); and
generating, by the memory sub-system in response to the request, the command (HORWICH, e.g., Fig 11A(1108), SDM generates request.);
wherein the connection is a compute express link connection (HORWICH, e.g., Fig 3A(305), CXL bus.).
Consider Claim 18,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein the memory sub-system is configured to cache a page of the memory device (HORWICH, e.g., Fig 2(230_;¶0075, local memory acts as a cache for the NVM.); and
the command is configured to cause the memory sub-system to swap a content of the page from a cache memory to the first memory (HORWICH, e.g., ¶0075, data is moved between a local memory (cache) and NVM.).
Consider Claim 19,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein
the storage access queue is configured in a memory of the host system (SHARIFIE, e.g., Fig 1, memory command queue may exist in a memory of the host system.);
the host system is configured to enter the command into the storage access queue (SHARIFIE, e.g., ¶0036, store commands issued by the host.); and
the memory sub-system is configured to retrieve the command from the storage access queue over the connection according to the storage access protocol (SHARIFIE, ¶0044, memory device reads commands from host command queue.).
Consider Claim 20,
The system of HORWICH and SHARIFIE, as combined, further teaches wherein
the storage access queue is configured in a second memory of the memory sub-system (HORWICH, e.g., Fig 3A(328); ¶0096, local memory (130) includes CMB (420); Fig 5(420), includes CMB Space (430);Fig 4(430), includes queues. In other words, the queue is configured in a subset of the local memory (i.e., a third portion of volatile RAM).);
the host system is configured to enter the command into the storage access queue over the connection using the cache-coherent memory access protocol (HORWICH, e.g., ¶0097, submission for a payload by the host;Fig 3A, submission over a CXL bus (i.e., a cache-coherent memory access protocol).); and
the memory sub-system is configured to retrieve the command from the storage access queue without using the connection (HORWICH, e.g., ¶0083, receive commands from submission queues; Fig 3A, NVM controller (128) accesses the command queues (328) without using the CXL bus (305).).
Response to Arguments
Applicant's arguments filed 18MAR2026 have been fully considered but they are not persuasive.
The applicant argues that the 112 rejection is improper because a person of ordinary skill in the art would recognize commonly used terms such as random access memory. The examiner completely agrees that “random access memory” is a well-known term in the art. However, random access memory is not the phrase which is the subject of the instant 112 rejection. The rejected claim describes randomly storing data which is clearly different than the ability to randomly access a memory page without accessing preceding locations, which is the concept behind the term random access memory. There is a clear and unambiguous difference between providing random access and prescribing random storage. For at least these reasons the applicant’s arguments are not persuasive.
The applicant further argues that the cited art fails to teach the claimed invention because the submission queues are accessible by a host and that Horwich does not disclose a memory sub-system that generates and enters a command into a queue. However, HORWICH expressly describes sending a request for a page by writing a submission into the demand queue in response to a page fault (HORWICH, e.g., ¶0105; Fig 11b, shows host request for CL’z’ and, in response to a page fault, the SDM generates a request for NVM LBAs.). HORWICH additionally describes that NVM commands (i.e., requests for NVM LBAs) are stored into a command queue (HORWICH, e.g., ¶0016). Additionally, all the elements associated with queuing and data retrieval may be considered part of the same memory sub-system. The examiner additionally notes that the applicant appears to emphasize the idea that at least a subset of the queues in the cited art are accessible by the host, but the claimed invention expressly recites permitting host access to the memory subsystem and fails to include any language that restricts access to the claimed queue. For at least theses reasons the applicant’s arguments are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Gary W. Cygiel/Primary Examiner, Art Unit 2137
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