DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-12, and 14-30 are pending.
Claims 1, 3, 12, 14, 22-23, and 26-27 have been amended.
This action is Final.
Response to Arguments
Applicant's arguments filed 2/17/2026 have been fully considered but they are not persuasive. Regarding claims 1 and 12, Applicant appears to argue on page 15 that Iyer does not teach the amended limitation of “…without initiation of a second transition to a third link state having a higher operating power than the first link state and the second link state” because in the transition from L1 to L2 in Iyer, they must go through higher power state L0 first, and thus Iyer teaches away from the claimed invention. Applicant further argues Examiner’s motivation to combine on pages 15-16, and that combining Cooper with Iyer would not lead to faster transition times for entry into Cooper’s L1 state because Iyer requires a transition from L1 to L0 first before transitioning to L2. Regarding claims 22 and 26, Applicant appears to argue on pages 17-18 that they have been amended to include limitations similar to claim 1, and that Iyer teaches away from the amended limitation because of the transition to L0 as described above. Applicant argues that Berchanskiy does not cure the deficiencies of Iyer. Examiner respectfully disagrees.
Regarding Applicant’s first argument that Iyer does not teach the amended limitation because of the intermediate transition from L1 to L0 to L2, Examiner points out that the previous Office Action relied on Cooper to teach the limitation, and not Iyer. Cooper shows a direct transition from the idle (low power usage) state L0s to a deeper power saving state L1 [col. 3 lines 37-61 and FIG. 2A: (state transitions from L0 to L0s to L1; there is no transition to a higher power state because it transitions directly from L0s to L1)]. As shown, there is no need for Cooper to transition from L0s to L0 to L1. Iyer was merely provided to show a link for providing a sideband message to initiate the transition into the deeper power saving state. Iyer does not teach away from the claimed invention.
Regarding Applicant’s next argument about the motivation and that Iyer would not lead to faster transition times for entry into Cooper’s L1 state because Iyer requires a transition from L1 to L0 first before transitioning to L2, Examiner notes again that the direct transition from a power saving state L0s to a deeper power saving state L1 is already taught by Cooper. Iyer was provided to show that messages may be communicated over a sideband to initiate transition into the L1 state. Examiner indicated that if such a teaching was provided in Cooper, Cooper would be able to transition to the L1 state upon receipt of the message instead of needing to wait for a period of time first before the transition is performed. Performing the transition immediately in response to a received message would allow for a faster state transition than waiting for a period of time to pass first and then performing the transition, which would lead to higher power savings. Thus Cooper is combinable with Iyer for the reason described above.
Regarding Applicant’s arguments on claims 22 and 26 that Iyer does not teach the amended limitations and that Berchanskiy does not cure the deficiencies of Iyer, Examiner notes that Berchanskiy does teach the amended limitation. Berchanskiy was relied on to teach the concept of transitioning to a low power state L1 and then directly transitioning to even lower power states L2 or L3 without returning to L0 [FIG. 2a and 0043]. Berchanskiy thus addresses the deficiencies of Iyer.
For the reasons described above, the previously applied prior art still teach the amended claims.
Examiner also notes that several prior art references cited in the previous Office Action but not used also teaches the concept of transitioning from a low power state to an even lower power state without returning to an active L0 state.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 8-9, 12-13, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cooper et al. (hereinafter as Cooper) USPAT 7,984,314, and further in view of Iyer et al. (hereinafter as Iyer) PGPUB 2020/0244397.
As per claim 1, Cooper teach a method performed by a first component of an electronic device [col. 3 lines 4-9: (device 102 (peripheral (first component) of computer system (electronic device)) causes link 104 to change power states)], the method comprising:
entering, based on expiration of a preconfigured time period, a first link state with respect to a bus that couples the first component to a second component of the electronic device [FIG. 1A: (PCIe link 104 (bus) couples device 102 with I/O controller 106 (second component); FIG. 2 and col. 3 lines 42-48: (the link begins in active state L0, and upon expiring of a particular time period of 7 microseconds, the link will transition to a standby state L0s (entering a first link state)];
transitioning from the first link state to a second link state with respect to the bus, the second link state having lower operating power than the first link state [col. 3 lines 48-61: (in L0s (first state), if it is determined there is no transaction pending and another period of time has passed, the link transitions to a deeper low power state L1 (second state))].
wherein transitioning from the first link state to the second link state includes transitioning from the first link state to the second link state without transitioning to a third link state having a higher operating power than the first link state and the second link state [col. 2 lines 6-17: (L0 state is the active state, L0s is a state of idleness where some amount of power is saved by quiescing the link, and L1 is a state of deeper power savings which allows clock to powered off) and col. 3 lines 37-61 and FIG. 2A: (state transitions from L0 to L0s to L1; there is no transition to a higher power state because it transitions directly from L0s to L1)].
Cooper does not teach receiving one or more signals via a first interrupt line of the bus, via a second interrupt line of the bus, or a combination thereof; and transitioning from the first link state to a second link state with respect to the bus based on the one or more signals. Cooper shows the link between device 102 and I/O controller but does not describe the link details.
Iyer teaches a PCIe interconnect between components and the use of L0 and L1 states of the interconnect. Iyer is thus similar to Cooper because they both teach the transitioning of the link between different L0 or L1 states. Iyer further teaches receiving one or more signals via a first interrupt line of the bus, via a second interrupt line of the bus, or a combination thereof [0059, 0077, and 0082: (the link may have a sideband link (first interrupt line of the bus) that allows messages (one or more signals) to be received)]; and transitioning from the first link state to a second link state with respect to the bus based on the one or more signals [0082: (transition may be made from an active state to a lower power state; a sideband signal may be asserted to acknowledge ACK was received and that the device is ready for entry into L1 lower power state, and when the sideband handshakes are completed, links can transition to the L1 state to be put into the idle power mode)]. Iyer teaches the use of a sideband channel on the PCIe link between components, and providing signals on the sideband channel to change to a lower power state.
The combination of Cooper with Iyer leads to Cooper’s PCIe link including a sideband channel, that provides messages for transitioning into the L1 lower power state. Thus the combination of Cooper with Iyer leads to upon elapse of a time, transitioning from L0 to L0s state, and then upon a receipt of a sideband message, transitioning from L0s state into the L1 state.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Iyer’s teachings of a sideband channel providing messages for transitioning to the L1 low power state in Cooper. One of ordinary skill in the art would have been motivated to use a sideband to provide messages for transitioning to the L1 state in Cooper instead of waiting for the second longer period of time (30 microseconds) to transition to the L1 state because it allows for faster transition times for entry into L1 state, which would allow for higher power savings.
As per claim 8, Cooper and Iyer teach the method of claim 1, wherein transitioning from the first link state to the second link state includes: receiving, from the second component, one or more first training sets having a first sequence; and transmitting, to the second component, one or more second training sets having a second sequence in response to receipt of the one or more first training sets [Iyer 0079: (sets of patterns are transmitted and stored; comparison is performed with stored set of patterns)].
As per claim 9, Cooper and Iyer teach the method of claim 8, wherein: transitioning from the first link state to the second link state includes transitioning from the first link state to an intermediate link state in response to receipt of the one or more first training sets [Iyer FIG. 10 L1 to L0 to L2]; receiving the one or more first training sets includes receiving a plurality of consecutive first training sets; and transmitting the one or more second training sets includes transmitting a plurality of second training sets [Iyer 0079].
Claim 12 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim 19 is similar in scope to claims 8 and 9 as addressed above and is thus rejected under the same rationale.
Claim(s) 3, 10-11, 14, and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cooper et al. (hereinafter as Cooper) USPAT 7,984,314 in view of Iyer et al. (hereinafter as Iyer) PGPUB 2020/0244397, and further in view of Doddi et al. (hereinafter as Doddi) PGPUB 2024/0354279.
As per claim 3, Cooper and Iyer teach the method of claim 1.
Cooper and Iyer do not explicitly teach wherein receiving the one or more signals includes receiving two or more signals, including: receiving a first signal via the first interrupt line; and receiving a second signal via the second interrupt line. Cooper and Iyer teach the sideband providing messages, but they do not specify providing different signals on different interrupt lines of the sideband.
Doddi teaches link training and transitions of link from active L0 state to lower power L1 or L2 state. Doddi is thus similar to Cooper and Iyer. Doddi further teaches wherein receiving the one or more signals includes receiving two or more signals, including: receiving a first signal via the first interrupt line [0027, 0035, 0045, and FIG. 1: (SB data line)]; and receiving a second signal via the second interrupt line [0027, 0035, 0045, and FIG. 1: (SB clock line)]. Doddi describes a sideband channel with different lines for receiving data and clock signals.
The combination of Cooper and Iyer with Doddi leads to the messages being provided in the sideband as having a data signal and a clock signal, for changing operation of the main band/bus.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Doddi’s teachings of the sideband including two lines for receiving two signals in Cooper and Iyer. One of ordinary skill in the art would have been motivated to have Cooper and Iyer’s sideband include a data and clock line because it allows the sideband to communicate data for changing operation of the link in a synchronous manner, thus ensuring accuracy.
As per claim 10, Cooper, Iyer, and Doddi teach the method of claim 3, wherein: the first signal comprises a data signal, the second signal comprises a clock signal, the method further comprises: processing the data signal based on the clock signal [FIG. 4: (sideband data line and sideband clock line provides clock and data signals to receiver to be processed together)].
As per claim 11, Cooper, Iyer, and Doddi teach the method of claim 10, wherein transitioning from the first link state to the second link state is based on the data signal indicating an acknowledgement from the second component [Iyer FIG. 11], the method further comprising, prior to receiving the first signal and the second signal: transmitting a third signal via the first interrupt line, wherein the third signal comprises a second data signal that indicates a request to transition to the second link state by the first component [Iyer FIG. 11 and Doddi FIG. 1-5 and 0045]; and transmitting a fourth signal via the second interrupt line, wherein the fourth signal comprises a second clock signal associated with the second data signal [Iyer FIG. 11 and Doddi FIG. 1-5 and 0045: (Iyer describes back and forth negotiation technique between the devices using requests and acknowledgements on the side channel; Doddi shows that the side channel has two lanes, one for data and one for clock, and may be bidirectional].
Claim 14 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Claim 20 is similar in scope to claim 10 as addressed above and is thus rejected under the same rationale.
Claim 21 is similar in scope to claim 11 as addressed above and is thus rejected under the same rationale.
Claim(s) 4-5 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cooper et al. (hereinafter as Cooper) USPAT 7,984,314 in view of Iyer et al. (hereinafter as Iyer) PGPUB 2020/0244397 and Doddi et al. (hereinafter as Doddi) PGPUB 2024/0354279, and further in view of Li et al. (hereinafter as Li) PGPUB 2020/0278733.
As per claim 4, Cooper, Iyer, and Doddi teach the method of claim 3.
Cooper, Iyer, and Doddi do not teach further comprising: decoding the first signal and the second signal to generate a plurality of sideband interrupt signals, the plurality of sideband interrupt signals including a first sideband interrupt signal, a second sideband interrupt signal, a third sideband interrupt signal, and a fourth sideband interrupt signal.
Li teaches link training and switching the link between different states based on data provided from sideband channels. Li is thus similar to Cooper, Iyer, and Doddi. Li further teaches decoding the first signal and the second signal to generate a plurality of sideband interrupt signals, the plurality of sideband interrupt signals including a first sideband interrupt signal, a second sideband interrupt signal, a third sideband interrupt signal, and a fourth sideband interrupt signal [FIG. 5 and 0052: (four auxiliary pins connect to the sideband to provide hints, and include pins such as reference clock (e.g., REFCLK−/REFCLK+) pins, add-in card presence detect pins (e.g., PRSNT1# and PRSNT2#), a reset (e.g., PERST#) pin, a clock required (e.g., CLKREQ#) pin (e.g., to implement clock power management), Joint Test Action Group (JTAG) testing pin(s), a wake (e.g., WAKE#) pin (e.g., to support wakeup and/or the Optimized Buffer Flush/Fill (OBFF) mechanism), a Power Brake (PWRBRK#) pin); thus, the hint provided these four pins are decoded and form four sideband interrupt signals (one for each pin))].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Li’s teachings of decoding four pins of the sideband to generate four interrupt signals for a hint in Cooper, Iyer, and Doddi. One of ordinary skill in the art would have been motivated to use the four pins to generate four interrupts in Cooper, Iyer, and Doddi because it allows hints to be provided over existing pin connections and thereby bypass the dependency upon PCIe stack readiness to convey system hints between devices, including during low power substates. Such implementation may provide a new option to have better trade-off between system power efficiency and performance during state transitions [Li 0048].
As per claim 5, Cooper, Iyer, Doddi, and Li teach the method of claim 4, wherein the first sideband interrupt signal indicates whether the first component is to transition to a next low power link state associated with a current link state indicated by a link state array [Cooper FIG. 2 and Li FIG. 6A and 0049: (purpose of the pins is to provide hints for state transitions to the next state; thus the first signal of the sideband indicates the transition)].
Claim 15 is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Claim 16 is similar in scope to claim 5 as addressed above and is thus rejected under the same rationale.
Claim(s) 22-23 and 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer et al. (hereinafter as Iyer) PGPUB 2020/0244397, and further in view of Berchanskiy et al. (hereinafter as Berchanskiy) PGPUB 2019/0155361.
As per claim 22, Iyer teaches a method performed by a first component of an electronic device [FIG. 11: (second device 1110 (first component)], the method comprising:
receiving a first set of one or more signals via a first interrupt line of a bus, via a second interrupt line of the bus, or a combination thereof [0082 and FIG. 11: (first device 1105 can assert a sideband signal 1115 to second device 1110; thus second device 1110 receives an interrupt)]; and
transmitting a second set of one or more signals via the first interrupt line of the bus, via the second interrupt line of the bus, or a combination thereof in response to receipt of the first set of one or more signals [0082 and FIG. 11: (additionally, second device 1110 can also assert a sideband signal to first device in response to the sideband signal 1115; thus a signal is provided from one device to another, and the other provides a response)], wherein:
transmission of the second set of one or more signals initiates, in a second component, a transition from a first link state to a second link state with respect to the bus, the second link state having lower operating power than the first link state [0064 and 0082 and FIG. 11: (upon sideband handshake completing, the link transitions from L0 to the lower power L1 state)].
Iyer does not teach the first set of one or more signals are received and the second set of one or more signals are transmitted while data lanes of the bus are in an inactive state; wherein transitioning from the first link state to the second link state includes transitioning from the first link state to the second link state without transitioning to a third link state having a higher operating power than the first link state and the second link state. Iyer teaches transition from the L0 state to the lower power/inactive L1 state using sideband communications, but Iyer does not indicate that the L0 state is an inactive state.
Berchanskiy teaches the transition of a link from the active L0 state into a L1 state. Berchanskiy is thus similar to Iyer because they teach transition into a low power state L1 state from the L0 state. Berchanskiy further teaches wherein transitioning from the first link state to the second link state includes transitioning from the first link state to the second link state without transitioning to a third link state having a higher operating power than the first link state and the second link state [FIG. 2a and 0043: direct transition into even lower power states L2 or L3 from the inactive L1 state].
The combination of Iyer and Berchanskiy allows similar sideband negotiations to occur when transitioning from the L1 inactive state to the L2 state that has even lower power usage. Berchanskiy teaches that even lower power state transitions may occur from the L1 state, and such entry may be accomplished using the sideband negotiation technique disclosed in Iyer. The combination would therefore teach the first set of one or more signals are received and the second set of one or more signals are transmitted while data lanes of the bus are in an inactive state (e.g. sideband negotiation occurs from L1 into L2 state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Berchanskiy’s teachings of entry into lower power L2, L3 states from an inactive low power L1 state in Iyer. One of ordinary skill in the art would have been motivated to provide direct entry into lower power L2 state from the L1 inactive state in Iyer because it would allow for a faster transition and additional power savings. One of ordinary skill in the art would have been motivated to use Iyer’s sideband negotiation technique in the state transition from L1 to L2 because it is an established technique used in Iyer for state transitions.
As per claim 23, Iyer and Berchanskiy teach the method of claim 22, wherein receiving the first set of one or more signals includes receiving two or more signals, including: receiving a first signal via the first interrupt line [Iyer FIG. 11 and 0080: (A-sideband asserted; sideband may have multiple lanes)]; and receiving a second signal via the second interrupt line [Iyer 0080 and FIG. 11: (B-sideband asserted)].
Claim 26 is similar in scope to claim 22 as addressed above and is thus rejected under the same rationale.
Claim 27 is similar in scope to claim 23 as addressed above and is thus rejected under the same rationale.
Claim(s) 24 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer et al. (hereinafter as Iyer) PGPUB 2020/0244397 in view of Berchanskiy et al. (hereinafter as Berchanskiy) PGPUB 2019/0155361, and further in view of Li et al. (hereinafter as Li) PGPUB 2020/0278733.
As per claim 24, Iyer and Berchanskiy teach the method of claim 23.
Iyer and Berchanskiy do not teach further comprising: decoding the first signal and the second signal to generate a first sideband interrupt signal, wherein the first sideband interrupt signal has a first value; and in response to the first sideband interrupt signal having the first value, transmitting, to the second component, a third signal via the first interrupt line and a fourth signal via the second interrupt line.
Li teaches link training and switching the link between different states based on data provided from sideband channels. Li is thus similar to Iyer and Berchanskiy. Li further teaches decoding the first signal and the second signal to generate a first sideband interrupt signal, wherein the first sideband interrupt signal has a first value; and in response to the first sideband interrupt signal having the first value, transmitting, to the second component, a third signal via the first interrupt line and a fourth signal via the second interrupt line [FIG. 5 and 0052: (four auxiliary pins connect to the sideband to provide hints, and include pins such as reference clock (e.g., REFCLK−/REFCLK+) pins, add-in card presence detect pins (e.g., PRSNT1# and PRSNT2#), a reset (e.g., PERST#) pin, a clock required (e.g., CLKREQ#) pin (e.g., to implement clock power management), Joint Test Action Group (JTAG) testing pin(s), a wake (e.g., WAKE#) pin (e.g., to support wakeup and/or the Optimized Buffer Flush/Fill (OBFF) mechanism), a Power Brake (PWRBRK#) pin); thus, the hint provided these four pins are decoded and form four sideband interrupt signals (one for each pin))].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Li’s teachings of decoding four pins of the sideband to generate four interrupt signals for a hint in Iyer and Berchanskiy. One of ordinary skill in the art would have been motivated to use the four pins to generate four interrupts in Iyer and Berchanskiy because it allows hints to be provided over existing pin connections and thereby bypass the dependency upon PCIe stack readiness to convey system hints between devices, including during low power substates. Such implementation may provide a new option to have better trade-off between system power efficiency and performance during state transitions [Li 0048].
Claim 28 is similar in scope to claim 24 as addressed above and is thus rejected under the same rationale.
Claim(s) 25 and 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iyer et al. (hereinafter as Iyer) PGPUB 2020/0244397 in view of Berchanskiy et al. (hereinafter as Berchanskiy) PGPUB 2019/0155361, and further in view of Doddi et al. (hereinafter as Doddi) PGPUB 2024/0354279.
As per claim 25, Iyer and Berchanskiy teach the method of claim 22, wherein: the first set of one or more signals comprise a first modulated data signal, the first modulated data signal indicating a request, by the second component, to enter into the second link state [Iyer FIG. 11: (request is provided for entry into L1 state from one device to another; request is a modulated data signal)]; the second modulated data signal to induce, in the second component, a transition from the first link state to the second link state [Iyer FIG. 11: (transition from L0 to L1 occurs after communication between the devices)].
Iyer and Berchanskiy do not teach the second set of one or more signals comprise a second modulated data signal and a clock signal. Iyer and Berchanskiy shows communication between the devices over sideband channel, but does not teach providing a clock on the sideband channel.
Doddi teaches link training and transitions of link from active L0 state to lower power L1 or L2 state. Doddi is thus similar to Iyer and Berchanskiy. Doddi further teaches wherein receiving the one or more signals includes: the second set of one or more signals comprise a second modulated data signal and a clock signal [0027, 0035, 0045, and FIG. 1: (SB data line and SB clock line)]. Doddi describes a sideband channel with different lines for receiving data and clock signals.
The combination of Iyer and Berchanskiy with Doddi leads to the messages being provided in the sideband as having a data signal and a clock signal, for changing operation of the main band/bus.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Doddi’s teachings of the sideband including two lines for receiving two signals in Iyer and Berchanskiy. One of ordinary skill in the art would have been motivated to have Iyer and Berchanskiy’s sideband include a data and clock line because it allows the sideband to communicate data for changing operation of the link in a synchronous manner, thus ensuring accuracy.
Claim 29 is similar in scope to claim 25 as addressed above and is thus rejected under the same rationale.
Claim 30 is similar in scope to claim 25 as addressed above and is thus rejected under the same rationale.
Allowable Subject Matter
Claims 6-7 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 5712703779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
Prosecution Insights