DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Remarks/Arguments filed on January 22nd, 2026, have been carefully considered.
No claims have been added, canceled, or amended.
Claims 1-10 and 17-26 are currently pending in the instant application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 and 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Horwich et al. [US2021/0374080] in view of GIM et al. [US2023/0062610]. Horwich teaches computer memory expansion device and method of operation. GIM teaches dual mode storage device.
Regarding claims 1 and 21, Horwich teaches a method, comprising:
providing, by a memory sub-system to a host system [Horwich paragraph 0073, first lines “…the CMX device 100 includes a coherent memory expansion controller (CMXC) 120 (which includes cache memory or device cache 127), and may further include or has access to local memory 130 (e.g., DDR DRAM), and/or non-volatile memory (NVM) 140 (e.g., NAND Flash memory)…”], memory services in a memory space addressable using memory addresses over a connection [Horwich paragraph 0007, first lines “…the memory expansion device is coupled to the host via a Computer Express Link (CXL) bus…”], from a host interface of the memory sub-system to the host system, in a first protocol of cache-coherent memory access [Horwich paragraph 0007, last lines “…the interface circuitry provides a CXL interface between the control logic and the CXL bus, and wherein the first coherent destination memory space is accessible by the host using a CXL protocol…”];
providing, by the memory sub-system to the host system [Horwich abstract, first lines “…A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic...”], storage services in a storage space addressable using logical block addresses over the connection in a second protocol of storage access [Horwich paragraph 0006, middle lines “…The control logic is configurable to receive a first submission from the host, the first submission including a first read command and specifying a first payload in the NVM subsystem…” and paragraph 0087, last lines “…the payload 630 corresponds to a plurality of logical blocks at corresponding logical block addresses…” and paragraph 0076, middle lines “…CXL bus 305 is a high-speed CPU-to-device and CPU-to-memory interconnect or link based on the CXL protocol, including sub-protocols CXL…”];
managing, by the memory sub-system, a file system configured within the memory sub- system [Horwich paragraph 0082, last lines “…CMX device 100 also provides additional coherency mechanisms and allows the SDM software to include additional extensions (or hints) in host NVMe submissions. In some embodiments, the SDM software 201 initiates data transfers into and out of the NVM 140 by writing submissions into one or more submission queues in a controller memory buffer (CMB) on the CMX device 100…”(Where the software-defined memory reads on the file system.)];
Horwich fails to explicitly teach providing, by the memory sub-system via the memory space, an application programming interface for the host system to access the file system;
However, GIM does teach providing, by the memory sub-system via the memory space [GIM paragraph 0027, first lines “…a machine including a storage device that may be used to extend the memory…”], an application programming interface for the host system to access the file system [GIM paragraph 0060, most lines “…an Application Programming Interface (API) to make system calls to change the mode to be used. For example, application 405 may use an API to change an attribute of file 485 to change the mode between block mode 330 and DAX mode 305. APIs may also be used for other purposes…”];
Horwich and GIM are analogous arts in that they both deal with using CXL protocols to enhance memory performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine Horwich’s CXL teachings with GIM’s use of an API for the benefit of increasing the amount of memory in a machine by a considerable amount for less cost than actual memory [GIM paragraph 0024, first lines “…Using a storage device, such as a Solid State Drive (SSD), to expand memory in the machine may increase storage by a considerable amount for less than the cost of a comparable amount of memory…”].
receiving, in the memory sub-system over the connection using the first protocol of cache-coherent memory access [Horwich paragraph 0049, first lines “…the CXL memory expansion device uses CXL coherency protocols to implement coherent hybrid data transfers, and supports direct cache-to-cache transfers between a host cache and the device cache…”], a request according to the application programming interface [GIM paragraph 0060, all lines “…an Application Programming Interface (API) to make system calls to change the mode to be used. For example, application 405 may use an API to change an attribute of file 485 to change the mode between block mode 330 and DAX mode 305. APIs may also be used for other purposes…”], the request having an identifier of a file in the file system [GIM paragraph 0051, first lines “…in identifying a particular data being requested from storage device 120, application 405 may use a logical identifier, such as an LBA. This LBA may be an identifier within LBA space 450…”]; and
generating, by the memory sub-system responsive to the request [GIM paragraph 0051, first lines “…These applications may issue requests (which may also be termed commands) to read data from or write data to either memory 115…”], a response according to the application programming interface [GIM paragraph 0060, all lines “…an Application Programming Interface (API) to make system calls to change the mode to be used. For example, application 405 may use an API to change an attribute of file 485 to change the mode between block mode 330 and DAX mode 305. APIs may also be used for other purposes…”], the response containing data for the file in the file system [GIM paragraph 0052, first lines “…application may issue load/store command 455 to read/write data from memory 115 of FIG. 1, which may be extended by storage device 120. Load/store command 455 may be delivered to operating system 410, which may also offer direct access for files (DAX) mode 305. Application 405 may use mmap( ) to perform memory mapping, which may enable byte-addressable access to the data in the extended memory system…”].
Regarding claim 2 and 22, as per claim 1, Horwich teaches the connection is according to a standard of compute express link (CXL) [Horwich paragraph 0007, last lines “…the interface circuitry provides a CXL interface between the control logic and the CXL bus, and wherein the first coherent destination memory space is accessible by the host using a CXL protocol…”].
Regarding claims 3 and 22, as per claim 1, Horwich teaches the request is stored by the host system into the memory space over the connection using the first protocol of cache-coherent memory access [Horwich paragraph 0049, first lines “…the CXL memory expansion device uses CXL coherency protocols to implement coherent hybrid data transfers, and supports direct cache-to-cache transfers between a host cache and the device cache…”]; and
the response is provided in the memory space for loading by the host system over the connection using the first protocol of cache-coherent memory access [GIM paragraph 0052, first lines “…application may issue load/store command 455 to read/write data from memory 115 of FIG. 1, which may be extended by storage device 120. Load/store command 455 may be delivered to operating system 410, which may also offer direct access for files (DAX) mode 305. Application 405 may use mmap( ) to perform memory mapping, which may enable byte-addressable access to the data in the extended memory system…”].
Regarding claims 4 and 23, as per claim 1, Horwich teaches configuring one or more message queues in the memory space, wherein the request is entered by the host system into the one or more message queues, and the response is entered by the memory sub-system into the one or more message queues [Horwich paragraph 0082, last lines “…the SDM software 201 initiates data transfers into and out of the NVM 140 by writing submissions into one or more submission queues in a controller memory buffer (CMB) on the CMX device 100, the CMX device 100 indicates completion of the submissions by writing completions into one or more completion queues in the CMB…”].
Regarding claim 5, as per claim 1, GIM teaches the data includes a content of the file in the file system [GIM paragraph 0049, last lines “…Operating system may enable access to a file such as file 420, store data from file 420 in page cache 425, manage the blocks of data in file 420 (which may be identified using logical block addresses (LBAs) or other logical identifiers) using block management 430…”].
Regarding claims 6 and 24, as per claim 1, GIM teaches the data includes one or more memory addresses configured to identify one or more memory regions assigned from the memory space to the file to host a content of the file [GIM paragraph 0049, last lines “…Operating system may enable access to a file such as file 420, store data from file 420 in page cache 425, manage the blocks of data in file 420 (which may be identified using logical block addresses (LBAs) or other logical identifiers) using block management 430…”].
Regarding claims 7 and 24, as per claim 1, Horwich teaches receiving, in the memory sub-system over the connection using the first protocol of cache-coherent memory access from the host system [Horwich paragraph 0049, first lines “…the CXL memory expansion device uses CXL coherency protocols to implement coherent hybrid data transfers, and supports direct cache-to-cache transfers between a host cache and the device cache…”], a memory access request having a memory address identified via the response [Horwich paragraph 0011, most lines “…the control logic is further configured to, after indicating completion of the first submission and in response to a memory read request from the host to read demand data in the payload, determine whether the demand data has been loaded in the cache memory, and in response to the demand data having been loaded in the cache memory…”]; and
GIM teaches processing, by the memory sub-system, the memory access request to store or load a portion of the content of the file into or from the memory space [GIM paragraph 0052, first lines “…application may issue load/store command 455 to read/write data from memory 115 of FIG. 1, which may be extended by storage device 120. Load/store command 455 may be delivered to operating system 410, which may also offer direct access for files (DAX) mode 305. Application 405 may use mmap( ) to perform memory mapping, which may enable byte-addressable access to the data in the extended memory system…”] .
Regarding claims 8 and 25, as per claim 1, GIM teaches the data includes one or more logical block addresses configured to identify one or more logical blocks assigned from the storage space to the file to host a content of the file [GIM paragraph 0049, last lines “…Operating system may enable access to a file such as file 420, store data from file 420 in page cache 425, manage the blocks of data in file 420 (which may be identified using logical block addresses (LBAs) or other logical identifiers) using block management 430…”].
Regarding claims 9 and 25, as per claim 1, Horwich teaches retrieving, by the memory sub-system over the connection using the second protocol of storage access [Horwich paragraph 0076, middle lines “…CXL.io is backward compatible with Peripheral Component Interconnect Express (PCIe) Interface Standard Gen 5…”], a storage access command from a storage access queue configured in a memory of the host system [Horwich paragraph 0009, middle lines “…The control logic is configured to, before loading the first payload into the cache memory issue first NVM read commands to read the first payload from the NVM subsystem, the first NVM read commands being written into a command queue associated with the NVM subsystem…”], the storage access command having a logical block address identified via the response [Horwich paragraph 0087, last lines “…the payload 630 corresponds to a plurality of logical blocks at corresponding logical block addresses (LBA-1, LBA-2, . . . , LBA-n) in the NVM 130 and can be specified by an LBA of a starting logical block (e.g., LBA-1) and a number of logical blocks n starting at the starting logical block…”]; and
processing, by the memory sub-system, the storage access command to read or write a portion of the content of the file into or from the storage space [Horwich paragraph 0089, last lines “…control logic control logic 125 is configured to process a submission from the host 110 with a certain priority based on whether the submission is for demand read, predictive read, or speculative read…”].
Regarding claims 10 and 26, as per claim 1, GIM teaches the data is configured to identify an address in the memory space storing a meta data of the file in the file system [GIM paragraph 0092, first line “…The file system may maintain metadata and should track the changes on the file…” and paragraph 0058, middle lines “…a file in operating system 410, such as file 485, may include a value and/or an attribute (such as a property associated with the file handled as metadata by operating system 410) that specifies whether store command 455 should be handled using block mode 330 or DAX mode 305…”].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Horwich et al. [US2021/0374080] in view of Merwaday et al. [US2022/0038554]. Horwich teaches computer memory expansion device and method of operation. Merwaday teaches edge computing local breakout.
Regarding claim 20, as per claim 17, Horwich fails to explicitly teach the messaging channel is in accordance with a hypertext transfer protocol (HTTP) representational state transfer (REST) application programming interface (API).
However, Merwaday does teach the messaging channel is in accordance with a hypertext transfer protocol (HTTP) representational state transfer (REST) application programming interface (API) [Merwaday paragraph 0069, middle lines “…Each microservice 211a, 211b could be composed of several services and/or processes such as, for example, multiple web API services or any other kind of services using HTTP and/or any other protocol…” and paragraph 0209, last lines “…The FAI API supports both queries and subscriptions (pub/sub mechanism) that are used over the RESTful API or over alternative transports such as a message bus…”].
Horwich and Merwaday are analogous arts in that they both deal with using CXL protocols to enhance memory performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine Horwich’s messaging teachings with Merwaday’s use of an HTTP encapsulated REST API for the benefit of improving cost of ownership and reducing application and network latency [Merwaday paragraph 0143, middle lines “…Edge computing, at a general level, refers to the implementation, coordination, and use of computing and resources at locations closer to the “edge” or collection of “edges” of the network. The purpose of this arrangement is to improve total cost of ownership, reduce application and network latency, reduce network backhaul traffic and associated energy consumption, improve service capabilities, and improve compliance with security or data privacy requirements (especially as compared to conventional cloud computing)…”].
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horwich et al. [US2021/0374080]. Horwich teaches computer memory expansion device and method of operation.
Regarding claim 17, Horwich teaches a non-transitory computer storage medium storing instructions which, when executed in a computing system [Horwich paragraph 0006, first lines “…a memory expansion device is operable in a computer system, the computer system including a host computer (host) and a dedicated bus…”], cause the computing system to perform a method, comprising:
establishing a connection between a host system and a memory sub-system [Horwich paragraph 0007, first lines “…the memory expansion device is coupled to the host via a Computer Express Link (CXL) bus…”], the connection operable according to a storage access protocol and a cache-coherent memory access protocol [Horwich paragraph 0007, last lines “…the interface circuitry provides a CXL interface between the control logic and the CXL bus, and wherein the first coherent destination memory space is accessible by the host using a CXL protocol…”];
attaching a portion of memory resources of the memory sub-system over the connection to the host system as a memory device accessible to the host system over the connection via the cache-coherent memory access protocol [Horwich paragraph 0030, most lines “…The memory expansion device comprises interface circuitry configured to communicate with the host via the dedicated bus based on a predefined protocol, a non-volatile memory (NVM) subsystem, local memory providing a coherent memory space accessible by the host, cache memory, and control logic coupled to the interface circuitry the cache memory, and the NVM subsystem…”];
running a file system manager in the memory sub-system to operate a file system hosted in the memory sub-system [Horwich paragraph 0082, last lines “…CMX device 100 also provides additional coherency mechanisms and allows the SDM software to include additional extensions (or hints) in host NVMe submissions. In some embodiments, the SDM software 201 initiates data transfers into and out of the NVM 140 by writing submissions into one or more submission queues in a controller memory buffer (CMB) on the CMX device 100…”(Where the software-defined memory reads on the file system.)]; and
communicating, via the memory device, between the memory sub-system and the host system to provide the host system with access to files in the file system [Horwich paragraph 0089, most lines “…in addition to demand read (e.g., an operation to resolve page fault at the host), CMX device 100 also facilitates predictive read (e.g., an operation to load a payload in a coherent memory space 410 or 420 based on prediction that the payload may be needed in a predictive time frame) and speculative read (e.g., an operation to load a payload in the private memory space 450 based on speculation that the payload may be needed in a speculative time frame…”].
Regarding claims 18, as per claim 17, Horwich teaches the method further comprises:
attaching the portion of the memory resources of the memory sub-system over the connection to the host system as a storage device accessible to the host system over the connection via the storage access protocol [Horwich paragraph 0049, first lines “…the CXL memory expansion device uses CXL coherency protocols to implement coherent hybrid data transfers, and supports direct cache-to-cache transfers between a host cache and the device cache…”];
wherein the files are accessible both in the memory device and the storage device [Horwich paragraph 0022, all lines “…the memory expansion device further comprises local memory coupled to the control logic, wherein one or both of the first coherent destination memory space and the second coherent destination memory space is provided by the device memory…”].
Regarding claim 19, as per claim 17, Horwich teaches the method further comprises:
operating, via the memory device, a messaging channel between an operating system running in the host system and the file system manager running in the memory sub-system [Horwich paragraph 0007, all lines “…the memory expansion device is coupled to the host via a Computer Express Link (CXL) bus, wherein the interface circuitry provides a CXL interface between the control logic and the CXL bus, and wherein the first coherent destination memory space is accessible by the host using a CXL protocol…”(Where the CXL protocols are CXL.mem, CXL.cache, and CXL.io)];
wherein the communicating is through the messaging channel [Horwich paragraph 0076, middle lines “…CXL.io is backward compatible with Peripheral Component Interconnect Express (PCIe) Interface Standard Gen 5…”(Where the .io is a storage messaging channel.)].
Response to Arguments
Applicant's arguments filed January 22nd, 2026, have been fully considered but they are not persuasive.
The applicant argues that the SDM of the prior art is located external to the actual memory. The examiner would like to point out that the current claim language does not limit the “file system” to being in the memory. The claims currently only state “within the memory sub-system” or “in the memory sub-system”. The claims fail to define the limitations on or provide a definition of what the sub-system is or contains. The examiner has given the term its broadest reasonable interpretation and determined the Merriam-Webster dictionary definition of the prefix “sub” can mean “subordinate : secondary : next lower than or inferior to” as well as “subordinate portion of : subdivision of”. The examiner has determined then that the file system can be located in any subdivision of the memory system. Thus, the examiner has drawn the box around the whole of figure 8A as the “sub-system” as the CPU and the SDM are subdivisions of the actual memory 140 and are needed for the memory system to function. Therefore, since the claim language is subjective and lacks definitive location limitations. The examiner maintains that the current prior art reads on the claims as currently presented.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
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