DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to amendments filed 26 January 2025.
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11 – 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gim (US 20230062610).
Regarding claim 11, Gim teaches
A memory sub-system (memory sub-system = Fig. 4 storage device 120), comprising:
a host interface (host interface = Fig. 4 interface 440-1 + interface 440-2) operable on a connection (connection = Fig. 4 first connection between interface 440-1 and transmitter + second connection between interface 440-2 and said transmitter) to a host system (host system = machine 105) according to a storage access protocol and a cache-coherent memory access protocol; (Gim teaches storage device 120 with i) interface 440-1 that receives, from transmitter in operating system (in machine 105 (see ¶[48])), commands that uses PCIe protocol (storage access protocol) where there is a first connection (connection) between said interface 440-1 and said transmitter (see Fig. 5, ¶[49-50]) and ii) interface 440-2 that receives, from said transmitter, commands that uses CXL.mem (cache-coherent memory access protocol) where there is a second connection (connection) between said interface 440-2 and said transmitter (see Fig. 5, ¶[52-53]). Gim teaches CXL is cache-coherent interconnect protocol (see ¶[30]).)
a first memory configured to provide a non-volatile storage capacity of the memory sub-system, wherein at least a portion of the first memory is configured to implement a memory device attached via the connection to the host system; (Gim teaches storage device 120 (which is SSD (non-volatile) (see ¶[32])) includes storage 320 (first memory) where a portion is used as HDM 310 (memory device) (see ¶[39-40]) that is thought as another memory module (see ¶[34]). Note that said HDM 310 is within said storage device (see Fig. 3) that has interface 440-2 which is connected via second connection (connection) to transmitter (see Fig. 4).)
a second memory faster than the first memory; and (Gim teaches i) storage 320 (first memory) in storage device 120 (see Fig. 3, ¶[39-40]) that is SSD (see ¶[32]) and ii) buffer 325 that is DRAM (see Fig. 3, ¶[43]) where DRAM is faster than SSD (see ¶[24]).)
a controller configured to manage storage locations of files of a file system mounted on the memory sub-system, and allocate memory resources for a file stored in the memory sub-system (Gim teaches storage device 120 (memory sub-system) comprising SSD controller 510 (controller) that includes (mounted on) flash translation layer (FTL) (file system) maps (manage) LBAs to PBAs where data is stored (stored) in flash chips of said storage device 120 (memory sub-system) (see Fig. 5, ¶[51], [73]) wherein i) said data is from file 420 (files, file) (see ¶[49], [51]), and ii) said data is stored in blocks (memory resources) (in said storage device 120) (see ¶[42]) that are freed up so that said blocks can be (allocate) written to again (see ¶[70]). )
Regarding claim 12, Gim teaches the memory sub-system of claim 11 where Gim also teaches
allocate the memory resources for the file stored in the memory sub-system in response to a request from a file system manager in the host system (Gim teaches data, from file 420 (file), is stored (stored) in storage device 120 (memory sub-system) (see ¶[49], [51], ¶[73]) wherein said data is stored in blocks (memory resources) (in said storage device 120) (see ¶[42]) that are freed up (allocate) so that said blocks can be written again (see ¶[70]). Gim also teaches said data is stored in said storage device 120 in response to write command (request) received (see ¶[81]) from operating system (file system manager) in machine 105 (host system) (see ¶[48-49]). Gim also teaches SSD controller 510 managing data of said storage device 120 (see ¶[114]).)
Regarding claim 13, Gim teaches the memory sub-system of claim 12 where Gim also teaches
wherein the controller is further configured to manage a medium map configured to identify, for the file, first addresses that are usable by the host system to address the memory resources over the connection (Gim teaches SSD controller (controller) includes (configured to) flash translation layer that handle (manage) translation of LBAs (first addresses) to (to address) PBAs where data is stored in flash chips of storage device 120 (see Fig. 5, ¶[73]) wherein i) said data is stored in blocks (memory resources) in storage device 120 (see ¶[42]) and ii) operating system (in machine 102 (host system)) uses (useable) said LBAs (first addresses) to identify (identify) said data that is from file 420 (file) (see ¶[48-49]).)
Regarding claim 14, Gim teaches the memory sub-system of claim 13 where Gim also teaches
wherein the first addresses include [i) memory addresses usable over the connection according to the cache-coherent memory access protocol, or] ii) logical block addresses usable over the connection according to the storage access protocol (Gim teaches sending, from transmitter to interface 440-1 where there is a connection (connection) between (over) said transmitter and said interface 440-1, write command of data that is identified using LBAs (first addresses include logical block addresses) wherein said write command uses PCIe protocol (storage access protocol) (see ¶[49-50]). Gim also teaches said LBAs (logical block addresses) are translated (useable) to PBAs where said data is stored (see ¶[73]).)
Regarding claim 15, Gim teaches the memory sub-system of claim 14 where Gim also teaches
wherein the file system is mounted at least in part in a memory device (Gim teaches storage device 120 (memory sub-system, storage device) comprises SSD controllers that include (mounted) FTL (file system) (see ¶[73]).)
Regarding claim 16, Gim teaches the memory sub-system of claim 15 where Gim also teaches
wherein the first memory is also configured to implement a storage device attached via the connection to the host system; (Gim teaches mapping application LBA to PBA where data is stored (storage device) in storage space 320 (first memory) (see ¶[51]). Gim also teaches said storage space 320 is connected to LBA space 450 which is connected to PCIe 445 which is connected to interface 440-1 which is connected, via said first connection (connection), to transmitter in operating system (see Fig. 4) that is in machine 105 (host system) (see ¶[48]).)
the memory device is accessible to the host system over the connection using the cache-coherent memory access protocol; (Gim teaches operating system (in machine 105 (host system) (see ¶48])) sending (accessible) load/store command 445 via transmitter 435 to interface 440-2 (where there is a second connection (connection) between said transmitted 435 and said interface 440-2) in storage device 120 (memory device) that maps physical address to storage space 320 (see Fig. 4, ¶[52-53]). Gim also teaches said load/store command is expected to use CXL.mem (cache-coherent memory access protocol) (see ¶[53]).)
the storage device is accessible to the host system over the connection using the storage access protocol; and (Gim teaches operating system (in machine 105 (host system) (see ¶[48])) sending write command from transmitter 435 to interface 440-1 (where there is a first connection (connection) between said transmitter 435 and said interface 440-1) wherein said write command is expected to use PCIe protocol (storage access protocol) (see ¶[49-50]). Gim also teaches said write command is to write (accessible) data to storage device 120 where said data is stored (storage device) in storage space 320 (first memory) (see ¶[49], [51]).)
the connection is a computer express link connection (Gim teaches that load/store command, received over interface 440-2 from transmitter 435 (where there is said second connection (connection) between said interface 440-2 and said transmitter 435), uses CXL.mem (computer express link) (see Fig. 4, ¶[52-53]). Note that said CXL.mem (computer express link) is used on said second connection (connection).)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 – 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sinclair (US 20060184720) in view of Gim.
Regarding claim 17, Sinclair teaches
A non-transitory computer storage medium storing instructions which, when executed in a computing system, cause the computing system to perform a method, comprising: (Sinclair teaches controller (computing system) executing (when executed) i) firmware (instructions) stored in non-volatile memory (non-transitory computer storage medium) and boot code (instructions) stored in ROM 209 (non-transitory computer storage medium) (see ¶[212-213]).)
establishing a connection between a host system and a memory sub-system (memory sub-system = Fig. 2, ¶[47] flash memory system used as non-volatile memory 2)[, the connection operable according to a storage access protocol and a cache-coherent memory access protocol]; (Sinclair teaches interface bus 23 interfacing (establishing) with host system (host system) through external contacts 37 (connection) wherein said interface bus is within flash memory system (see Fig. 2, ¶[48], Sinclair claim 10).)
attaching a first memory (first memory = Fig. 2 memory cell arrays 41, 43) of the memory sub-system, over the connection to the host system, as a memory device accessible[, via the cache-coherent memory access protocol]; (Sinclair teaches host system (host system) transferring (accessible) data to buffer memory and then to said flash memory system (see ¶[220]) wherein said data is stored in blocks of memory cell arrays (first memory) (see Sinclair claim 1) of said flash memory system (see Fig. 2, ¶[47]). Note that said host system accesses said memory cell arrays (memory device) via said buffer memory (memory). Sinclair also teaches said memory cell arrays (first memory) are connected (attaching) to interface bus 23 that interfaces with said host system via external contacts 37 (connection) (see Fig. 2, ¶[48], Sinclair claim 10).)
mounting a file system on the memory sub-system; and
configuring, via the memory device, the memory sub-system to manage storage locations of files in the file system (Sinclair teaches said flash memory system (memory sub-system) controller keeps (mounting) its (on) own table (file system) of (manage) where (storage locations) data of each file (files) is stored (see Fig. 9, ¶[81]) wherein said table is file index table (FIT) (see Fig. 19, ¶[167]) that is stored in blocks (see ¶[179]) of said memory cell arrays (first memory) (see Sinclair claim 1) where said host system stores, via buffer memory (memory), data (see ¶[220]) to blocks in said memory cell arrays (memory device) (see Sinclair claim 1). Note that said FIT (file system), which (via) is in said memory cell arrays (first memory, memory device), is used to track where data of each file is stored.)
As noted in claim 17, Sinclair teaches attaching first memory of memory subsystem to host system via connection between said host and said memory subsystem but does not appear to explicitly teach said connection supports storage access protocol and cache-coherent memory access protocol wherein said first memory is accessible as memory device via said cache-coherent memory access protocol.
However, Gim teaches
establishing a connection between a host system and a memory sub-system, the connection operable according to a storage access protocol and a cache-coherent memory access protocol (Gim teaches connecting operating system (host system) to storage device 120 (memory sub-system) via set of connections (connection) between transmitter and interfaces 440-1, 440-2 wherein said storage device includes storage space 320 (see Fig. 4). Gim also teaches i) load/store command (using CXL.mem protocol (cache-coherent memory access protocol)) being sent from said transmitter to said interface 440-2 via said set of connections (see Fig. 4, ¶[52-53]), and ii) write command (using PCIe protocol (storage access protocol)) being sent from said transmitter to said interface 440-1 via said set of connections (see Fig. 4, ¶[49-50]).)
attaching a first memory of the memory sub-system, over the connection to the host system, as a memory device accessible via the cache-coherent memory access protocol (Gim teaches load/store command, received over interface 440-2, is expected to use CXL.mem protocol (cache-coherent memory access protocol) to access (accessible) storage space 320 (first memory) wherein said load/store command enables bye-addressable (memory) access to data stored in said storage space 320 (memory device) (see ¶[34]) of said storage device used to extend memory 115 (see Fig. 4, ¶[25], [52-53]). Gim also teaches said storage space 320 (first memory) is linked to LBA space/physical address that is connected (attaching) to operating system (host system) via said set of connections (connection) between said transmitter and said interfaces 440-1,440-2 (see Fig. 4).)
In view of Gim, Sinclair is modified such that said connection (between said host and said memory subsystem) supports PCIe protocol (storage access protocol) and CXL.mem protocol (cache-coherent memory access protocol) wherein said first memory (memory device) is accessible using load/store command that enables byte-addressable (memory) access.
Sinclair and Gim are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Sinclair in the manner described supra because using different modes to access data based on amount of data to access would avoid delay in reading small amount of data from storage (Gim, ¶[25-26]).
Regarding claim 18, Sinclair in view of Gim teaches the non-transitory computer storage medium of claim 17 where Gim also teaches
attaching the first memory, over the connection to the host system, as a storage device accessible via the storage access protocol;
wherein [the files are] data is accessible both in the memory device and the storage device (Gim teaches using write command (offering block (storage) access) to access (accessible) data (data) stored in storage space 320 (storage device) (see ¶[34]) of storage device 120 wherein said write command is expected to use PCIe protocol (storage access protocol) (see Fig. 4, ¶[49-50]). Gim also teaches said storage space 320 (first memory) is linked to LBA space/physical address that is connected (attaching) to operating system (host system) via said set of connections (connection) between said transmitter and said interfaces 440-1,440-2 (see Fig. 4). Gim further teaches load/store command enables bye-addressable (memory) access (accessible) to data stored in said storage space 320 (memory device) (see ¶[34]) of said storage device used to extend memory 115 (see Fig. 4, ¶[25], [52-53]).)
In view of Gim, modified Sinclair is further modified such that said first memory (storage device) is also accessible using write command that offers block storage (storage) access wherein i) said write command is used to access (accessible) files in said first memory (storage device) and ii) load/store command (enabling byte-addressable (memory) access) is used to access (accessible) said files stored in said first memory (memory device).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Sinclair in the manner described supra because using different modes to access data based on amount of data to access would avoid delay in reading small amount of data from storage (Gim, ¶[25-26]).
Response to Remarks
Applicant’s remarks, with respect to operating system being outside of storage device, have already been addressed in Office Action mailed 01 July 2025. Therefore, remarks in said Office Action would apply to these remarks.
Applicant’s remarks, with respect to newly amendment limitations of claim 11, have been fully considered and are persuasive. Therefore, previous rejection of claim 11 has been withdrawn. However, upon further consideration, new ground(s) of rejection is made in view of newly identified portion of Gim. Therefore, claim 11 stand rejected as noted supra.
Allowable Subject Matter
Claims 1 – 10 have been indicated as allowable over prior art in Office Action mailed 18 March 2025.
Claims 19 – 20 have been indicated as allowable over prior art in Office Action mailed 24 October 2025. It is noted in said Office Action mailed 24 October 2025, there is a typo as it is claim 19 (and not claim 18) that is allowable.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHIE YEW/ Primary Examiner, Art Unit 2139