DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5,7,9-10, 18-23, 25-26, 34-38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paek et al. (US 2019/0245019) in view of Lee et al. (US 2023/0135679).
As to Claim 1 Paek et al. discloses A display apparatus comprising: a substrate including an emission portion of a subpixel (fig.3-substrate 100, first opening area FIRST O/A may correspond to an essive area; para.0054) and a non-emission portion adjacent to the emission portion (fig.3, area outside the boundaries of the first opening area FIRST O/A);
a planarization layer disposed on the substrate, the planarization layer including a groove disposed in the non-emission portion (fig.3, planarization layer 170 including contact hole CH3; para.0053, 0059);
a first electrode disposed in the emission portion and the non-emission portion (fig.3, anode electrode 190 extend from the emissive area FIRST O/A to non-emissive area (area outside FIRST O/A) ; and
a bank disposed in the non-emission portion and provided in a partial region of the first electrode and in the groove (fig.3, bank 180 disposed in non-emissive area under an end region of the anode electrode 190),
wherein the partial region of the first electrode is an end of the first electrode (fig.3, end region of anode electrode 190), wherein the end of the first electrode overlaps the groove (fig.3, end region anode electrode 190 overlaps the contact hole CH3 of planarization layer 170),
wherein a lower surface of the bank provided in the groove is configured between the first electrode and the substrate (fig.3, lower surface of bank 180 is between anode electrode 190 and substrate 100) and an upper surface of a portion of the bank provided in the groove supports a rear surface of the end of the first electrode (fig.3, upper surface of bank 180 supports rear surface of anode 190), and
wherein a thickness of the portion of the bank provided in the groove is equal to a depth of the groove formed in the planarization layer.
Paek et al. discloses where bank 180 is provided on the planarization layer 170 (para.0054).
Paek et al. does not expressly disclose where the bank is disposed in the groove, and wherein a thickness of the portion of the bank provided in the groove is equal to a depth of the groove formed in the planarization layer.
Lee et al. discloses a planarization layer (fig.10,16; planarization layer 170) including a groove (fig.10, groove GR; para.0122,0143), a bank disposed in the groove (fig.10,16; bank portion 181 fills groove GR; para.0122,0144), and wherein a thickness of the portion of the bank provided in the groove is equal to a depth of the groove formed in the planarization layer (fig.10,16; thickness of the portion of bank 181 that fills groove GR is equal to the depth of the groove GR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Paek et al. with the teachings of Lee et al., such that the bank (180 of Paek) fills a groove in the planarization layer (as disclosed by Lee). The motivation to improve the degree of crosslinking of the pixel defining layer at a region adjacent to the light emission opening.
As to Claim 2, Paek et al. in view of Lee et al. disclose where disclose wherein the bank comprises a black material (Lee-para. 0072-0073).
As to Claim 3, Paek et al in view of Lee et al. disclose wherein the bank fills the groove (fig.10, bank 181 fills groove GR; para.0122).
As to Claim 4, Paek et al in view of Lee et al. disclose wherein the bank covers an upper surface, a lower surface, and a lateral surface of the end of the first electrode (Paek-fig.3, bank 180 covers lower surface of electrode 190; Lee-fig.10, bank 181 covers upper, lower and lateral surface of end region of pixel electrode 190).
As to Claim 5, Paek et al. in view of Lee et al. disclose wherein the portion of the bank is disposed under the end of the first electrode (Paek-fig.3, bank 180 under end of electrode 190; Lee-bank 181 fills groove GR disposed under end of electrode 190).
As to Claim 7, Paek et al. in view of Lee et al. disclose wherein the partial region of the first electrode protrudes from the groove (Paek-fig.3, end portion of electrode 190 protrude from the bank 180; Lee-fig.10, end region of electrode 190 protrudes from the grove GR of planarization layer 170).
As to Claim 9, Paek et al. in view of Lee et al. disclose a spacer overlapping the groove (Lee-fig.10,16, spacer 182, protrusion 181d; para.0073).
As to Claim 10, Paek et al. in view of Lee et al. disclose wherein the spacer is disposed on the bank (Lee-fig.10,16; spacer 182 on bank 181; para.0073).
As to Claim 18, Paek et al. in view of Lee et al. disclose an emission unit disposed on the first electrode, the emission unit including an emission layer (Paek- light emitting layer 210 disposed on anode 190, para.0078; Lee-fig.10, light emitting element 300); and a second electrode disposed on the emission unit (Paek-fig.3, cathode 220 disposed on emitting layer 210, para.0078,0084; Lee-fig.10, light emitting element 300).
As to Claim 19, Paek et al. in view of Lee et al. disclose wherein the emission unit comprises a plurality of layers, and includes a charge generating layer disposed between the plurality of layers (Paek-para.0080).
As to Claim 20, Paek et al. discloses A display apparatus comprising: a substrate including an emission portion of a subpixel (fig.3-substrate 100, first opening area FIRST O/A may correspond to an essive area; para.0054) and a non-emission portion adjacent to the emission portion (fig.3, area outside the boundaries of the first opening area FIRST O/A);
a planarization layer disposed on the substrate, the planarization layer including a groove disposed in the non-emission portion (fig.3, planarization layer 170 including contact hole CH3; para.0053, 0059);
a first electrode disposed in the emission portion and the non-emission portion (fig.3, anode electrode 190 extend from the emissive area FIRST O/A to non-emissive area (area outside FIRST O/A) ; and
a first bank disposed in the groove (fig.3, bank 180 disposed on planarization layer 170);
a second bank disposed on the first bank (fig.3, bank 200, para.0067-0068),
wherein an end of the first electrode overlaps the groove and is interposed between the first bank and second bank (fig.3, end of anode electrode 190 overlaps the planarization layer 170 and interposed between bank 200 and bank 180),
wherein a lower surface of the first bank is configured between the first electrode and the substrate (fig.3, lower surface of bank 180 is between anode electrode 190 and substrate 100) and an upper surface of the first bank supports a rear surface of the end of the first electrode (fig.3, upper surface of bank 180 supports rear surface of anode 190), and
wherein a thickness of the first bank is equal to a depth of the groove formed in the planarization layer.
Paek et al. discloses where first bank (bank 180) is provided on the planarization layer 170 (para.0054).
Paek et al. does not expressly disclose where the first bank is disposed in the groove, an end of the first electrode overlaps the groove, and wherein a thickness of the first bank is equal to a depth of the groove formed in the planarization layer.
Lee et al. discloses a planarization layer (fig.10,16; planarization layer 170) including a groove (fig.10, groove GR; para.0122,0143), a bank disposed in the groove (fig.10,16; bank portion 181 fills groove GR; para.0122,0144), an end of the first electrode overlaps the groove (fig.10, end portion of electrode 190 overlaps groove GR), and wherein a thickness of the portion of the bank provided in the groove is equal to a depth of the groove formed in the planarization layer (fig.10,16; thickness of the portion of bank 181 that fills groove GR is equal to the depth of the groove GR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Paek et al. with the teachings of Lee et al., such that the bank (180 of Paek) fills a groove in the planarization layer (as disclosed by Lee). The motivation to improve the degree of crosslinking of the pixel defining layer at a region adjacent to the light emission opening.
As to Claim 21, Paek et al. in view of Lee et al. disclose the thickness of the first bank differs from a thickness of the second bank (Paek-as depicted in fig.3, thickness of bank 180 differs from bank 200).
As to Claim 22, Paek et al. in view of Lee et al. disclose wherein the thickness of the first bank is smaller than the thickness of the second bank (Paek-fig.3, thickness of bank 180 smaller than bank 200).
As to Claim 23, Paek et al. in view of Lee et al. disclose wherein the end of the first electrode is disposed between the first bank and the second bank (Paek-fig.3, electrode 190 interposed between banks 180 and 200), and the first electrode protrudes from the groove (Lee-fig.10,16; electrode 190 protrude from groove GR).
As to Claim 25, Paek et al. in view of Lee et al. disclose a spacer overlapping the groove (Lee-fig.10,16, spacer 182; para.0073).
As to Claim 26, Paek et al. in view of Lee et al. do not expressly disclose wherein the spacer is disposed on the second bank. However, Lee et al. discloses a spacer disposed on bank 181 (Lee-fig.10,16; spacer 182 disposed on bank 181; para.0073). It would have been obvious to one of ordinary skilled in the art to modify the device disclosed by Paek et al. in view of Lee et al. by disposing the spacer on the second bank to provide support for the second electrode from collapsing toward the substrate when the light emitting layer is formed.
As to Claim 34 Paek et al. in view of Lee et al. disclose an emission unit disposed on the first electrode, the emission unit including an emission layer (Paek-fig.3, light emitting layer 210 disposed on anode 190, para.0078; Lee-fig.10,16-light emitting element 300); and a second electrode disposed on the emission unit (Paek-fig.3, cathode 220 disposed on emitting layer 210; para.0078,0084; Lee-fig.10,16-light emitting element 300).
As to Claim 35, Paek et al. in view of Lee et al. disclose wherein the emission unit comprises a plurality of layers, and includes a charge generating layer disposed between the plurality of layers (Paek-para.0080).
As to Claim 36, Paek et al. in view of Lee et al. disclose wherein at least one of the first bank and the second bank are configured to block light for a thin film transistor (TFT) (Paek-fig.3, bank 200, 180 overlap transistor T in non-emissive area; Lee-bank 181 may include black pigment).
As to Claims 37 Paek et al. in view of Lee et al. disclose wherein an entire bottom surface of the groove corresponding to the depth of the groove formed in the planarization layer is in direct contact with the lower surface of the bank filled in the groove (Lee-fig.10,16; bottom surface of groove GR is filled with bank 181; para.0122, 0144).
As to Claim 38, Paek et al. in view of Lee et al. disclose, wherein an entire bottom surface of the groove corresponding to the depth of the groove formed in the planarization layer is in direct contact with the lower surface of the first bank filled in the groove (Lee-fig.10,16; bottom surface of groove GR is filled with bank 181; para.0122, 0144).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paek et al. (US 2019/0245019) in view of Lee et al. (US 2023/0135679), further in view of Kobayashi et al. (US 2009/0230858).
As to Claim 6, Paek et al. in view of Lee et al., do not expressly disclose, but Kobayashi et al. discloses: wherein a thickness of the bank is 1.5 µm to 2.5µm (fig.3-4; para.0067, thickness of bank layer 112b about 2 µm; fig.9-10; para.0113).
Thus, “where claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (see MPEP 2144.05 I). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Paek et al. in view of Lee et al, with the teachings of Kobayashi et al., the motivation being to provide a bank having a desired thickness so as to have a desired pixel aperture.
Claim(s) 11-17, 27-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paek et al. (US 2019/0245019) in view of Lee et al. (US 2023/0135679), further in view of Oh et al. (US 2023/0123503).
As to Claim 11, Paek et al. in view of Lee et al. disclose a first thin film transistor (TFT) on the substrate, the first TFT including a first semiconductor layer, wherein at least one of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor layer. (Paek-fig.3, TFT layer T; para.0041-0042; Lee-fig.10, transistor 200, para.0096).
Paek et al. in view of Lee et al. do not expressly disclose a second TFT on the substrate, the second TFT including a second semiconductor layer.
Oh et al. discloses a first thin film transistor (TFT) on the substrate, the first TFT including a first semiconductor layer (fig.3, switching transistor ST, para.0072,0074-0075) and a second TFT on the substrate, the second TFT including a second semiconductor layer (fig.3, driving transistor DT, para.0072,0074-0075), and wherein at least one of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor layer (para.0075).
It would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Paek et al. in view of Lee et al, with the teachings of Oh et al., the motivation being to provide the circuit elements to drive the light emitting elements.
As to Claim 12, Paek et al. in view of Lee et al., as modified by Oh et al. disclose wherein the first TFT is a switching TFT or a sampling TFT (Oh-fig.3, switching transistor ST).
As to Claim 13, Paek et al. in view of Lee et al., as modified by Oh et al. disclose wherein the second TFT is a driving TFT, and the second TFT comprises a polycrystalline layer (Oh-fig.3, driving transistor DT, para.0075).
As to Claim 14, Paek et al. in view of Lee et al., as modified by Oh et al. disclose a first light blocking layer disposed under the first semiconductor layer (Paek-fig.3, para.0042-light blocking layer may be formed between the substrate and active layer 110; Oh-fig.3, BLM2, para.0072); a second light blocking layer disposed under the second semiconductor layer (Oh-fig.3, BML1 layer; para.0072)
As to Claim 15, Paek et al. in view of Lee et al., as modified by Oh et al. do not expressly disclose wherein a distance between the first semiconductor layer and the first light blocking layer differs from a distance between the second semiconductor layer and the second light blocking layer.
However, Paek et al. in view of Lee et al., as modified by Oh et al., Paek et al. discloses where the light blocking layer may be formed between the substrate and the active layer (Paek-para.0042). Oh et al. further discloses a distance between first semiconductor layer and first light blocking layer (ST_ACT and BML2) and a distance between the second semiconductor layer and second light blocking layer (DT_ACT and BML1). Oh et al. further discloses where the light blocking layers BML1 and BML2 are provided in buffer layer 102 and where buffer layer may be formed as a multilayer (Oh-para.0073).
The re-arrangements of parts or shifting the position of one part to another would not have modified the operation of the device. Therefore, one of ordinary skill in the art would have recognized the arrangement of the light blocking layers BLM1 and BLM2 so as to have different spacing (distance) between respective semiconductor layers, would not have modified the operation of the device, thus yielding predictable results. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975)
As to Claim 16, Paek et al. in view of Lee et al., as modified by Oh et al., do not expressly disclose wherein a distance between the first semiconductor layer and the first blocking layer is greater than a distance between the second semiconductor layer and the second blocking layer.
However, in Paek et al. in view of Lee et al., as modified by Oh et al., Paek et al. discloses where the light blocking layer may be formed between the substrate and the active layer (Paek-para.0042). Oh et al. discloses a distance between first semiconductor layer and first light blocking layer (ST_ACT and BML2) and a distance between the second semiconductor layer and second light blocking layer (DT_ACT and BML1). Oh et al. further discloses where the light blocking layers BML1 and BML2 are provided in buffer layer 102 and where buffer layer may be formed as a multilayer (Oh-para.0073).
The re-arrangements of parts or shifting the position of one part to another would not have modified the operation of the device. Therefore, one of ordinary skill in the art would have recognized the arrangement of the light blocking layers BLM1 and BLM2 so as to have different spacing (distance) between respective semiconductor layer, would not have modified the operation of the device, thus yielding predictable results. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975)
As to Claim 17, Paek et al. in view of Lee et al., as modified by Oh et al., disclose at least one insulation layer between the first blocking layer and the second blocking layer (Oh-para.0069, buffer layer 102 may be an insulating layer).
As to Claims 27-33 have limitations similar to those of Claims 11-17 and are met by the references as set forth above.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 20 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892 form.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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