DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/08/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 7, 11, 13, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2018/0166522, hereinafter Kim522) in view of Kim et al. (US 2021/0313498, hereinafter Kim498).
As to Claim 1, Kim522 discloses A display apparatus comprising: a substrate (fig.10-12; substrate 111; para.0128) including an emission portion of a subpixel (fig.10-12; emission area EA; para.0062) and a non-emission portion adjacent to the emission portion (fig. 10-12; non-emission area where the bank 270 is located; para.0062,0085-0086);
a planarization layer disposed on the substrate, the planarization layer including a groove disposed in the non-emission portion (fig.10, para.0142,0145, planarization layer 250 (fig.12E, recess formed on planarization layer 250));
a first electrode disposed in the emission portion and the non-emission portion (fig.10, first electrode 261 and auxiliary electrode 264 extend to the non-emissive area where bank 270 is located;); and
a bank disposed in the non-emission portion and provided in a partial region of the first electrode and in the groove (fig.10, 12G, bank 270 is in non-emissive area and provided at the edge regions of the first electrode and recess portion of planarization layer 250),
wherein the partial region of the first electrode is an end of the first electrode (fig.10, 12G, end portion of electrodes 261, 264),
wherein the end of the first electrode overlaps the groove (fig.10,12F-12G, end portion of electrode 261 and electrode 264 overlap the recess area of planarization layer 250), and
wherein a lower surface of the bank provided in the groove is configured between the first electrode and the substrate (fig.10, 12G, lower surface of bank 270 is between electrodes 261,264 and substrate 111) and an upper surface of the bank provided in the groove supports a rear surface of the end of the first electrode.
Kim522 does not expressly disclose an upper surface of the bank provided in the groove supports a rear surface of the end of the first electrode.
Kim498 discloses a bank BNL1_1 and planarization layer 19-1 are integrally formed and may formed having different heights, and where an upper surface of the bank BNL1_1 provided in the planarization layer 19_1, supports a rear surface of an end region of electrode 21 {where bank BNL2 is located} (fig.20, para.0214).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim522 with the teachings of Kim498, such that bank may be integrally formed in the planarization layer (150, of Kim522) as disclosed by Kim498, thereby an upper surface supports an end of the first electrode (261,264 of Kim522). The motivation being to reduce the number of processes for forming the display device.
As to claim 3, Kim522 in view of Kim498 disclose wherein the bank fills the groove (Kim522-fig.10, 12G; bank 270, para.0150).
As to claim 4, Kim522 in view of Kim498 disclose wherein the bank covers an upper surface, a lower surface, and a lateral surface of the end of the first electrode (Kim522- fig.10, 12G, bank 270, covers upper end surface, lower end surface, and lateral end surface of electrodes 261, 264).
As to claim 5, Kim522 in view of Kim498 disclose wherein the bank is disposed under the end of the first electrode (Kim522- fig.10, 12G, bank 270 under end portion of electrodes 261,264; Kim498-fig.20, bank BNL1_1 (19_1) under end portion of electrode 21 (where BNL2 is located)).
As to Claim 7, Kim522 in view of Kim498 disclose wherein the partial region of the first electrode protrudes from the groove (Kim522-fig.10, 12F-G, end region electrode 261 and 264 protrude from recess of planarization layer 250).
As to Claim 11, Kim522 in view of Kim498 disclose a first thin film transistor (TFT) on the substrate, the first TFT including a first semiconductor layer (Kim522-fig.10, TFT 210; para.0072-0073; Kim498-fig.3,20); and a second TFT on the substrate, the second TFT including a second semiconductor layer, wherein at least one of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor layer (Kim522-fig.10, TFT 210; para.0072-0073; Kim498- fig.3,20)
As to Claim 13, Kim522 in view of Kim498 disclose wherein the second TFT is a driving TFT, and the second TFT comprises a polycrystalline layer (Kim522- para.0072-0073, 0077; Kim498-fig.3,20, para.0085,0103).
As to Claim 18, Kim522 in view of Kim498 disclose an emission unit disposed on the first electrode (fig.10, organic light emitting device 260,0080), the emission unit including an emission layer (fig.10, organic light emitting layer 262; para.0080,0141); and a second electrode disposed on the emission unit (fig.10, electrode 263; para.0080,0141).
As to Claim 19, Kim522 in view of Kim498 disclose wherein the emission unit comprises a plurality of layers, and includes a charge generating layer disposed between the plurality of layers (Kim522-para.0088-0089, emission layer 262 may be formed in a structure of two or more stacks, and a charge generating layer may be formed between the stacks).
Claim(s) 2, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2018/0166522, hereinafter Kim522) in view of Kim et al. (US 2021/0313498, hereinafter Kim498), further in view of Yang et al. (US 2017/0373124).
As to Claim 2, Kim522 in view of Kim498 do not expressly disclose, Yang discloses: wherein the bank comprises a black material (fig.4, bank 142, para.0100, 0128).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim522 in view of Kim498, with the teachings of Yang et al., the motivation being to reduce reflection of external light.
As to Claim 9, Kim522 in view of Kim498 do not expressly disclose, but Yang et al. discloses: a spacer overlapping the groove (fig.4, spacer 246 overlapping bank 142,141; para.0126-0127).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim522 in view of Kim498, with the teachings of Yang et al., such that a spacer (as disclosed by Yang) may be disposed on the bank in alignment with the recess of planarization layer (of Kim522). The motivation being to suppress defect caused by a contact with a mask when a plurality of transport layers or light emitting layers EML is formed on the emission structure or when an electrode is formed on the emission structure.
As to Claim 10, Kim522 in view of Kim498, as modified by Yang et al. disclose wherein the spacer is disposed on the bank (Yang-fig.4, spacer 246, bank 142, 141).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2018/0166522, hereinafter Kim522) in view of Kim et al. (US 2021/0313498, hereinafter Kim498), further in view of Kobayashi et al. (US 2009/0230858).
As to Claim 6, Kim522 in view of Kim498 do not expressly disclose, but Kobayashi et al. discloses: wherein a thickness of the bank is 1.5 µm to 2.5µm (fig.3-4; para.0067, thickness of bank layer 112b about 2 µm; fig.9-10; para.0113).
Thus, “where claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (see MPEP 2144.05 I). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim522 in view of Kim498, with the teachings of Kobayashi et al., the motivation being to provide a bank having a desired thickness so as to have a desired pixel aperture.
Claim(s) 12, 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2018/0166522, hereinafter Kim522) in view of Kim et al. (US 2021/0313498, hereinafter Kim498), further in view of Oh et al. (US 2023/0123503).
As to Claim 12, Kim522 in view of Kim498, do not expressly disclose but Oh et al. discloses: wherein the first TFT is a switching TFT or a sampling TFT (Oh-fig.3, switching transistor ST, para.0072, 0074; driving transistor DT, para.0072,0074).
It would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim522 in view of Kim498 with the teachings of Oh et al., the motivation being to provide the circuit elements to drive the light emitting elements.
As to Claim 14, Kim522 in view of Kim498, disclose a second light blocking layer disposed under the second semiconductor layer (Kim498-fig.20, light blocking layer BML; para.0100).
Kim522 in view of Kim498, do not expressly disclose a first light blocking layer disposed under the first semiconductor layer.
Oh et al. discloses where a switching transistor ST, where a first light blocking layer disposed under the first semiconductor layer (Oh-fig.3, BML2 layer; para.0072). Oh further discloses a driving transistor DT, and a second light blocking layer disposed under the second semiconductor layer (Oh-fig.3, BML1 layer, para.0072).
It would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim522 in view of Kim498 with the teachings of Oh et al., the motivation being to provide the circuit elements to drive the light emitting elements.
As to Claim 15, Kim522 in view of Kim498, as modified by Oh et al., do not expressly disclose wherein a distance between the first semiconductor layer and the first light blocking layer differs from a distance between the second semiconductor layer and the second light blocking layer.
However, in Kim522 in view of Kim498, as modified by Oh et al., Oh et al. discloses a distance between first semiconductor layer and first light blocking layer (ST_ACT and BML2) and a distance between the second semiconductor layer and second light blocking layer (DT_ACT and BML1). Oh et al. further discloses where the light blocking layers BML1 and BML2 are provided in buffer layer 102 and where buffer layer may be formed as a multilayer (para.0073).
The re-arrangements of parts or shifting the position of one part to another would not have modified the operation of the device. Therefore, one of ordinary skill in the art would have recognized the arrangement of the light blocking layers BLM1 and BLM2 so as to have different spacing (distance) between respective semiconductor layers, would not have modified the operation of the device, thus yielding predictable results. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975)
As to Claim 16, Kim522 in view of Kim498, as modified by Oh et al., do not expressly disclose wherein a distance between the first semiconductor layer and the first blocking layer is greater than a distance between the second semiconductor layer and the second blocking layer.
However, in Kim522 in view of Kim498, as modified by Oh et al., Oh et al. discloses a distance between first semiconductor layer and first light blocking layer (ST_ACT and BML2) and a distance between the second semiconductor layer and second light blocking layer (DT_ACT and BML1). Oh et al. further discloses where the light blocking layers BML1 and BML2 are provided in buffer layer 102 and where buffer layer may be formed as a multilayer (para.0073).
The re-arrangements of parts or shifting the position of one part to another would not have modified the operation of the device. Therefore, one of ordinary skill in the art would have recognized the arrangement of the light blocking layers BLM1 and BLM2 so as to have different spacing (distance) between respective semiconductor layer, would not have modified the operation of the device, thus yielding predictable results. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975)
As to Claim 17, Kim522 in view of Kim498, as modified by Oh et al.., disclose at least one insulation layer between the first blocking layer and the second blocking layer (Oh-para.0069, buffer layer 102 may be an insulating layer).
Claim(s) 20-23, 27, 29, 34-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0359048, hereinafter Kim048) in view of Kim et al. (US 2018/0166522, hereinafter Kim522).
As to Claim 20, Kim048 discloses A display apparatus comprising: a substrate (fig.9, substrate 100) including an emission portion of a subpixel (fig.9, emission area EA;) and a non-emission portion adjacent to the emission portion (fig.9, non- emission area outside area of the EA (where bank BL2-1 is located)),
a planarization layer disposed on the substrate, the planarization layer including a groove disposed in the non-emission portion (fig.9, planarization layer 119; para.0094);
a first electrode disposed in the emission portion and the non-emission portion (fig.2, electrode 121 disposed in EA and non-emissive area (where bank BL2-1 is located)); and
a first bank disposed in the groove (fig.9, bank BL1; para.0166),
a second bank disposed on the first bank (fig.9, bank BL2-1, para.0167),
wherein an end of the first electrode overlaps the groove and is interposed between the first bank and second bank (fig.9, end portion of electrode 121 is interposed between bank BL1 and bank BL2-1), and
wherein a lower surface of the first bank is configured between the first electrode and the substrate (fig.9, lower surface of bank BL1 is between electrode 121 and substrate 100), and
an upper surface of the first bank supports a rear surface of the end of the first electrode (fig.9, upper surface of bank BL1 supports rear surface end of electrode 121).
Kim048 does not expressly disclose the planarization layer including a groove disposed in the non-emission portion; a first bank disposed in the groove; wherein an end of the first electrode overlaps the groove.
Kim522 discloses the planarization layer (fig.10, 12G, planarization layer 250) including a groove (fig.10,12F-G- recess at end portion of planarization layer 250) disposed in the non-emission portion (fig.10, 12F-G, non-emissive area where bank 270 is located; para.0062,0085-0086) a first bank disposed in the groove (fig.10,12F-G, bank 270 provided in the recess), wherein an end of the first electrode overlaps the groove (fig.10, 12F-G, end portion of electrodes 261,264 overlap the recess of planarization layer 250).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim048 with the teachings of Kim522, such that a recess (as disclosed by Kim) may be formed on the planarization layer (119, of Paek, 170) and filled with the bank BL1 (as disclosed by Kim522) in alignment with the end portion of electrode 121 (of Kim048). The motivation being to provide a sunken or recess region in the planarization, thereby further increasing the bank BL1 in the vertical direction. It is further noted, that in doing so would not have modified the operation of the device, yielding predictable results.
As to Claim 21, Kim048 in view of Kim522 disclose wherein a thickness of the first bank differs from a thickness of the second bank (Kim048, as depicted in figs.7,9,10b,12b, bank BL1 and BL2).
As to Claim 22, Kim048 in view of Kim522 disclose wherein a thickness of the first bank is greater than a thickness of the second bank (fig.9, BL1 greater thickness than BL2-1).
As to Claim 23, Paek et al. in view of Kim522 disclose wherein the end of the first electrode is disposed between the first bank and the second bank (Kim048-fig.9, end portion of electrode 121 disposed between bank BL1 and bank BL2-1), and the first electrode protrudes from the groove (Kim522-fig.10,12F-G, end portion of electrode 261 and 264 protrude from recess of planarization layer 250).
As to Claim 27, Kim048 in view of Kim522 disclose a first thin film transistor (TFT) on the substrate, the first TFT including a first semiconductor layer (Kim048-fig.9, TFT; Kim522-fig.10, TFTs 210; para.0072-0073); and a second TFT on the substrate, the second TFT including a second semiconductor layer, wherein at least one of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor layer (Kim522-TFTs 210; para.0072-0073)
As to Claim 29, Kim048 in view of Kim522 disclose wherein the second TFT is a driving TFT (Kim048-TFT para.0062; Kim522-TFT, para.0072-0073, 0077).
As to Claim 34, Kim048 in view of Kim522 disclose an emission unit disposed on the first electrode (Kim048-fig.9, OLED (layers 121,122,123) the emission unit including an emission layer (Kim048-fig.9, emission layer 122; para.0168); and a second electrode disposed on the emission unit (Kim048-fig.9, electrode 123).
As to Claim 35, Kim048 in view of Kim522 disclose wherein the emission unit comprises a plurality of layers, and includes a charge generating layer disposed between the plurality of layers (Kim522-para.0088-0089, emission layer 262 may be formed in a structure of two or more stacks, and a charge generating layer may be formed between the stacks).
Claim(s) 25-26, 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210359048, hereinafter Kim048) in view of Kim et al. (US 2018/0166522, hereinafter Kim522), further in view of Yang et al. (US 2017/0373124).
As to Claim 25, Kim048 in view of Kim522, do not expressly disclose but Yang et al. discloses: comprising a spacer overlapping the groove (fig.4, spacer 246 overlapping bank 142,141; para.0126-0127).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim048 in view of Kim522, with the teachings of Yang et al., such that a spacer (as disclosed by Yang) may be disposed on the bank in alignment with the recess of planarization layer (of Kim522). The motivation being to suppress defect caused by a contact with a mask when a plurality of transport layers or light emitting layers EML is formed on the emission structure or when an electrode is formed on the emission structure.
As to Claim 26, Kim048 in view of Kim522, as modified by Yang et al. wherein the spacer is disposed on the second bank (Yang-fig.4, spacer 246 disposed on bank 142).
As to Claim 36, Kim048 in view of Kim522 do not expressly disclose, but Yang et al. discloses wherein at least one of the first bank and the second bank are configured to block light for a thin film transistor (TFT) (fig.2, bank 142; para.0105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim048 in view of Kim522, with the teachings of Yang et al., the motivation being to reduce reflection of external light.
Claim(s) 28, 30-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210359048, hereinafter Kim048) in view of Kim et al. (US 2018/0166522, hereinafter Kim522), further in view of Oh et al. (US 2023/0123503).
As to Claim 28, Kim048 in view of Kim522 do not expressly disclose, but Oh et al. discloses: wherein the first TFT is a switching TFT or a sampling TFT (Oh-fig.3, switching transistor ST, para.0072, 0074; driving transistor DT, para.0072,0074).
It would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim048 in view of Kim522 with the teachings of Oh et al., the motivation being to provide the circuit elements to drive the light emitting elements.
As to Claim 30, Kim048 in view of Kim522 do not expressly disclose, but Oh et al. discloses: a first light blocking layer disposed under the first semiconductor layer; and a second light blocking layer disposed under the second semiconductor layer.
Oh et al. discloses a first light blocking layer disposed under the first semiconductor layer (Oh-fig.3, switching transistor ST, BML2 layer; para.0072), and a second light blocking layer disposed under the second semiconductor layer(Oh-fig.3, driving transistor DT, BML1 layer, para.0072).
It would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim048 in view of Kim522 with the teachings of Oh et al., the motivation being to block light and prevent light from being incident upon the first and second active material layers of the transistors.
As to Claim 31, Kim048 in view of Kim522, as modified by Oh et al., do not expressly disclose wherein a distance between the first semiconductor layer and the first light blocking layer differs from a distance between the second semiconductor layer and the second light blocking layer.
However, in Kim048 in view of Kim522, as modified by Oh et al., Oh et al. discloses a distance between first semiconductor layer and first light blocking layer (ST_ACT and BML2) and a distance between the second semiconductor layer and second light blocking layer (DT_ACT and BML1). Oh et al. further discloses where the light blocking layers BML1 and BML2 are provided in buffer layer 102 and where buffer layer may be formed as a multilayer (para.0073).
The re-arrangements of parts or shifting the position of one part to another would not have modified the operation of the device. Therefore, one of ordinary skill in the art would have recognized the arrangement of the light blocking layers BLM1 and BLM2 so as to have different spacing (distance) between respective semiconductor layers, would not have modified the operation of the device, thus yielding predictable results. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975)
As to Claim 32, Kim048 in view of Kim522, as modified by Oh et al., do not expressly disclose wherein a distance between the first semiconductor layer and the first light blocking layer is greater than a distance between the second semiconductor layer and the second light blocking layer.
However, in Kim522 in view of Kim498, as modified by Oh et al., Oh et al. discloses a distance between first semiconductor layer and first light blocking layer (ST_ACT and BML2) and a distance between the second semiconductor layer and second light blocking layer (DT_ACT and BML1). Oh et al. further discloses where the light blocking layers BML1 and BML2 are provided in buffer layer 102 and where buffer layer may be formed as a multilayer (para.0073).
The re-arrangements of parts or shifting the position of one part to another would not have modified the operation of the device. Therefore, one of ordinary skill in the art would have recognized the arrangement of the light blocking layers BLM1 and BLM2 so as to have different spacing (distance) between respective semiconductor layer, would not have modified the operation of the device, thus yielding predictable results. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ7 (CCPA 1975)
As to Claim 33, Kim048 in view of Kim522, as modified by Oh et al at disclose least one insulation layer between the first light blocking layer and the second light blocking layer (Oh-para.0069, buffer layer 102 may be an insulating layer).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,20 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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