DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2024/0159518 A1) in view of Dutton et al. (US 2015/0041625 A1) and Moore et al. (US 2017/0115381 A1).
Regarding Claim 1, Wang teaches a time-of-flight (TOF) system ([0108] the depth sensor 800 is a flash LiDAR or an iToF sensor), comprising;
an array of vertical-cavity surface-emitting lasers (VCSELs) ([0108] an VCSEL laser array 810 emits laser light beams 832 to emitting optics 820);
a VCSEL driver configured to drive the VCSEL array during operation to emit light toward a target ([0108] an VCSEL laser array 810 emits laser light beams 832 to emitting optics 820, which may include one or more of a lens, a lens group, a mirror, a prism, micro lenses, diffusers, or any other optics. Emitting optics 820 may include optical structures configured to receive light beams emitted from the VCSEL laser array 810 and transmit the light beams to an FOV as transmission light beams 832. Examiner Note: The presence of the driver is implied by the fact that the VCSEL laser emits laser light beams);
a reference single-photon avalanche diode (SPAD) array positioned to receive a reference light signal ([0108] the time-of-flight engine 850 can compute the distance of target object 870 using the time and/or phase information associated with the return light 852 and a time and/or phase associated with the transmission light beams 832 (or a reference light beam));
a return SPAD array positioned to receive portions of light emitted by the array of VCSELs that reflect off the target ([0108] collecting and directing return light 852 to SPAD array 830 in depth sensor 800. SPAD array 830, as described above, can include highly sensitive light detectors configured to convert detected photons in return light 852 to electrical signals);
reference readout circuitry configured to read out signals from the reference SPAD array ([0108] For example, the time-of-flight engine 850 can compute the distance of target object 870 using the time and/or phase information associated with the return light 852 and a time and/or phase associated with the transmission light beams 832 (or a reference light beam));
return readout circuitry configured to read out signals from the return array ([0108] For example, the time-of-flight engine 850 can compute the distance of target object 870 using the time and/or phase information associated with the return light 852).
Wang is not relied upon as teaching a timing generator configured to generate a base timing reference; first buffer driver circuitry configured to buffer the base timing reference to produce a first timing reference; second buffer driver circuitry configured to buffer the first timing reference to produce a second timing reference; third buffer driver circuitry configured to buffer the base timing reference to produce a third timing reference to clock the return readout circuitry; and calibration circuitry configured to take a first time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the first timing reference, take a second time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the second timing reference, and compensate for an offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first time of flight measurement and the second time of flight measurement.
However, Dutton teaches a timing generator configured to generate a base timing reference ([0053] FIG. 10 shows a phase-locked loop (PLL)-based timing reference generation module 9000 suitable for providing the clock signals for the Flash TDC depicted in FIG. 9, wherein each sampling element receives a different equally spaced timing reference or clock input);
first buffer driver circuitry configured to buffer the base timing reference to produce a first timing reference;
second buffer driver circuitry configured to buffer the first timing reference to produce a second timing reference;
third buffer driver circuitry configured to buffer the base timing reference to produce a third timing reference to clock the return readout circuitry ([0053] It comprises N delay elements 9010 and a charge pump 9020 arranged as shown. The parallel outputs CLK(0)-CLK(N) from the timing reference module 9000 are slightly delayed in time relative to each other. This difference in time creates the sampling window in time. Any mismatch in the delay between two timing reference signals will produce a mismatch in the sampling window manifesting itself as linearity error in the time conversion. Examiner Note: Fig. 10, reproduced below, shows a plurality of buffer driver circuitry elements connected to the base timing reference to produce more than three timing references).
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Wang and Dutton are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing and timing generation systems. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the timing circuitry of Wang to include the timing generator and buffered clock circuitry (comprising first, second, and third buffer driver circuitry) of Dutton with a reasonable expectation of success. This modification would have been motivated by the desire to provide accurate and adjustable clock signals and timing references for sampling elements to reduce linearity errors in time conversion. By integrating Dutton’s teaching of the timing reference generation module into Wang’s system, the system can dynamically buffer and distribute multiple timing references to clock the readout circuitry and handle calibration. A person of ordinary skill in the art would recognize that utilizing Dutton’s buffered timing reference architecture in Wang would yield the predictable result of properly synchronized clock signals and compensated time-of-flight measurements across the readout channels.
Dutton is not relied upon as teaching calibration circuitry configured to take a first time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the first timing reference, take a second time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the second timing reference, and compensate for an offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first time of flight measurement and the second time of flight measurement.
However, Moore teaches calibration circuitry configured to take a first time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the first timing reference, take a second time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the second timing reference, and compensate for an offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first time of flight measurement and the second time of flight measurement ([0004] Time to digital converters are sometimes used in time of flight imaging applications to convert an event arrival time to a time-stamped digital output. [0006] A time to digital converter (TDC) may include a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, the sampling stage providing a respective output for each of the different timing signals. A first synchronization stage may be configured to receive the outputs from the sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals. A second synchronization stage may be configured to receive the synchronized outputs from the first synchronization stage, and synchronize all of the synchronized outputs from the first synchronization stage to the first one of the plurality of timing signals).
Wang (as previously modified by Dutton) and Moore are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight imaging. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the calibration and timing circuitry of Wang (as previously modified by Dutton) to include the calibration circuitry and TDC configuration of Moore (which incorporates Dutton by reference for its time-to-digital converted configuration) with a reasonable expectation of success. This modification would have been motivated by the desire to accurately measure event arrival times and compensate for offsets between readout channels using proven time-to-digital conversion techniques. By integrating Moore’s teaching of the calibration circuitry and TDC configuration into Wang (as previously modified by Dutton)’s system, the system can dynamically take multiple time-of-flight measurements using different timing references and compensate for offsets. A person of ordinary skill in the art would recognize that utilizing Moore’s calibration architecture in Wang would yield the predictable result of eliminated linearity errors and precise distance calculations.
Regarding Claim 12, Wang is not relied upon as teaching that the calibration circuitry includes a multiplexer configured to selectively pass either the first timing reference or the second timing reference to the return readout circuitry based on a control signal from the calibration circuitry.
However, Moore teaches that the calibration circuitry includes a multiplexer configured to selectively pass either the first timing reference or the second timing reference to the return readout circuitry based on a control signal from the calibration circuitry ([0040] To help mitigate the above-noted bin width errors, in some embodiments of the above-described systems a VCSEL pulse control approach may be used to shift the VCSEL pulse onto a different clock phase in each cycle. The output from each TDC 71 is multiplexed so the phases output from the TDC are always aligned to the respective phase of the input VCSEL waveform. Since this multiplexing is done in a synchronous digital domain, no additional error is introduced by the multiplexing. The VCSEL waveform then “sees” every bin location and the associated error. The final range result averages the errors across all bins. Considered alternatively, the VCSEL phase rotation occurs before the output signal takes a differential path through the reference and return arrays. Any minor errors in rotation circuitry is not significant for ranging. [0041] In the timing diagram 80 of FIG. 8 and associated VCSEL start position table 90 of FIG. 9, it may be seen that the VCSEL pulse start (VCSEL START 0-VCSEL START 7) occupies each of the eight locations associated with the eight different phases PLLPHASE<0>-PLLPHASE<7>, which thereby helps to average and effectively eliminate any bin mismatch errors. The output signal multiplexing means the shift is transparent to the digital readout).
Wang (as previously modified by Dutton and Moore) and Moore are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the calibration circuitry of Wang (as previously modified by Dutton and Moore) to include the multiplexer configured to selectively pass either the first timing reference or the second timing reference to the return readout circuitry based on a control signal of Moore with a reasonable expectation of success. This modification would have been motivated by the desire to help mitigate bin width errors and average out bin mismatch errors. By integrating Moore’s teaching of the multiplexer into Wang (as previously modified by Dutton and Moore)’s system, the system can selectively pass and align phases output from the TDC to the respective phases of the input waveform. A person of ordinary skill in the art would recognize that utilizing Moore’s multiplexer configuration in Wang would yield the predictable result of eliminating bin mismatch errors and averaging errors across all bins.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2024/0159518 A1), Dutton et al. (US 2015/0041625 A1), and Moore et al. (US 2017/0115381 A1) in further view of Kim (US 7,109,774 B2).
Regarding Claim 10, Wang is not relied upon as teaching that the third buffer driver circuitry has fewer delay causing elements than the first buffer driver circuitry.
However, Kim teaches that the third buffer driver circuitry has fewer delay causing elements than the first buffer driver circuitry ([Abstract] A delay line unit of a delay locked loop (DLL) circuit, includes a first delay line having a plurality of first unit delays, each first unit delay having a first delay; a second delay line having a plurality of second unit delays, each second unit delay having a second delay; and a third delay line having a plurality of third unit delays, each third unit delay having a third delay, wherein the first delay is shorter than the second delay, and the second delay is shorter than the third delay. [Col. 5, ll. 41-47] Accordingly, if the delay line unit is configured to have a resolution of 65 ps for securing an operation of over 200 MHz, a resolution of 100 ps for securing an operation of 100 to 200 MHz, or a resolution of 150 ps for 100 MHz, 77 first unit delays in the first delay line 810, 50 second unit delays in the second delay line 820, and 14 third unit delays in the third delay line 830 are required).
Wang (as previously modified by Dutton and Moore) and Kim are considered to be analogous to the claimed invention because they are both in the same field of electronic timing references. Therefore, it would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the buffer driver circuitry of Wang (as previously modified by Dutton and Moore) to include the third buffer driver circuitry having fewer delay-causing elements than the first buffer driver circuitry of Kim with a reasonable expectation of success. This modification would have been motivated by the desire to configure delay lines units with adjustable resolutions and selectable operating frequencies. By integrating Kim’s teaching of the delay line unit into Wang (as previously modified by Dutton and Moore)’s system, the system can selectively provide different unit delays and resolutions. A person of ordinary skill in the art would recognize that utilizing Kim’s delay element configuration in Wang would yield the predictable result of securing precise operating frequencies and customizable timing resolutions.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2024/0159518 A1), Dutton et al. (US 2015/0041625 A1), and Moore et al. (US 2017/0115381 A1) in further view of Kappel et al. (US 2020/0379095 A1).
Regarding Claim 13, Wang is not relied upon as teaching that the calibration circuitry is further configured to perform the first and second time of flight measurements during a calibration phase that precedes normal operation of the TOF system.
However, Kappel teaches that the calibration circuitry is further configured to perform the first and second time of flight measurements during a calibration phase ([0171] Thus, the photodiode circuit 50 shown in FIG. 16 is configured for the calibration phase and the measurement phase… Use of a double differential measurement setup requires two rounds of measurements) that precedes normal operation of the TOF system ([0193] A calibration phase may be performed before each measurement phase or in predetermined time intervals).
Wang (as previously modified by Dutton and Moore) and Kappel are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing systems. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the calibration circuitry of Wang (as previously modified by Dutton and Moore) to include performing the first and second time of flight measurements during a calibration phase that precedes normal operation of the time-of-flight system as taught by Kappel with a reasonable expectation of success. This modification would have been motivated by the desire to calibrate photodiode and measurement circuits prior to normal operation to ensure accurate data capture. By integrating Kappel’s teaching of a calibration phase into Wang (as previously modified by Dutton and Moore)’s system, the system can execute double differential measurement setups and perform calibration routines before each measurement phase or at predetermined time intervals. A person of ordinary skill in the art would recognize that utilizing Kappel’s pre-operational calibration phase in Wang would yield the predictable result of compensating for circuit offsets and improving measurement accuracy before normal time-of-flight operation begins.
Regarding Claim 14, Wang is not relied upon as teaching that the return readout circuitry includes first return readout circuitry used by the calibration circuitry to take the first time of flight measurement and used by control circuitry to take time of flight measurements of the reference readout circuitry during normal operation, and second return circuitry used by the calibration circuitry to take the second time of flight measurement.
However, Kappel teaches that the return readout circuitry includes first return readout circuitry used by the calibration circuitry to take the first time of flight measurement and used by control circuitry to take time of flight measurements of the reference readout circuitry during normal operation ([0044]-[0045] a TOF arrangement is free of an optical barrier that separates the at least one photodiode circuit comprised by a calibration or reference sensor from at least another photodiode circuit comprised by a measurement sensor… Thus, the photodiode circuit 50 shown in FIG. 16 is configured for the calibration phase and the measurement phase), and second return circuitry used by the calibration circuitry to take the second time of flight measurement ([0107] This enable switch 59 is off during operation. In FIG. 3A, no external trigger signal is used during a calibration phase. Therefore, a trigger event of the SPAD 51 due to a photon or dark count is needed for calibration. In case of an event, the signal is detected by the fast sense buffer 58 which is connected to the input side of the TDC 14, e.g. to the start input 16. In parallel, the signal propagates through the readout buffer 57 and the readout logic 63 to the input side of the TDC 14, e.g. to the first stop input 17. The difference in time TDC stop-TDC start represents the readout delay L3, also named delay_sensor_to_TDC).
Wang (as previously modified by Dutton and Moore) and Kappel are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing and readout circuitry arrangements. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the return readout circuitry of Wang to include first return readout circuitry used by the calibration circuitry to take the first time of flight measurements and used by control circuitry to take time of flight measurements of the reference readout circuitry during normal operation, and second return circuitry used by the calibration circuitry to take the second time of flight measurement as taught by Kappel with a reasonable expectation of success. This modification would have been motivated by the desire to configure shared photodiode and readout circuits for both calibration and measurement phases without requiring a separating optical barrier. By integrating Kappel’s teaching of the dual-use return readout circuitry into Wang (as previously modified by Dutton and Moore)’s system, the system can utilize enable switches, fast sense buffers, and readout logic to capture events and calculate readout delay lines during calibration and normal operation. A person of ordinary skill in the art would recognize the utilizing Kappel’s readout configuration in Wang (as previously modified by Dutton and Moore) would yield the predictable result of properly routing calibration and measurement signals through the TDC inputs to measure readout delays.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2024/0159518 A1), Dutton et al. (US 2015/0041625 A1), and Moore et al. (US 2017/0115381 A1) in further view of Applicant Admitted Prior Art (Herein after AAPA).
Regarding Claim 15, Wang is not relied upon as teaching that the reference light signal is formed by portions of light that reflect off an interior of a housing of the TOF system.
However, AAPA teaches that the reference light signal is formed by portions of light that reflect off an interior of a housing of the TOF system ([P. 2, ll. 4-13 and Fig. 1] Within the outgoing signal chamber 12, a Vertical-Cavity Surface-Emitting Laser (VCSEL) substrate 15 houses the VCSEL 16. The majority of the infrared laser beam produced by the VCSEL 16 forms an outgoing beam 17 directed towards a target object, while a portion of the infrared laser beam produced by the VCSEL 16 bounces off the interior of the housing 11 to form a reference beam 18. The reference laser beam 18 reflects off the interior of the housing 11 within the outgoing signal chamber 12 to strike a reference array of Single-Photon Avalanche Diodes (SPADs) 20, embedded within a substrate 19. These reference SPADs 20 detect the arrival of the reference beam 18, establishing a reference time-of-flight value. The optical barrier 14 prevents the outgoing beam 17 and reference beam 18 from reaching the incoming signal chamber 13).
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Wang (as previously modified by Dutton and Moore) and AAPA are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing and optical housing systems. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the reference light signal configuration of Wang (as previously modified by Dutton and Moore) to include portions of light that reflect of an interior of a housing of the time-of-flight system as taught by AAPA with a reasonable expectation of success. This modification would have been motivated by the desire to generate a reliable reference beam internally within the outgoing signal chamber without needing external optical components. By integrating AAPA’s teaching of housing reflections into Wang (as previously modified by Dutton and Moore)’s system, the system can bounce a portion of the infrared laser beam off the interior of housing 11 to form a reference beam 18 that spikes a reference array 20. A person of ordinary skill in the art would recognize that utilizing AAPA’s internal housing reflection configuration in Wang (as previously modified by Dutton and Moore) would yield the predictable result of establishing an internal reference time-of-flight value using the existing structural enclosure.
Claims 16 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kappel et al. (US 2020/0379095 A1) in view of Applicant Admitted Prior Art (Herein after AAPA), Dutton et al. (US 2015/0041625 A1), and Moore et al. (US 2017/0115381 A1).
Regarding claim 16, Kappel teaches a method for calibrating a time-of-flight (TOF) system in a calibration phase ([0007] the TOF arrangement is configured to operate in a calibration phase and in a measurement phase, wherein a delay information is determined in the calibration phase), the method comprising:
emitting light toward a target ([0077] The laser 15 emits light through the first opening of the housing 40. This light is reflected by a target 45);
receiving light that reflects off the target at a return array ([0077] The reflected light may be absorbed by a photodiode of one of the photodiode circuits 13, 18, 19);
reading out signals from the return array using return readout circuitry ([0077] The reflected light may be absorbed by a photodiode of one of the photodiode circuits 13, 18, 19 resulting in the measurement readout signal SM of one of the measurement photodiode circuits 13, 18, 19); and
generating a base timing reference with a timing generator ([0079] The clock generator 11 generates a clock signal CLK).
Kappel is not relied upon as teaching receiving a reference light signal at a reference array;
reading out the reference light signal using reference readout circuitry; applying a first time delay to the base timing reference to produce a first timing reference; applying a second time delay to the first timing reference to produce a second timing reference; applying a third time delay to the base timing reference to produce a third timing reference to clock the return readout circuitry; taking a first time of flight measurement using the return readout circuitry when clocked by the first timing reference; taking a second time of flight measurement using the return readout circuitry when clocked by the second timing reference; and taking a first time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the first timing reference, take a second time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the second timing reference, and compensate for an offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first time of flight measurement and the second time of flight measurement.
However, AAPA teaches receiving a reference light signal at a reference array; and reading out the reference light signal using reference readout circuitry ([P. 2, ll. 4-13 and Fig. 1] Within the outgoing signal chamber 12, a Vertical-Cavity Surface-Emitting Laser (VCSEL) substrate 15 houses the VCSEL 16. The majority of the infrared laser beam produced by the VCSEL 16 forms an outgoing beam 17 directed towards a target object, while a portion of the infrared laser beam produced by the VCSEL 16 bounces off the interior of the housing 11 to form a reference beam 18. The reference laser beam 18 reflects off the interior of the housing 11 within the outgoing signal chamber 12 to strike a reference array of Single-Photon Avalanche Diodes (SPADs) 20, embedded within a substrate 19. These reference SPADs 20 detect the arrival of the reference beam 18, establishing a reference time-of-flight value. The optical barrier 14 prevents the outgoing beam 17 and reference beam 18 from reaching the incoming signal chamber 13.).
Kappel and AAPA are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing and calibration systems. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the calibration method of Kappel to include receiving a reference light signal at a reference array and reading out the reference light signal using reference readout circuitry as taught by AAPA with a reasonable expectation of success. This modification would have been motivated by the desire to establish an accurate internal reference time-of-flight value for calibration purposes. By integrating AAPA’s teaching of the reference array and reference readout circuitry into Kappel’s system, the system can detect an internal reference beam striking a reference array of SPADs. A person of ordinary skill in the art would recognize that utilizing AAPA’s reference signal detection in Kappel would yield the predictable result of providing a reliable baseline reference value to compensate for system offsets during calibration.
AAPA is not relied upon as teaching applying a first time delay to the base timing reference to produce a first timing reference; applying a second time delay to the first timing reference to produce a second timing reference; applying a third time delay to the base timing reference to produce a third timing reference to clock the return readout circuitry; taking a first time of flight measurement using the return readout circuitry when clocked by the first timing reference; taking a second time of flight measurement using the return readout circuitry when clocked by the second timing reference; and taking a first time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the first timing reference, take a second time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the second timing reference, and compensate for an offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first time of flight measurement and the second time of flight measurement.
However, Dutton teaches applying a first time delay to the base timing reference to produce a first timing reference;
applying a second time delay to the first timing reference to produce a second timing reference; and
applying a third time delay to the base timing reference to produce a third timing reference to clock the return readout circuitry ([0053] It comprises N delay elements 9010 and a charge pump 9020 arranged as shown. The parallel outputs CLK(0)-CLK(N) from the timing reference module 9000 are slightly delayed in time relative to each other. This difference in time creates the sampling window in time. Any mismatch in the delay between two timing reference signals will produce a mismatch in the sampling window manifesting itself as linearity error in the time conversion. Examiner Note: Fig. 10, reproduced above, shows a plurality of buffer driver circuitry elements connected to the base timing reference in series to produce more than three timing references).
Kappel (as previously modified by AAPA) and Dutton are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing and timing generation systems. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the calibration method of Kappel (as previously modified by AAPA) to include applying a first time delay to the base timing reference to produce a first timing reference, applying a second time delay to the first timing reference to produce a second timing reference, and applying a third time delay to the base timing reference to produce a third timing reference to clock the return readout circuitry as taught by Dutton with a reasonable expectation of success. This modification would have been motivated by the desire to generate precise, multi-phase clock signals and timing references to reduce linearity errors in time conversion. By integrating Dutton’s teaching of the timing reference generation module into Kappel (as previously modified by AAPA)’s system, the system can utilize delay elements and a charge pump to produce adjustable, delayed parallel outputs for clocking readout circuitry. A person of ordinary skill in the art would recognize that utilizing Dutton’s buffered timing architecture in Kappel (as previously modified by AAPA)’s calibration method would yield the predictable result of providing synchronized timing references to accurately measure and compensate for time-of-flight offsets.
Dutton is not relied upon as teaching taking a first time of flight measurement using the return readout circuitry when clocked by the first timing reference; taking a second time of flight measurement using the return readout circuitry when clocked by the second timing reference; and taking a first time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the first timing reference, take a second time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the second timing reference, and compensate for an offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first time of flight measurement and the second time of flight measurement
However, Moore teaches
taking a first time of flight measurement using the return readout circuitry when clocked by the first timing reference;
taking a second time of flight measurement using the return readout circuitry when clocked by the second timing reference; and
taking a first time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the first timing reference, take a second time of flight measurement using the return readout circuitry when the return readout circuitry is clocked by the second timing reference, and compensate for an offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first time of flight measurement and the second time of flight measurement ([0004] Time to digital converters are sometimes used in time of flight imaging applications to convert an event arrival time to a time-stamped digital output. [0006] A time to digital converter (TDC) may include a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, the sampling stage providing a respective output for each of the different timing signals. A first synchronization stage may be configured to receive the outputs from the sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals. A second synchronization stage may be configured to receive the synchronized outputs from the first synchronization stage, and synchronize all of the synchronized outputs from the first synchronization stage to the first one of the plurality of timing signals).
Kappel (as previously modified by AAPA and Dutton) and Moore are considered to be analogous to the claimed invention because they are both in the same field of time-of-flight sensing. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the calibration and measurement method of Kappel (as previously modified by AAPA and Dutton) to include taking a first time-of-flight measurement using the return readout circuitry when clocked by the first timing reference, taking a second time-of-flight measurement using the return readout circuitry when clocked by the second timing reference, and taking measurements where the return readout circuitry is clocked by the respective timing references to compensate for an offset between time-of-flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation based on at least the first and second time-of-flight measurements as taught by Moore with a reasonable expectation of success. This modification would have been motivated by the desire to accurately convert event arrival times into timestamped digital outputs and eliminate systematic offset errors by utilizing multi-phase sampling. By integrating Moore’s teaching of time-to-digital converters, sampling stages operating on a plurality of timing signals having different respective phases, and synchronization stages into the combined system, the arrangement can effectively handle multi-phase clocked measurements. A person of ordinary skill in the art would recognize that utilizing Moore’s phase-sampled TDC and compensation framework in the Kappel (as previously modified by AAPA and Dutton) architecture would yield the predictable result of achieving high-precision, phase-aligned time-of-flight measurements and robust offset compensation.
Regarding Claim 22, Kappel teaches that the calibration phase includes using a multiplexer to selectively pass either the first timing reference or the second timing reference to the return readout circuitry based on a control signal ([0142] the TOF arrangement 10 comprises switches and/or multiplexers. In a first part of the calibration phase, the TOF arrangement 10 is configured to measure the delay L3 of the readout logic 62 as shown in FIGS. 5 and 6. In a second part of the calibration phase, the TOF arrangement 10 is configured to measure the delays L1+L2 of the laser driver 12 as shown in FIGS. 7 and 8. The first part may be before or after the second part. In the measurement phase, the TOF arrangement 10 is configured to measure the time-of-flight TOF, as shown in FIG. 9. The not-shown switches and multiplexers connect appropriate nodes and outputs to the start input 16 and the first and the second stop input 17, 93 in the parts of the calibration phase and the measurement phase).
Regarding Claim 23, Kappel teaches that the calibration phase is performed prior to normal operation of the TOF system ([0193] A calibration phase may be performed before each measurement phase or in predetermined time intervals) and involves using first return readout circuitry to take the first time of flight measurement and second return readout circuitry to take the second time of flight measurement ([0107] This enable switch 59 is off during operation. In FIG. 3A, no external trigger signal is used during a calibration phase. Therefore, a trigger event of the SPAD 51 due to a photon or dark count is needed for calibration. In case of an event, the signal is detected by the fast sense buffer 58 which is connected to the input side of the TDC 14, e.g. to the start input 16. In parallel, the signal propagates through the readout buffer 57 and the readout logic 63 to the input side of the TDC 14, e.g. to the first stop input 17. The difference in time TDC stop-TDC start represents the readout delay L3, also named delay_sensor_to_TDC).
Allowable Subject Matter
Claims 2-9, 11, and 17-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, Kappel teaches that the calibration circuitry compensates for the offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation as a function of the first time of flight measurement, the second time of flight measurement ([0171] Thus, the photodiode circuit 50 shown in FIG. 16 is configured for the calibration phase and the measurement phase… Use of a double differential measurement setup requires two rounds of measurements).
However, Kappel and the other references cited in this Office action, alone or in combination, do not teach compensat[ing] for the offset between time of flight measurements taken by the return readout circuitry and the reference readout circuitry during normal operation as a function of a number of delay causing elements within the second buffer driver circuitry, and a difference between a number of delay causing elements within the first buffer driver circuitry and a number of delay causing elements within the third buffer driver circuitry.
Claim 17 recites the same features considered allowable in claim 2 referenced above and is considered to contain allowable subject matter for similar reasons. Claims 3-11 depend from Claim 2 and Claims 18-21 depend from 17. Claims 3-9, 11, and 18-21 are considered to contain allowable subject matter for reasons of dependency.
Conclusion
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/E.H.H./Patent Examiner, Art Unit 3645
/HELAL A ALGAHAIM/SPE , Art Unit 3645
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