DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 18440226 in view of Tsai et al. (US 2011/0295539 A1), hereinafter Tsai.
Application No. 18/440,191
Application No. 18/440,226
Claim 1
A
a formation comprising one or more layers and comprising a plurality of thermal zones
a first thermal zone of said plurality of thermal zones configured to apply thermal energy to a first thermal region of said wafer DUT;
a second thermal zone of said plurality of thermal zones configured to apply thermal energy to a second thermal region of said wafer DUT,
wherein said second thermal zone is configured to control a temperature of said second thermal region of said
wherein said first thermal zone is configured to control a temperature of said first thermal region of said wafer DUT independently of a temperature of said second thermal region, and wherein said formation further comprises a plurality of thermal resistance structures located between said plurality of thermal zones, said plurality of thermal resistance structures configured to limit conductance of thermal energy between said plurality of thermal zones.
Claim 1
An active thermal interposer (ATI) device for testing a device under test (DUT), said ATI device comprising:
a formation comprising one or more layers, said formation comprising: a first thermal zone; and a second thermal zone;
said first thermal zone configured to apply thermal energy to a first thermal region of said DUT,
said second thermal zone configured to apply thermal energy to a second thermal region of said DUT,
wherein said second thermal zone is configured to control a temperature of said second thermal region of said DUT independently of a temperature of said first thermal region of said DUT,
wherein further said first thermal zone is configured to control said temperature of said first thermal region of said DUT independently of said temperature of said second thermal region of said DUT; and a thermal resistance structure, disposed in said formation and located between said first thermal zone and said second thermal zone, said thermal resistance structure configured to limit conductance of thermal energy therebetween.
But 18/440,226 does not specifically teach configured to apply thermal energy to a plurality of dice of said wafer DUT during said testing thereof and wherein said plurality of thermal zones corresponds to a die layout of said wafer DUT. However, Tsai et al. (US 2011/0295539 A1) suggests configured to apply thermal energy to a plurality of dice of said wafer DUT during said testing thereof and wherein said plurality of thermal zones corresponds to a die layout of said wafer DUT (para [0014]; radiation source of the thermal process chamber directs thermal energy or incident infrared radiation to a DUT to heat the DUT; the DUT may be a semiconductor wafer, a semiconductor chip, multiple such semiconductor chips, a circuit board, or virtually any other device). Furthermore, It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify 18/440,226 in view of Tsai because in semiconductor device fabrication, the characterization and measurement of the temperature variation across a wafer undergoing a thermal process in a thermal process chamber is critical for circuit performance and manufacturability (Tsai, para [0004]).
Comments
The prior art of record found as a result of the search, does not teach alone or in combination all the elements recited in claims 1. Specifically, the prior art of record does not teach claimed limitation: “a formation comprising one or more layers and comprising a plurality of thermal zones configured to apply thermal energy to a plurality of dice of said wafer DUT during said testing thereof and wherein said plurality of thermal zones corresponds to a die layout of said wafer DUT; a first thermal zone of said plurality of thermal zones configured to apply thermal energy to a first thermal region of said wafer DUT; a second thermal zone of said plurality of thermal zones configured to apply thermal energy to a second thermal region of said wafer DUT, wherein said second thermal zone is configured to control a temperature of said second thermal region of said wafer DUT independently of a temperature of said first thermal region, wherein said first thermal zone is configured to control a temperature of said first thermal region of said wafer DUT independently of a temperature of said second thermal region, and wherein said formation further comprises a plurality of thermal resistance structures located between said plurality of thermal zones, said plurality of thermal resistance structures configured to limit conductance of thermal energy between said plurality of thermal zones.”. Therefore, no prior art rejection for claim 1 is presented in this action. Claims 2-13, which dependent from claim 1, would be allowable in the event that the double patenting rejection is resolved.
Allowable Subject Matter
Claims 14-30 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 14, the prior art of record neither shows nor suggests the combination of structural elements comprising a test stack coupled to said tester system, said test stack comprising: a wafer probe for contacting a first surface of said wafer and for probing individual circuits of said circuits of said wafer; a thermal interposer device operable to contact a second surface of said wafer and comprising a plurality of heating zones corresponding to a die layout of said wafer and operable to selectively heat a plurality of regions of said wafer during said testing, wherein said thermal interposer device comprises a plurality of thermal resistance structures disposed between said plurality of heating zones and configured to limit conductance of thermal energy between said plurality of heating zones; a cold plate disposed adjacent to a surface of said thermal interposer device and operable to cool said wafer; and a thermal controller for selectively heating and maintaining temperatures of said plurality of regions of said wafer by controlling cooling of said cold plate and by controlling selective heating of said plurality of heating zones of said thermal interposer device.
Claims 15-22 depend from allowed claim 14 and are therefore also allowed.
With respect to claim 23, the prior art of record neither shows nor suggests the combination of structural elements comprising a tester system for testing said circuits of said wafer; and a test stack coupled to said tester system, said test stack comprising: a wafer probe for contacting a top surface of said wafer and for probing individual circuits of said circuits of said wafer; a thermal interposer device operable to contact a bottom surface of said wafer and comprising a plurality of discretely controllable thermal zones, wherein each thermal zone of said plurality of discretely controllable thermal zones is operable to be discretely and selectively heated to selectively heat a corresponding area of said wafer, wherein said thermal interposer device comprises a plurality of thermal resistance structures operable to limit thermal energy conductance between said plurality of discretely controllable thermal zones; and a cold plate disposed under said thermal interposer device and operable to cool said wafer; and a thermal controller for selectively heating and maintaining temperatures of areas of said wafer by controlling cooling of said cold plate and by controlling heating of said plurality of discretely controllable thermal zones of said thermal interposer device.
Claims 24-28 depend from allowed claim 23 and are therefore also allowed.
With respect to claim 29, the prior art of record neither shows nor suggests the combination of method steps of testing said circuits of said wafer using a tester system; and in conjunction with performing said testing, selectively heating and maintaining temperatures of a plurality of areas of said wafer by using a thermal controller controlling a thermal interposer and a cold plate, both disposed in proximity of said wafer and wherein dimensions of said thermal interposer are customized for said wafer, and wherein said thermal interposer comprises a plurality of separately controllable thermal zones wherein each thermal zone of said plurality of separately controllable thermal zones is operable to be selectively heated and temperature maintained by said thermal controller, and wherein said thermal interposer further comprises a plurality of thermal resistance structures located between said plurality of separately controllable thermal zones, said plurality of thermal resistance structures is configured to limit conductance of thermal energy between said plurality of separately controllable thermal zones.
Claim 30 depends from allowed claim 29 and is therefore also allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PUB 2018/0095127 discloses systems, methods, and apparatuses for implementing testing of fault repairs to a through silicon via (tsv) in two-level memory (2lm) stacked die subsystems.
US PUB 2018/0031629 discloses a test board for semiconductor package, test system, and method of manufacturing semiconductor package.
US PUB 2015/0241471 discloses a probe card.
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/TEMILADE S RHODES-VIVOUR/Examiner, Art Unit 2858
/GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 5/15/2026
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