DETAILED ACTION
Status of Claims
This action is in reply to the communication filed on 07/23/2026.
Claims 1, 7, 9, and 16 have been amended.
Claim 21 has been added.
Claims 15 and 20 have been cancelled.
Claims 1-14, 16-19, and 21 are currently pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 07/23/2026 with respect to the rejections under 35 USC § 102/103 have been considered but are moot in view of the new grounds of rejection.
Claim Interpretations
The following is a quotation of 35 U.S.C. 112(f):
(f) ELEMENT IN CLAIM FOR A COMBINATION.—An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims include one or more elements which are being interpreted as invoking 35 U.S.C. 112(f).
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element is limited by the description in the specification when 35 U.S.C. 112(f), is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as "configured to" or "so that"; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “means” and/or that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
Claim 1: subsystem configured to switch between two or more contexts (Applicant’s Specification (AppSpec) ¶0045, 0049-0050); a bandwidth monitoring subsystem configured to limit access to the memory… (AppSpec: ¶0064-0067, 0075-0076); resource management subsystem configured to enforce memory bandwidth limitations…(AppSpec: ¶0065-0067, 0076-0077). Claims 5, 13, 18: first/second bandwidth monitor is configured to limit access to the memory by the first subsystem when the first subsystem is configured for the first/second context (AppSpec: ¶0068-0069, 0079, 0084-0085). Claim 16: means for enforcing memory bandwidth limitations...(AppSpec: ¶0065-0067, 0076-0077); means for providing virtualized contexts…(AppSpec: ¶0056, 0080). Claim 20: means for measuring data access rates…(AppSpec: ¶0067, 0083, 0113).
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have the limitation(s) above interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 9, 10, 12, 13, 16-18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger (US 2021/0208924 A1) in view of Yi et al. (“MT2: Memory Bandwidth Regulation on Hybrid NVM/DRAM Platforms”, 2022, cited in PTO-892 of the 05/12/2026 Non-Final OA).
Claim 1:
Krueger discloses the limitations as shown in the following rejections:
A multiprocessing apparatus comprising: memory configured to support a maximum data access rate expressed as memory bandwidth (¶0043-0046; FIG. 1).
a plurality of subsystems coupled to the memory, each of the plurality of subsystems (processing units/elements) being configured to switch between two or more contexts (partitions/software execution environments/operating state) (¶0043, 0047-0048, 0061-0065; FIG. 1). Exemplary quotation:
“a software execution environment may comprise an application, a guest operating system or virtual machine…or a sub-portion of any of these types of processes (e.g. a single virtual machine may have different parts considered as separate software execution environments). As shown in FIG. 2, each software execution environment may be allocated a given partition identifier” (¶0043).
a bandwidth monitoring subsystem (memory system component, particularly control registers and parameter selection logic) configured to limit access to the memory by a first subsystem to a first portion (maximum bandwidth threshold/limit) of the memory bandwidth when the first subsystem is configured for a first context (partition ID), and to limit access to the memory by the first subsystem to a second portion of the memory bandwidth when the first subsystem is configured for a second context; and a resource management subsystem (memory system component, particularly memory controller) configured to enforce memory bandwidth limitations defined by the bandwidth monitoring subsystem based on context in which the first subsystem is operated (see at least ¶0049-0051, 0125-0128, 0157-0161; FIG. 2, 12, 16). Exemplary quotation(s):
“resource allocation or contention resolution operations can be controlled based on one of a number of sets of memory system component parameters selected based on the partition identifier…in a memory system component such as the memory controller 24 which has a finite amount of bandwidth available for servicing memory transactions, minimum and/or maximum bandwidth thresholds may be specified for each partition identifier” (¶0049-0050).
“for system components which support resource partitioning, the memory system component selects a set of memory system component parameters based on the partition ID. The memory system component parameters may be resource control parameters which are used to control allocation of memory system resources (such as bandwidth, cache capacity, etc.) or contention for those resources…If the memory system component supports memory system resource partitioning (step 202), then at step 204 a set of resource control parameters is selected base on the partition ID and the security state...At step 206, allocation of resources is controlled using the selected set of resource control parameters, or contention for those resources is managed using the selected set of resource parameters” (¶0125-0126).
Krueger further discloses (¶0150-0154, 0157, 0165, 0170-0171) the memory bandwidth limitations are specified in reconfigurable registers but does not explicitly disclose redefine the memory bandwidth limitations when changes are detected in memory bandwidth usage…wherein the memory bandwidth limitations are redefined by reconfiguring registers in the resource management subsystem.
Yi, however, discloses (pg. 199, Abstract; pg. 202, § 3.1; pg. 203-204, § 3.3; pg. 205, § 3.3.2; pg. 209, col. 1) an analogous system and methods of limiting access to memory bandwidth by different application thread Throttling Groups (“TGroups”) (contexts) including operations to redefine the memory bandwidth limitations (dynamically throttle memory request rate) when changes are detected in memory bandwidth usage (occurrence of excessive memory contention/interference) including using Intel Memory Bandwidth Allocation (MBA) hardware regulation mechanism (the resource management subsystem) (pg. 202, col. 1; pg. 206, col. 1) including defining/updating throttle values and TGroup bandwidth allocations via control Model Specific Registers (MSR)1 of the MBA HW (redefined by reconfiguring registers in the resource management subsystem). Exemplary quotations:
“MT2 adopts a dynamic bandwidth throttling algorithm that constantly monitors and adjusts restrictions based on the real-time bandwidth and the interference level (§ 3.1)...Monitoring the bandwidth information is the first step towards bandwidth regulation. The following step is to restrict the bandwidth a TGroup can occupy, which is handled by the regulator. The regulator takes the interference level and the monitored bandwidth as the input and decides what actions to take to adjust the bandwidth of the TGroup according to the regulation policy (§ 3.3)…The MBA hardware supports ten MBA throttling values...To set up the MT2 context for each thread, including setting the PMU related context, writing the MSR registers related to MBA” (pg. 206, col. 1).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Krueger to employ the dynamic bandwidth regulation of Yi’s MT2 because “Evaluation shows that MT2 can effectively regulate the bandwidth among applications with nearly zero performance overhead and can be used in multiple use cases” and to avoid wasting utilization of memory hardware when shared memory interference of competing applications is low.
Claim 2:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses wherein the first context corresponds to a first use case (operating state and/or application thereof) and the second context corresponds to a second use case (¶0048, 0060, 0063-0064, 0185).
Claim 4:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses a hypervisor configured to provide virtualized contexts in which virtual machines are operated, wherein the first context comprises a first virtualized context and the second context comprises a second virtualized context (¶0048, 0060, FIG. 4 and 5).
Claim 5:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses the bandwidth monitoring subsystem comprises a first bandwidth monitor (set of control register parameters) configured to limit access to the memory by the first subsystem when the first subsystem is configured for the first context, and a second bandwidth monitor configured to limit access to the memory by the first subsystem when the first subsystem is configured for the second context (¶0125-0128, 0157, 0169-0171).
Claim 9:
Krueger discloses the limitations as shown in the following rejections:
A method for managing memory access comprising: allocating memory bandwidth among two or more subsystems (processing units/elements) based on current contexts (partitions/software execution environments/operating state) of the two or more subsystems, the memory bandwidth corresponding to a maximum data access rate associated with a memory; (¶0043, 0047-0051, 0125-0126, 0161, 0169, 0191-0192; FIG. 1, 2).
limiting access to the memory by a first subsystem to a first portion of the memory bandwidth when the first subsystem is configured for a first context (partition ID); limiting access to the memory by the first subsystem to a second portion of the memory bandwidth when the first subsystem is configured for a second context; and enforcing memory bandwidth limitations defined for the first subsystem based on context in which the first subsystem is operated (see at least ¶0049-0051, 0063-0064, 0125-0128, 0157-0161; FIG. 2, 12, 16).
Krueger further discloses (¶0150-0154, 0157, 0165, 0170-0171) the memory bandwidth limitations are specified in reconfigurable registers but does not explicitly disclose redefining the memory bandwidth limitations when changes in memory bandwidth usage are indicated by measurements of the data access rate associated with the memory, wherein the memory bandwidth limitations are redefined by reconfiguring registers in a resource management subsystem.
Yi, however, discloses (pg. 199, Abstract; pg. 202, § 3.1; pg. 203-204, § 3.3; pg. 205, § 3.3.2; pg. 209, col. 1) an analogous system and methods of limiting access to memory bandwidth by different application thread Throttling Groups (“TGroups”) (contexts) including operations to redefining the memory bandwidth limitations (dynamically throttle memory request rate) when changes in memory bandwidth usage are indicated by measurements of the data access rate associated with the memory (e.g. occurrence of excessive memory contention/interference; memory traffic) including using Intel Memory Bandwidth Allocation (MBA) hardware regulation mechanism (the resource management subsystem) (pg. 202, col. 1; pg. 206, col. 1; pg. 202-203, § 3.2) including defining/updating throttle values and TGroup bandwidth allocations via control Model Specific Registers (MSR)2 of the MBA HW (redefined by reconfiguring registers in the resource management subsystem). Exemplary quotations:
“MT2 adopts a dynamic bandwidth throttling algorithm that constantly monitors and adjusts restrictions based on the real-time bandwidth and the interference level (§ 3.1)...Monitoring the bandwidth information is the first step towards bandwidth regulation. The following step is to restrict the bandwidth a TGroup can occupy, which is handled by the regulator. The regulator takes the interference level and the monitored bandwidth as the input and decides what actions to take to adjust the bandwidth of the TGroup according to the regulation policy (§ 3.3)…The MBA hardware supports ten MBA throttling values...To set up the MT2 context for each thread, including setting the PMU related context, writing the MSR registers related to MBA” (pg. 206, col. 1).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Krueger to employ the dynamic bandwidth regulation of Yi’s MT2 because “Evaluation shows that MT2 can effectively regulate the bandwidth among applications with nearly zero performance overhead and can be used in multiple use cases” and to avoid wasting utilization of memory hardware when shared memory interference of competing applications is low.
Claim 10:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses wherein the first context corresponds to a first use case (operating state and/or application thereof) and the second context corresponds to a second use case (¶0048, 0060, 0063-0064, 0185).
Claim 12:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses configuring a hypervisor to provide virtualized contexts in which virtual machines are operated, wherein the first context comprises a first virtualized context and the second context comprises a second virtualized context (¶0048, 0060, FIG. 4 and 5).
Claim 13:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses wherein a first bandwidth monitor (set of control register parameters) configured to limit access to the memory by the first subsystem when the first subsystem is configured for the first context, and a second bandwidth monitor configured to limit access to the memory by the first subsystem when the first subsystem is configured for the second context (¶0125-0128, 0157, 0169-0171).
Claim 16:
Krueger discloses the limitations as shown in the following rejections:
An apparatus comprising: means (memory system component) for enforcing memory bandwidth limitations on a plurality of subsystems (processing units/elements), each of the plurality of subsystems being operable in two or more contexts (partitions/software execution environments/operating state), each context being associated with a memory bandwidth allocation (see at least ¶0043, 0047-0051, 0063-0064, 0125-0128, 0157-0161; FIG. 1, 2, 12, 16).
means for providing virtualized contexts in which one or more of the plurality of subsystems are operated (¶0048, 0060, FIG. 4 and 5).
means for measuring data access rates associated with the memory (¶0041-0044, 0055)
Krueger further discloses (¶0150-0154, 0157, 0165, 0170-0171) the memory bandwidth limitations are specified in reconfigurable registers but does not explicitly disclose redefine the memory bandwidth limitations when the means for measuring data access rates indicates changes in memory bandwidth usage and wherein the memory bandwidth limitations are redefined by reconfiguring registers maintained by the means for enforcing memory bandwidth limitations.
Yi, however, discloses (pg. 199, Abstract; pg. 202, § 3.1; pg. 203-204, § 3.3; pg. 205, § 3.3.2; pg. 209, col. 1) an analogous system and methods of limiting access to memory bandwidth by different application thread Throttling Groups (“TGroups”) (contexts) including operations to redefine the memory bandwidth limitations (dynamically throttle memory request rate) when the means for measuring data access rates indicates changes in memory bandwidth usage (e.g. occurrence of excessive memory contention/interference; memory traffic) including using Intel Memory Bandwidth Allocation (MBA) hardware regulation mechanism (the resource management subsystem) (pg. 202, col. 1; pg. 206, col. 1; pg. 202-203, § 3.2) including defining/updating throttle values and TGroup bandwidth allocations via control Model Specific Registers (MSR)3 of the MBA HW (redefined by reconfiguring registers in the resource management subsystem). Exemplary quotations:
“MT2 adopts a dynamic bandwidth throttling algorithm that constantly monitors and adjusts restrictions based on the real-time bandwidth and the interference level (§ 3.1)...Monitoring the bandwidth information is the first step towards bandwidth regulation. The following step is to restrict the bandwidth a TGroup can occupy, which is handled by the regulator. The regulator takes the interference level and the monitored bandwidth as the input and decides what actions to take to adjust the bandwidth of the TGroup (§ 3.3)…The MBA hardware supports ten MBA throttling values...To set up the MT2 context for each thread, including setting the PMU related context, writing the MSR registers related to MBA” (pg. 206, col. 1).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Krueger to employ the dynamic bandwidth regulation of Yi’s MT2 because “Evaluation shows that MT2 can effectively regulate the bandwidth among applications with nearly zero performance overhead and can be used in multiple use cases” and to avoid wasting utilization of memory hardware when shared memory interference of competing applications is low.
Claim 17:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses wherein a first subsystem operates in a first context corresponds to a first use case (operating state and/or application thereof) and in a second context that corresponds to a second use case (¶0048, 0060, 0063-0064, 0185).
Claim 18:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses wherein the means for providing the virtualized contexts comprises a hypervisor configured to support a plurality of virtual machines (¶0048, 0060, FIG. 4 and 5). Krueger further discloses a first bandwidth monitor (set of control register parameters) configured to limit access to the memory by a first subsystem when the first subsystem is configured for operation in a first virtualized context; and a second bandwidth monitor configured to limit access to the memory by the first subsystem when the first subsystem is configured for operation in a second virtualized context (¶0125-0128, 0157, 0169-0171).
Claim 21:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses wherein the means for enforcing memory bandwidth limitations comprises a dedicated processing circuit (e.g. regulator) (¶0057-0059, 0174 FIG. 6). See also Yi pg. 202, § 2.5.
Claims 3, 6, 11, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger in view of Yi in further view of Kim et al. (“Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux cgroup”, 2018).
Claims 3, 6, 11, 14, and 19:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses (¶0159-0161, 0191) a partition’s maximum bandwidth limit can be optionally unset or set to theoretical maximum capacity and accordingly operate without throttling/limitation (wherein the first portion of the memory bandwidth is unlimited). Krueger also suggests (¶0189-0190) associating limits with software execution environment priorities, but Krueger/Yi do not specifically disclose a partition being associated with a safety requirement dictating it bandwidth limit.
Kim, however, discloses (pg. 215-216) an analogous method of limiting application tasks’ (context/use case) access to memory bandwidth where a task identified as safety-critical task (associated with a safety requirement) operates without throttling/limitation (wherein the first portion of the memory bandwidth is unlimited).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Krueger/Yi to operate safety-critical tasks without throttling as taught by Kim to protect the operation of critical system functions while mitigating resource underutilization and wastage (pg. 215-216, § I).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger in view of Yi in further view of Herdrich et al. (US 2021/0117244 A1).
Claims 7 and 8:
The combination of Krueger/Yi discloses the limitations as shown in the rejections above. Krueger further discloses the memory bandwidth limitations correspond to an allocation of the memory bandwidth among the plurality of subsystems (¶0047-0051, 0125-0128, 0191-0192); see also Yi pg. 202, col. 1. Yi further discloses wherein the changes that are detected in memory bandwidth usage are indicated by measurements of the data access rate associated with the memory pg. 202-203, § 3.2. The combination of Krueger/Yi does not specifically disclose wherein the bandwidth monitoring subsystem is controlled using a Finite State Machine.
Herdrich, however, discloses (¶0102) an analogous “Memory Bandwidth Monitoring (MBM)” (bandwidth monitoring subsystem) that is controlled by a resource manager implemented as a Finite State Machine.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify Krueger/Yi’s Memory Bandwidth Monitoring to be controlled using a FSM as taught by Herdich as it represents the simple selection from finite number of well known controller models with predictable results (“Resource manager can be implemented as a microcontroller, state machine, core that executes a process, fixed function device (e.g., field programmable gate array), and so forth.” (¶0102).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
“Introduction to Memory Bandwidth Allocation” and “Intel Memory Bandwidth Allocation (MBA) Feature” provide further description of the Intel Memory Bandwidth Allocation (MBA) feature, referenced as evidence of inherency in the rejections above.
US 20220197819 A1 and 20230137769 A1 discloses memory bandwidth allocation regulators.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry of a general nature or relating to the status of this application or concerning this communication or earlier communications from the Examiner should be directed to Paul Mills whose telephone number is 571-270-5482. The Examiner can normally be reached on Monday-Friday 11:00am-8:00pm. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, April Blair can be reached at 571-270-1014.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/P. M./
Paul Mills
08/18/2026
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
1 For completeness of record, Examiner refers to “Introduction to Memory Bandwidth Allocation” and “Intel Memory Bandwidth Allocation (MBA) Feature” included with this Action for additional description of the register control interface of Intel MBA.
2 For completeness of record, Examiner refers to “Introduction to Memory Bandwidth Allocation” and “Intel Memory Bandwidth Allocation (MBA) Feature” included with this Action for additional description of the register control interface of Intel MBA.
3 For completeness of record, Examiner refers to “Introduction to Memory Bandwidth Allocation” and “Intel Memory Bandwidth Allocation (MBA) Feature” included with this Action for additional description of the register control interface of Intel MBA.
Prosecution Insights