CTNF 18/440,758 CTNF 88803 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claims 1-20 are presented for examination. Claim Objections Claim 13 is objected to because of the following informality. The term “non-hose” is used. The examiner is assuming “non-host” is meant instead. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1,2,4,5,10,11,13,14 and 19 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Drysdale (US 2018/0095750 A1) As per claim 1, Drysdale teaches A computer-implemented method, comprising: receiving, by a first non-host processing device of a computer system from a host processing device of the computer system, configuration information for configuring the first non-host processing device to execute a first execution flow; (Drysdale [0039] The context pointer may point to the control and/or configuration information for the job specific operation to be performed on a specific device. This context pointer may be provided during initialization (e.g., of a device) by the processor (e.g., CPU) along with channel information and setup for communication between devices. In certain embodiments, once this is done, the processor (e.g., CPU) has no involvement with data passing between the devices. Memory buffers for communication between devices may be configured (e.g., allocated) by the processor (e.g., CPU) when the channel is initialized.) receiving, by the first non-host processing device, first computer code for execution by the first non-host processing device; (Drysdale [0042] A processor 300 (e.g., core 306) may receive a request (e.g., from software) to perform an operation and may offload (e.g., at least part of) the operation (e.g., thread) to a hardware accelerator (e.g., accelerator 302) [0043] In one embodiment, a hardware accelerator is in processor 300. Hardware accelerator (e.g., each hardware accelerator) may be coupled to (e.g., its own or a shared) input buffer and/or output buffer, e.g., to receive a stream of input data [code for execution] to operate on to produce output data and [0045] In one embodiment, a processor (e.g., core) is to write the descriptors and/or transmit a new LastValidIn (e.g., in a command packet) then (e.g., by executing an ENQ operation) transmit that data (e.g., in the command packet) to accelerator(s).) receiving, by the first non-host processing device, a first trigger to execute at least a first portion of the first computer code; executing, by the first non-host processing device and in response to the first trigger, the at least a first portion of the first computer code; (Drysdale [0046] In one embodiment, when accelerator 0 receives input data from the processor (e.g., CPU) (e.g., or other device) it is to begin processing when it has both input buffers and output buffers available [trigger]. In one embodiment, once accelerator 0 fills an output buffer (e.g., or encounters some other signal on the input indicating that it should transmit current completed data) it may mark the buffer as full/complete and send a command packet to accelerator 1 indicating that a buffer is ready for processing in the circular buffer descriptor array see also Fig 2A (Processed Data 0 out Data (1) sent to hardware accelerator 2)) writing, by the first non-host processing device and based at least in part on the execution of the at least a first portion of the first computer code, first data to a destination buffer of a second non-host processing device; (Drysdale 0093] FIG. 6 illustrates a flow diagram 600 of an acceleration operation according to embodiments of the disclosure. Depicted flow 600 includes offloading an operation from a hardware processor to a first hardware accelerator 602; and executing the operation on the first hardware accelerator and a second hardware accelerator to generate output data and consume input data, wherein the first hardware accelerator and the second hardware accelerator are coupled to a plurality of shared buffers to store the output data from the first hardware accelerator and provide the output data as the input data to the second hardware accelerato r, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer…..) sending, by the first non-host processing device and in response to writing the first data to the destination buffer of the second non-host processing device, a second trigger to the second non-host processing device to cause the second non-host processing device to execute second computer code. (Drysdale Fig 2A and 2B and [0037] The specifics of what is to be performed by the next device may be provided with a Job Context Pointer (Ptr) that is (e.g., only) meaningful to the receiving device, for example, that allows the receiving device to determine what to do with the data. In one embodiment, the Job Context Pointer is setup at initialization time when the channel is configured. Certain embodiments herein utilize an encode command (e.g., command packet) operation (e.g., ENQ) or other mechanism) to provide the transport mechanism. In one embodiment, the use of ENQ further allows multiple submitters to one accelerator port. For example, in FIG. 2B, an encode signal (e.g., command) [trigger] may be sent from accelerator 202 to accelerator 204 (e.g., to indicate that output data generated by accelerator 202 is ready to be inputted into or processed on by accelerator 204) and/or may be sent from accelerator 204 to accelerator 202 (e.g., to indicate that accelerator 204 has processed the data from accelerator 202 and is ready for more input data from accelerator 202 see paragraph 94 for further details about use if indices in communication among accelerators). As per claim 2, Drysdale teaches the at least a first portion of the first computer code is an initial portion of the first computer code; (Drysdale [0106] Certain embodiments herein provide for a novel techniques to improve the interaction between hardware accelerators, for example, for improved performance. In one embodiment, a call for an operation (e.g., to perform compression and/or decompression) by an accelerator is not considered a mere request to the accelerator to perform the operation. Instead in this embodiment, an initial request [initial portion of code] may set up the context for the operation (e.g., the compression and/or decompression job). The input buffers may be submitted to a per-context queue of buffers. The output buffers may be submitted to a per-context queue of buffers. In one embodiment, there is no (e.g., strict) correlation between the input and output buffers) Initial portion is not defined . The examiner will treat this under broadest reasonable interpretation to be any portion that is run before another. the first trigger is received by the first non-host processing device from the host processing device. ( Drysdale [0046] In one embodiment, when accelerator 0 receives input data from the processor (e.g., CPU) (e.g., or other device) it is to begin processing when it has both input buffers and output buffers available) As per claim 5, Drysdale teaches the second non-host processing device and the third non-host processing device are a same non-host processing device. (Drysdale Fig 2B shows each accelerator using output of the other and [0037] FIGS. 2A-2B illustrate a hardware processing device 200 and hardware accelerators (202, 204) according to embodiments of the disclosure. In contrast to FIG. 1, hardware accelerators (202, 204) may pass data directly between themselves , e.g., with no intervention from hardware processing device 200. In one embodiment, the device (e.g., accelerator) job control and job specification and initialization are separated logically and physically from the communication channel interface between devices. In certain embodiments, this communication channel between devices may (e.g., only) then be used to carry information about the availability of data and data buffers to be used by the devices. This data transmission is mechanism may be defined to be the same across (e.g., all) devices. For example, in an embodiment where the data transmitted between devices is limited in scope and/or because the data transmission is common across the (e.g., all) devices using this mechanism, it relieves the device of having information about where the data is coming from or going to, e.g., only that it now has data to work on or to provide to another device. The specifics of what is to be performed by the next device may be provided with a Job Context Pointer (Ptr) that is (e.g., only) meaningful to the receiving device, for example, that allows the receiving device to determine what to do with the data. In one embodiment, the Job Context Pointer is setup at initialization time when the channel is configured. Certain embodiments herein utilize an encode command (e.g., command packet) operation (e.g., ENQ) or other mechanism) to provide the transport mechanism. In one embodiment, the use of ENQ further allows multiple submitters to one accelerator port. For example, in FIG. 2B, an encode signal (e.g., command) may be sent from accelerator 202 to accelerator 204 (e.g., to indicate that output data generated by accelerator 202 is ready to be inputted into or processed on by accelerator 204) and/or may be sent from accelerator 204 to accelerator 202 (e.g., to indicate that accelerator 204 has processed the data from accelerator 202 and is ready for more input data from accelerator 202)) As to claims 5, 13 and 14, they are rejected based on the same reason as claim 4. As to claim 11, it is rejected based on the same reason as claim 2. As to claims 10 and 19, they are rejected based on the same reason as claim 1. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Drysdale (US 2018/0095750 A1) in view of Jo (US 2024/0303138 A1) . As per claim 3, Drysdale does not teach wherein the first trigger is received by the first non-host processing device from another non-host processing device. However, Jo teaches wherein the first trigger is received by the first non-host processing device from another non-host processing device. (Jo [0111] A first command for transmitting result data (Act 1) output from the second primitive operation 824 to the second accelerator (GPU 1) may be inserted into the second sub call list 830. Additionally or alternatively, a second command for receiving result data (Act 1) of the second primitive operation 824 from the first accelerator (GPU 0) may be inserted into the second sub call list 830. The inserting the command and dividing the primitive operation described above may be performed by one or more processors included in the information processing system. [0134] Based on the inserted command, the first accelerator (GPU 0) may receive a calculation result of the first primitive operation 1032 included in the second sub call list 1030 from the second accelerator (GPU 1). In addition, the first accelerator (GPU 0) may calculate the final calculation result (Act 0) of the first primitive operation 1012 based on the partial calculation result of the first primitive operation 1022 included in the first sub call list 1020 and the partial calculation result of the first primitive operation 1032 received from the second accelerator (GPU 1), and transmit the calculated final calculation result (Act 0) to the second accelerator (GPU 1) for sharing). It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Jo with the system of Drysdale to get a trigger from non-host device. One having ordinary skill in the art would have been motivated to use Jo into the system of Drysdale for the purpose of using primitive operations that can be parallelly executed through a plurality of accelerators. (Jo paragraph 02) As to claim 12, it is rejected based on the same reason as claim 3 . 07-21-aia AIA Claim s 6,15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Drysdale (US 2018/0095750 A1) in view of Patel (US 2023/0419166 A1) . As per claim 6, Drysdale does not teach the first non-host processing device is configured to receive multiple triggers from one or more other non-host processing devices prior to executing at least a second portion of the first computer code; and the method further comprises: receiving, by the first non-host processing device, the multiple triggers from the one or more other non-host processing devices; and executing, by the first non-host processing device in response to the multiple triggers from the one or more other non-host processing devices, the at least the second portion of the first computer code. However, Patel teaches the first non-host processing device is configured to receive multiple triggers from one or more other non-host processing devices prior to executing at least a second portion of the first computer code; and the method further comprises: receiving, by the first non-host processing device, the multiple triggers from the one or more other non-host processing devices; and executing, by the first non-host processing device in response to the multiple triggers from the one or more other non-host processing devices, the at least the second portion of the first computer code. (Patel [claim 1] A computing system comprising: one or more hardware processors; one or more hardware storage devices configured to store computer-executable instructions which are executable by the one or more hardware processors for managing a distribution of sparse and dense layers of a mixture-of-experts (MOE) model on a plurality of accelerators; a plurality of accelerators comprising a first set of accelerators and a second set of accelerators, the accelerators in the second set of accelerators having a greater memory capacity than accelerators in the first set of accelerators, and accelerators in the first set of accelerators having a greater processing capability than accelerators in the second set of accelerators; and a machine learning model comprising a plurality of dense layers and a plurality of sparse layers, the machine learning model being distributed on the plurality of accelerators such that (i) the plurality of dense layers is distributed on one or more accelerators selected from the first set of accelerators, (ii) the plurality of sparse layers is distributed on one or more accelerators selected from the second set of accelerators, and (iii) at least one accelerator storing one or more sparse layers of the machine learning model is configured to receive multiple inputs from one or more accelerators storing dense layers of the machine learning model). It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Patel with the system of Drysdale to use multiple triggers. One having ordinary skill in the art would have been motivated to use Patel into the system of Drysdale for the purpose of distributing MOE models into various system configurations. (Patel paragraph 04) As to claims 15 and 20, they are rejected based on the same reason as claim 6 . 07-21-aia AIA Claim s 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Drysdale (US 2018/0095750 A1) in view of Kodama (US 2023/0409302 Al) . As per claim 7, Drysdale does not teach at least one of the first non-host processing device or the second non-host processing device is an accelerator; at least one of the first non-host processing device or the second non-host processing device is a compute-capable storage device; or one of the first non-host processing device and second non-host processing devices is an accelerator and the other of the first non-host processing device and the second non-host processing device is a compute-capable storage device. However, Kodama teaches at least one of the first non-host processing device or the second non-host processing device is an accelerator; at least one of the first non-host processing device or the second non-host processing device is a compute-capable storage device; or one of the first non-host processing device and second non-host processing devices is an accelerator and the other of the first non-host processing device and the second non-host processing device is a compute-capable storage device. (Kodama [0056] The node 200 is a computer that executes the application in cooperation with the plurality of accelerators. The node 200 offloads the part of the process of the application to the accelerator mounted in each of the NW device 300, the storage device 400, the memory device 500, the FPGA device 600, and the GPU device 700). It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Kodama with the system of Drysdale to use an accelerator and storage device. One having ordinary skill in the art would have been motivated to use Kodama into the system of Drysdale for the purpose of selecting, based on a result of analysis of an access count from each of the plurality of program blocks to each of a plurality of accelerators. (Kodama paragraph 05) As to claim 16, it is rejected based on the same reason as claim 7 . 07-21-aia AIA Claim s 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Drysdale (US 2018/0095750 A1) in view of Lal (US 2019/0130120 A1) . As per claim 8, Drysdale does not teach wherein the configuration information comprises an assignment of a source memory buffer and a destination memory buffer. However, Lal teaches wherein the configuration information comprises an assignment of a source memory buffer and a destination memory buffer. (Lal [0072] In block 808, the TEE 302 securely configures a descriptor for the DMA transfer. The TEE 302 may, for example, perform one or more secure MMIO writes to a register, command buffer, or other address of the accelerator 136 to provide the descriptor. The descriptor includes data describing the secure DMA transaction, including a source address, a destination address, a length, and a direction of transfer. The descriptor may also include additional data, such as a last flag that instructs the accelerator 136 to raise an interrupt or otherwise notify the TEE 302 after performing the DMA transaction. In some embodiments, in block 810 the descriptor may indicate a host to accelerator 136 transfer. In those embodiments the source address may identify a host buffer in the memory 130 that includes encrypted data, and the destination address may identify an accelerator buffer in a memory of the accelerator 136. In some embodiments, in block 812 the descriptor may indicate an accelerator 136 to host transfer. In those embodiments the source address may identify an accelerator buffer in a memory of the accelerator 136, and the destination address may identify a host buffer in the memory 130) It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Lal with the system of Drysdale to use a source and destination memory. One having ordinary skill in the art would have been motivated to use Lal into the system of Drysdale for the purpose of committing the transaction that may include storing the data item in a memory of the accelerator (Lala paragraph 35) As to claim 17, it is rejected based on the same reason as claim 8 . 07-21-aia AIA Claim s 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Drysdale (US 2018/0095750 A1) in view of Kasichainula (US 2022/0414037 A1) . As per claim 9, Drysdale does not teach the configuration information comprises a termination condition for terminating, by the first non-host processing device, the first execution flow; or the method further comprises receiving, by the first non-host processing device, an interrupt from the host processing device to cause the first non-host processing device to terminate the first execution flow. However, Kasichainula teaches the configuration information comprises a termination condition for terminating, by the first non-host processing device, the first execution flow; or the method further comprises receiving, by the first non-host processing device, an interrupt from the host processing device to cause the first non-host processing device to terminate the first execution flow. (Kasichainula [0108] FIG. 10 is a flowchart representative of example machine readable instructions and/or example operations 1000 that may be executed and/or instantiated by processor circuitry to batch and moderate interrupts in a plurality of compute units. The example instructions 1000 begin at block 1002 at which the example interrupt batching and moderation circuitry 102 of FIG. 6 receives an interrupt. At block 1006, the example interrupt batching circuitry 604 of FIG. 6 determines if the interrupt can be serviced by an accelerator compute unit. For example, the interrupt batching and moderation circuitry 102 of FIG. 6 may direct the interrupt to an accelerator compute unit when a first set of CPUs are in a C-state that reduces or stops selected functions). It would have been obvious to a person in the ordinary skill in the art before the effective filing date of the claimed invention to combine Kasichainula with the system of Drysdale to issue an interrupt for termination. One having ordinary skill in the art would have been motivated to use Kasichainula into the system of Drysdale for the purpose of managing processor interrupts. (Kasichainula paragraph 01) As to claim 18, it is rejected based on the same reason as claim 9 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20170060637 A1 – discloses a data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation. US 20200167487 A1 – discloses initializing, by an accelerator device of the computing device, an authentication tag in response to an initialization command from a trusted execution environment of the computing device, initiating a transfer, by the accelerator device, of data between a host memory and an accelerator device memory in response to a descriptor from the trusted execution environment, wherein the descriptor comprises a target memory address and is indicative of a transfer direction, comparing, in a memory range selection engine comprising at least one comparator to compare the target memory address with a plurality of address ranges and select a cryptographic key from the plurality of plurality of address range registers based on the target memory address, performing, by the accelerator device, a cryptographic operation with the data in response to transferring the data, updating, by the accelerator device, the authentication tag in response to transferring the data, and finalizing, by the accelerator device, the authentication tag in response to a finalization command from the trusted execution environment. Other embodiments are described and claimed. US 20250173294 A1 – discloses interacting with an interface for one or more computational devices, wherein the interacting is based on an identifier, and wherein the identifier comprises information that identifies a functionality of a computational device function. The information may include a functionality identifier. The identifier may further include information that identifies a group of the computational device function. The group of the computational device function may be based on a source of the computational device function. The information that identifies the functionality of a computational device function may include a functionality identifier, and the information that identifies the group of the computational device function may include a group identifier. The functionality identifier may include a unique function identifier, and the group identifier may include an organizationally unique identifier. US 20190286479 A1 – discloses scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEHRAN KAMRAN whose telephone number is (571)272-3401. The examiner can normally be reached on 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEHRAN KAMRAN/ Primary Examiner, Art Unit 2196 Application/Control Number: 18/440,758 Page 2 Art Unit: 2196 Application/Control Number: 18/440,758 Page 3 Art Unit: 2196 Application/Control Number: 18/440,758 Page 4 Art Unit: 2196 Application/Control Number: 18/440,758 Page 5 Art Unit: 2196 Application/Control Number: 18/440,758 Page 6 Art Unit: 2196 Application/Control Number: 18/440,758 Page 7 Art Unit: 2196 Application/Control Number: 18/440,758 Page 8 Art Unit: 2196 Application/Control Number: 18/440,758 Page 9 Art Unit: 2196 Application/Control Number: 18/440,758 Page 10 Art Unit: 2196 Application/Control Number: 18/440,758 Page 11 Art Unit: 2196 Application/Control Number: 18/440,758 Page 12 Art Unit: 2196 Application/Control Number: 18/440,758 Page 13 Art Unit: 2196 Application/Control Number: 18/440,758 Page 14 Art Unit: 2196 Application/Control Number: 18/440,758 Page 15 Art Unit: 2196 Application/Control Number: 18/440,758 Page 16 Art Unit: 2196
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