DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/29/26 has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 8-11, 12-13, 15, 17-18, and 20-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breakstone (US 20150373115) in view of Cheng (US 20140379964).
With respect to claim 2, the Breakstone reference teaches a switch, comprising:
a plurality of ports configured to be coupled with a plurality of hosts and a plurality of physical devices, a physical device of the plurality of physical devices being a memory device; (e.g, fig. 1, and paragraph 31, where each processing module 130 communicates over one or more PCIe links 135 through PCIe switches 133 with external expansion cards or external PCIe ports; and paragraph 32, where plurality of storage sleds 110 are included in system 100. Each storage sled 110 includes one or more storage drives, such as four each shown in FIG. 3.) and
a switch fabric interconnecting the plurality of ports. (e.g. fig. 8; and paragraph 117, where table 880 can comprise a listing of various portions of a shared PCIe address space that each of the processors of system 800 handles storage operations for, such as an associated address range)
However, the Breakstone reference does not explicitly teach to have circuitry configured to use mapping information to translate first memory locations in access requests received from the plurality of hosts to second memory locations in the plurality of physical devices, the first memory locations in local address domains corresponding to the plurality of hosts, and the second memory locations in a global address domain corresponding to the plurality of physical devices.
The Cheng reference teaches it is conventional to have circuitry configured to use mapping information to translate first memory locations in access requests received from the plurality of hosts to second memory locations in the plurality of physical devices, the first memory locations in local address domains corresponding to the plurality of hosts, and the second memory locations in a global address domain corresponding to the plurality of physical devices.
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Breakstone reference to have
circuitry configured to use mapping information to translate first memory locations in access requests received from the plurality of hosts to second memory locations in the plurality of physical devices, the first memory locations in local address domains corresponding to the plurality of hosts, and the second memory locations in a global address domain corresponding to the plurality of physical devices, as taught by the Cheng reference.
The suggestion/motivation for doing so would have been to have allow multiple operations to be performed in parallel to reduce the computation time when performing random accessing to the flash memory. (paragraph 21)
Therefore it would have been obvious to combine the Breakstone and Cheng references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 3, the combination of the Breakstone and Cheng references teaches the switch of claim 2, wherein the switch is configured to receive a first access request identifying a first memory segment on a first physical device from the first host, to receive a second access request identifying a second memory segment on the first physical device from the second host, and to access the first memory segment for the first access request and the second segment memory for the second access request. (Breakstone, see fig. 8; and paragraph 100, where processing module 630 communicates with any of storage sleds 610, 615, 710, and 715 over PCIe links 654 and 655 which are switched through associated PCIe switches on associated I/O modules; and paragraph 118, where routing table 880 indicates that processor 732 manages the storage devices associated with transaction 892. Processor 632 transfers transaction 892 over at least PCIe switch 830, PCIe switch 833, and PCIe switch 831 for delivery to processor 732, as indicated by “transaction transfer 893” in FIG. 8)
With respect to claim 4, the combination of the Breakstone and Cheng references teaches the switch of claim 2, wherein the mapping information maps a particular set of memory locations in a first host to a corresponding set of corresponding memory locations in at least a first physical device and a second physical device of the plurality of physical devices. (Breakstone, see fig. 8; and paragraph 100, where processing module 630 communicates with any of storage sleds 610, 615, 710, and 715 over PCIe links 654 and 655 which are switched through associated PCIe switches on associated I/O modules; and paragraph 118, where routing table 880 indicates that processor 732 manages the storage devices associated with transaction 892. Processor 632 transfers transaction 892 over at least PCIe switch 830, PCIe switch 833, and PCIe switch 831 for delivery to processor 732, as indicated by “transaction transfer 893” in FIG. 8)
With respect to claim 8, the combination of the Breakstone and Cheng references teaches the switch of claim 2, wherein the switch is configured to allow a first host to access at least one shared memory location only if the at least one shared memory location is not attached to a second host. (Breakstone, paragraph 153, where processor 0 address space 1010 includes a miscellaneous area that includes space for lock indicators, flags, and interrupts. These interrupts can be used to signal a receiving processor that data or packets are ready for handling. The lock and flag spaces can be used for handshaking, semaphoring, or other uses during data or packet transfer between processors)
With respect to claim 9, the combination of the Breakstone and Cheng references teaches the switch of claim 2, wherein the memory mapper includes an address table configured to translate between memory locations in the plurality of hosts and corresponding memory locations in the plurality of physical devices. (Breakstone, paragraph 118, where routing table 880 indicates that processor 732 manages the storage devices associated with transaction 892. Processor 632 transfers transaction 892 over at least PCIe switch 830, PCIe switch 833, and PCIe switch 831 for delivery to processor 732, as indicated by “transaction transfer 893” in FIG. 8)
With respect to claim 10, the combination of the Breakstone and Cheng references teaches the switch of claim 2, wherein the mapping information maps a portion of the physical device to each of the plurality of hosts. (Breakstone, paragraph 104, where table 780 can include all of the various PCIe address ranges for all processors, so that when a particular processor receives a storage operation that particular processor can check the associated PCIe address against table 780 to determine if that particular processor should manage the storage operation or if the storage operation should be transferred to another of the processors for further handling)
With respect to claim 11, the combination of the Breakstone and Cheng references teaches the switch of claim 2, wherein the mapping information is received at the memory mapper from a fabric manager. (Breakstone, see fig. 8; and paragraph 117, where table 880 can comprise a listing of various portions of a shared PCIe address space that each of the processors of system 800 handles storage operations for, such as an associated address range)
With respect to claim 21, the combination of the Breakstone and Cheng references teaches the switch of claim 2, wherein the switch is configured to receive the mapping information from a device separate from the switch. (Breakstone, see fig. 1; and paragraph 43, where a particular processing system 131 manages (instantiates/binds) a subset number of the total quantity of storage sleds, such as 16 storage drives spanning 4 storage sleds, and handles transactions for that subset of storage drives, such as read and write transactions. Each processing system 131, however, has memory-mapped visibility to the storage drives managed by any other processing system 131. When a transaction is desired for a storage drive not managed by a particular processing system, the particular processing system uses the memory mapped access to all storage drives for that transaction. The transaction can be transferred and transitioned to the appropriate processing system that manages that storage drive associated with the data of the transaction)
Claims 12-13, 15, 17-18, and 22 are the method implementation of the claims noted above, and rejected under the same rationale.
Claim 20 and 23 is the system implementation of the claims noted above, and rejected under the same rationale as shown above.
Claims 5-6, 14, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breakstone in view of Cheng as shown in the rejections above, and further view of Das Sharma (US 20210240655).
With respect to claim 5, the combination of the Breakstone and Cheng references does not explicitly teach the switch of claim 2, wherein the switch is configured to receive a first request from the first host, the first request being a compute express link (CXL) request and the first host is a CXL host.
The Das Sharma reference teaches it is conventional to have wherein the switch is configured to receive a first request from the first host, the first request being a compute express link (CXL) request and the first host is a CXL host. (paragraph 52, where Compute Express Link (CXL) has been developed, providing an improved, high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation data center performance, among other application. CXL maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, among other example advantages)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Breakstone and Cheng references does not explicitly teach the switch of claim 2, wherein the switch is configured to have wherein the switch is configured to receive a first request from the first host, the first request being a compute express link (CXL) request and the first host is a CXL host, as taught by the Das Sharma reference.
The suggestion/motivation for doing so would have been to provide a standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging computing applications such as artificial intelligence, machine learning and other applications. (Das Sharma, paragraph 52)
Therefore it would have been obvious to combine the Breakstone, Cheng, and Das Sharma references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 6, the Breakstone and Cheng references does not explicitly teach the switch of claim 2, wherein the physical device is a compute express link (CXL) memory device.
The Das Sharma reference teaches it is conventional to have wherein the physical device is a compute express link (CXL) memory device. (paragraph 52, where Compute Express Link (CXL) has been developed, providing an improved, high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation data center performance, among other application. CXL maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, among other example advantages)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify combination of the Breakstone and Cheng references to have wherein the physical device is a compute express link (CXL) memory device, as taught by the Das Sharma reference.
The suggestion/motivation for doing so would have been to provide a standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging computing applications such as artificial intelligence, machine learning and other applications. (Das Sharma, paragraph 52)
Therefore it would have been obvious to combine the Breakstone, Cheng, and Das Sharma references for the benefits shown above to obtain the invention as specified in the claim.
Claims 14 and 19 are the method implementation of the claims noted above, and rejected under the same rationale.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 8-11 of the remarks) and amendments with respect to claims 2-6, 8-10, 12-15, and 17-23 have been considered, and are persuasive. The Examiner notes the inclusion of the Cheng reference to teach the newly added claim limitations as shown in the rejections above.
3. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights