DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 1/5/26, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 8-11, 12-13, 15, 17-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breakstone (US 20150373115) in view of Houssein (US 6418479).
With respect to claim 2, the Breakstone reference teaches a switch, comprising:
a plurality of ports configured to be coupled with a plurality of hosts and a plurality of physical devices, a physical device of the plurality of physical devices being a memory device; (e.g, fig. 1, and paragraph 31, where each processing module 130 communicates over one or more PCIe links 135 through PCIe switches 133 with external expansion cards or external PCIe ports; and paragraph 32, where plurality of storage sleds 110 are included in system 100. Each storage sled 110 includes one or more storage drives, such as four each shown in FIG. 3.)
a switch fabric interconnecting the plurality of ports; (e.g. fig. 8; and paragraph 117, where table 880 can comprise a listing of various portions of a shared PCIe address space that each of the processors of system 800 handles storage operations for, such as an associated address range)
wherein the switch is configured to receive mapping information from a memory mapper coupled to a port of the plurality of ports, the mapping information including at least one shared memory location on the physical device for a first host and a second host of the plurality of hosts, (see fig. 8, and paragraph 116, where processor 632 includes routing table 880 which comprises one or more data structures that indicate which particular processor of system 800 manages data for the storage address space contained within the storage sleds of system 800) the switch further being configured to allow access to the physical device, in response to at least one request. (see fig. 8, and paragraph 116, where processor 632 includes routing table 880 which comprises one or more data structures that indicate which particular processor of system 800 manages data for the storage address space contained within the storage sleds of system 800)
However, the Breakstone reference does not explicitly teach to have such that the at least one shared memory location is accessible via the switch by only one of the first host and the second host at a particular time, wherein in the event that the at least one shared memory location is being accessed by the one host at the particular time via the switch, the at least one shared memory location is not accessible by the other host at the particular time via the switch, wherein the switch is configured such that the first host and the second host transfer information through the at least one shared memory location, wherein the switch is configured to disallow the second host to access the at least one shared memory location if the at least one shared memory location is attached to the first host, wherein the first host and the second host are attached to the at least one shared memory location, wherein only one host can access the at least one shared memory location and the other host cannot access the at least one shared memory location, wherein the first host is connected to the at least one shared memory location via the switch, wherein the second host is connected to the at least one shared memory location via the switch.
The Houssein reference teaches it is conventional to have such that the at least one shared memory location is accessible via the switch by only one of the first host and the second host at a particular time, wherein in the event that the at least one shared memory location is being accessed by the one host at the particular time via the switch, the at least one shared memory location is not accessible by the other host at the particular time via the switch, (see fig. 2; and column 7, lines 9-31, where a common I/O resource is shared among multiple host nodes, the host nodes must usually control and coordinate access to each I/O device and manage data coherency among themselves. For example, resource locks can be used to provide exclusive access to the shared resource; [i.e only one host node can access the shared location at a time]) wherein the switch is configured such that the first host and the second host transfer information through the at least one shared memory location, wherein the switch is configured to disallow the second host to access the at least one shared memory location if the at least one shared memory location is attached to the first host; and wherein the first host and the second host are attached to the at least one shared memory location, wherein only one host can access the at least one shared memory location and the other host cannot access the at least one shared memory location, wherein the first host is connected to the at least one shared memory location via the switch, wherein the second host is connected to the at least one shared memory location via the switch. (see fig. 2, where hosts nodes 210 and I/O nodes are connected via a SAN [which includes a switch] to connect to the shared resource [i.e. shared memory location]; and column 2, lines 23-37, where plurality of host nodes 210 and a plurality of I/O nodes 230. Each host node 210 is connected to each I/O node 230 via a network, such as a system area network (SAN) 220. SAN 220 includes links and one or more switches for routing packets between host nodes 210 and I/O nodes 230 [and thus the “one shared memory location is not accessible by the other host at the particular time via the switch” and “wherein the switch is configured to disallow the second host to access the at least one shared memory location if the at least one shared memory location is attached to the first host” as claimed])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Breakstone reference to have teach to have such that the at least one shared memory location is accessible via the switch by only one of the first host and the second host at a particular time, wherein in the event that the at least one shared memory location is being accessed by the one host at the particular time via the switch, the at least one shared memory location is not accessible by the other host at the particular time via the switch, wherein the switch is configured such that the first host and the second host transfer information through the at least one shared memory location, wherein the switch is configured to disallow the second host to access the at least one shared memory location if the at least one shared memory location is attached to the first host, wherein the first host and the second host are attached to the at least one shared memory location, wherein only one host can access the at least one shared memory location and the other host cannot access the at least one shared memory location, wherein the first host is connected to the at least one shared memory location via the switch, wherein the second host is connected to the at least one shared memory location via the switch, as taught by the Houssein reference.
The suggestion/motivation for doing so would have been to have a common I/O resource be shared among multiple host nodes; and have the host nodes must usually control and coordinate access to each I/O device and manage data coherency among themselves. (Houssein, column 7, lines 9-31)
Therefore it would have been obvious to combine the Breakstone and Houssein references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 3, the combination of the Breakstone and Houssein references teaches the switch of claim 2, wherein the switch is configured to receive a first request identifying first memory on the physical device from the first host, to receive a second request identifying second memory on the physical device from the second host, and to access the first memory for the first request and the second memory for the second request. (Breakstone, see fig. 8; and paragraph 100, where processing module 630 communicates with any of storage sleds 610, 615, 710, and 715 over PCIe links 654 and 655 which are switched through associated PCIe switches on associated I/O modules; and paragraph 118, where routing table 880 indicates that processor 732 manages the storage devices associated with transaction 892. Processor 632 transfers transaction 892 over at least PCIe switch 830, PCIe switch 833, and PCIe switch 831 for delivery to processor 732, as indicated by “transaction transfer 893” in FIG. 8)
With respect to claim 4, the combination of the Breakstone and Houssein references teaches the switch of claim 2, wherein the mapping information received by the switch maps a particular set of memory locations in the first host to a corresponding set of corresponding memory locations in at least a first physical device and a second physical device of the plurality of physical devices. (Breakstone, see fig. 8; and paragraph 100, where processing module 630 communicates with any of storage sleds 610, 615, 710, and 715 over PCIe links 654 and 655 which are switched through associated PCIe switches on associated I/O modules; and paragraph 118, where routing table 880 indicates that processor 732 manages the storage devices associated with transaction 892. Processor 632 transfers transaction 892 over at least PCIe switch 830, PCIe switch 833, and PCIe switch 831 for delivery to processor 732, as indicated by “transaction transfer 893” in FIG. 8)
With respect to claim 8, the combination of the Breakstone and Houssein references teaches the switch of claim 2, wherein the switch is configured to allow the second host to access the at least one shared memory location only if the at least one shared memory location is not attached to the first host. (Houssein, column 6, lines 53-65, where the SBMP server 205 may be configured to grant locks on particular data blocks in the shared storage volume to only one of the first and second clients at a time responsive to lock requests from those clients. Thus, the SBMP server 205 may receive from the SBMP client 206 a lock request for a first range of data blocks in the shared storage volume of the storage array 202, and grant a lock on the first range of data blocks to the SBMP client 206 responsive to its lock request)
With respect to claim 9, the combination of the Breakstone and Houssein references teaches the switch of claim 2, wherein the memory mapper includes an address table configured to translate between memory locations in the plurality of hosts and corresponding memory locations in the plurality of physical devices. (Breakstone, paragraph 118, where routing table 880 indicates that processor 732 manages the storage devices associated with transaction 892. Processor 632 transfers transaction 892 over at least PCIe switch 830, PCIe switch 833, and PCIe switch 831 for delivery to processor 732, as indicated by “transaction transfer 893” in FIG. 8)
With respect to claim 10, the combination of the Breakstone and Houssein references teaches the switch of claim 2, wherein the mapping information maps a portion of the physical device to each of the plurality of hosts. (Breakstone, paragraph 104, where table 780 can include all of the various PCIe address ranges for all processors, so that when a particular processor receives a storage operation that particular processor can check the associated PCIe address against table 780 to determine if that particular processor should manage the storage operation or if the storage operation should be transferred to another of the processors for further handling)
With respect to claim 11, the combination of the Breakstone and Houssein references teaches the switch of claim 2, wherein the mapping information is received at the memory mapper from a fabric manager. (Breakstone, see fig. 8; and paragraph 117, where table 880 can comprise a listing of various portions of a shared PCIe address space that each of the processors of system 800 handles storage operations for, such as an associated address range)
Claims 12-13, 15, and 17-18 are the method implementation of the claims noted above, and rejected under the same rationale.
Claim 20 is the system implementation of the claims noted above, and rejected under the same rationale as shown above.
Claims 5-6, 14, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breakstone in view of Breakstone and Houssein as shown in the rejections above, and further view of Das Sharma (US 20210240655).
With respect to claim 5, the combination of the Breakstone and Houssein references does not explicitly teach the switch of claim 2, wherein the switch is configured to receive a first request from the first host, the first request being a compute express link (CXL) request and the first host is a CXL host.
The Das Sharma reference teaches it is conventional to have wherein the switch is configured to receive a first request from the first host, the first request being a compute express link (CXL) request and the first host is a CXL host. (paragraph 52, where Compute Express Link (CXL) has been developed, providing an improved, high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation data center performance, among other application. CXL maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, among other example advantages)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Breakstone and Houssein references does not explicitly teach the switch of claim 2, wherein the switch is configured to have wherein the switch is configured to receive a first request from the first host, the first request being a compute express link (CXL) request and the first host is a CXL host, as taught by the Das Sharma reference.
The suggestion/motivation for doing so would have been to provide a standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging computing applications such as artificial intelligence, machine learning and other applications. (Das Sharma, paragraph 52)
Therefore it would have been obvious to combine the Breakstone, Houssein, and Das Sharma references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 6, the Breakstone and Houssein references does not explicitly teach the switch of claim 2, wherein the physical device is a compute express link (CXL) memory device.
The Das Sharma reference teaches it is conventional to have wherein the physical device is a compute express link (CXL) memory device. (paragraph 52, where Compute Express Link (CXL) has been developed, providing an improved, high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation data center performance, among other application. CXL maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, among other example advantages)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify combination of the Breakstone and Houssein references to have wherein the physical device is a compute express link (CXL) memory device, as taught by the Das Sharma reference.
The suggestion/motivation for doing so would have been to provide a standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging computing applications such as artificial intelligence, machine learning and other applications. (Das Sharma, paragraph 52)
Therefore it would have been obvious to combine the Breakstone, Houssein, and Das Sharma references for the benefits shown above to obtain the invention as specified in the claim.
Claims 14 and 19 are the method implementation of the claims noted above, and rejected under the same rationale.
2. ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS/OBJECTIONS
Rejections - USC 112
Applicant's arguments and amendments with respect to claims 2-6, 8-15, and 17-20 have been considered, and have overcome the Examiner’s prior rejections and thus are withdrawn.
3. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's amendments and arguments with respect to claims 2-6, 8-15, and 17-20 have been considered, and not persuasive. The applicant argues that the applied references does not teach the limitations of “the first host and the second host are attached to the at least one shared memory location, wherein only one host can access the at least one shared memory location and the other host cannot access the at least one shared memory location, wherein the first host is connected to the at least one shared memory location via the switch, wherein the second host is connected to the at least one shared memory location via the switch" as recited in claims 2, 12, and 20, and the Examiner respectfully disagrees. The Houssein reference teaches (see fig. 2; and column 2, lines 23-37) that there are hosts nodes 210 and I/O nodes that are connected via a SAN [which includes a switch] to connect to the shared resource [i.e. shared memory location]; and where each host node 210 is connected to each I/O node 230 via a network, such as a system area network (SAN) 220. SAN 220 includes links and one or more switches for routing packets between host nodes 210 and I/O nodes 230. The Houssein reference also teaches (column 7, lines 9-31) that there is a a common I/O resource is shared among multiple host nodes, the host nodes must usually control and coordinate access to each I/O device and manage data coherency among themselves; and for example, resource locks can be used to provide exclusive access to the shared resource. Thus, based on the citations above, the Examiner contends the Houssein reference teaches the limitations above as broadly and instantly claimed, and the combination of the references teaches the claimed invention as shown in the rejections above.
4. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137