CTNF 18/440,991 CTNF 98266 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-4, 6-7, 9, 12 and 15-19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Jun (US 20210183816 A1) . Regarding Claim 1, Jun teaches a semiconductor chip (600, see Figs. 1-2) comprising: a main area (see annotated below); an edge area (see annotated below) that is positioned on an outer side of the main area in a first direction (D2, shown Fig. 1); main area chip pads (CP) arranged in the main area; and edge area chip pads (TP) arranged in the edge area, wherein the edge area chip pads are arranged such that first (TPb, shown Fig. 5A) and second (TPa) edge area chip pads immediately adjacent to each other in the first direction are spaced apart from each other in a direction (D1) intersecting the first direction (shown Fig. 5A). PNG image1.png 100 100 image1.png Greyscale Regarding Claim 2, Jun teaches the semiconductor chip of claim 1, wherein: the main area chip pads are arranged in a first line and a second line (shown Fig. 1); and the first line and the second line extend in the first direction (shown Fig. 1). Regarding Claim 3, Jun teaches the semiconductor chip of claim 1, further comprising a data pad area in the main area (wherein a data pad area is broadly interpreted as an area comprising pads for receiving/transmitting data, see also [0053] which discloses pads of the semiconductor chip 600 being configured to receive/transmit data, and thus a data pad area may be interpreted to be any plurality of pads within the main area). Regarding Claim 4, Jun teaches the semiconductor chip of claim 3, wherein a first end of the data pad area in the first direction is positioned at a boundary of the main area and the edge area. Regarding Claim 6, Jun teaches the semiconductor chip of claim 3, wherein at least one main area chip pad is arranged between the data pad area and a boundary of the main area and the edge area (see in example of the designated “data pad area” below). PNG image3.png 100 100 image3.png Greyscale Regarding Claim 7, Jun teaches the semiconductor chip of claim 6, wherein a distance in the first direction between the data pad area and an edge positioned on a side of the edge area opposite from the main area is 10% or more of a total length of the semiconductor chip in the first direction (wherein a data pad area may further be interpreted as two chip pads in the middle of the main area). PNG image4.png 100 100 image4.png Greyscale Regarding Claim 9, Jun teaches the semiconductor chip of claim 3, wherein a portion of the data pad area is positioned in the edge area (see embodiment of Fig. 9, which further teaches all limitations of claims 1 and 3 and shows a chip pad being partially positioned in the edge area, see also annotated below). Regarding Claim 12, Jun teaches a semiconductor chip (600, shown Fig. 1) comprising: a main area (see annotated below); a first edge area (top edge area, see annotated below) that is positioned on a first side of the main area in a first direction (D2, shown Fig. 1); and a second edge area (bottom edge area, see annotated below) that is positioned a second side of the main area that is opposite from the first side in the first direction; main area chip pads (CP) provided in the main area on a first line and a second line (interpreted as an imaginary vertical line) that extend in the first direction (shown Fig. 1); and edge area chip pads (TP) provided in first and second edge areas (shown Fig. 1), wherein the edge area chip pads are arranged such that two edge area chip pads immediately adjacent to each other in the first direction are spaced apart from each other in a second direction (D1) intersecting the first direction (see Fig. 5A). PNG image6.png 100 100 image6.png Greyscale Regarding Claim 15, Jun teaches the semiconductor chip of claim 12, wherein the edge area chip pads are alternately arranged on a third line and the first line, and are alternately arranged on a fourth line and the second line, the third and fourth lines extending in the first direction (see also annotated Fig. 9 below drawn to a separate embodiment which further teaches all limitations of claim 12). PNG image7.png 100 100 image7.png Greyscale Regarding Claim 16, Jun teaches the semiconductor chip of claim 15, wherein the third line is positioned on the opposite side of the first line with respect to the second line (see annotated above), and wherein the fourth line is positioned on the opposite side of the second line with respect to the first line (see annotated above), and wherein the first line is closer to the third line than to the second line, and the second line is closer to the fourth line than to the first line (see annotated above). Regarding Claim 17, Jun teaches the semiconductor chip of claim 16, wherein a length of a distance between the second line and the fourth line is equal to a length of a distance between the first line and the third line (see also Fig. 10, wherein each section DD shown in Fig. 9 is configured symmetrically across the device). Regarding Claim 18, Jun teaches the semiconductor chip of claim 15, wherein at least one of the third line and the fourth line is positioned between the first line and the second line (see annotated above). Regarding Claim 19, Jun teaches a semiconductor package (shown Fig. 1) comprising: a substrate (100); a semiconductor chip (600) on the substrate; and chip terminals (TSV and BP, shown Fig. 2) that couple the semiconductor chip to the substrate, wherein the semiconductor chip comprises: a main area (see annotated below); and an edge area (see annotated below) positioned on a first side of the main area in a first direction (D2); main area chip pads (CP) provided on the main area; and edge area chip pads (TP) provided on the edge area, wherein the edge area chip pads are arranged such that two edge area chip pads immediately adjacent to each other in the first direction are spaced apart from each other in a direction (D1) intersecting the first direction (see also Fig. 5A) . PNG image6.png 100 100 image6.png Greyscale Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 5, 8, 10-11, 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jun (US 20210183816 A1) . Regarding Claim 5, Jun teaches the semiconductor chip of claim 4, but is silent regarding a length of the edge area in the first direction or a total length of the semiconductor chip in the first direction. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within their technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103. See also MPEP 2144.05. More specifically to this case, Jun shows that edge pad spacing and test pad diameter (which define a dimension of the edge pad area along the first direction) are result-effective variables because it reveals that insufficient spacing may result in unreliable alignment testing (see [0066-0067]) . Furthermore, the general effort of minimizing chip size is known in the art as this allows for increased chip density. A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal edge pad spacing and test pad diameter (which further define dimensions of the edge pad area) to minimize chip footprint while ensuring reliable alignment testing. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties. As such, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application, through routine optimization, to configure a length of the edge area in the first direction to be in a range between 6% and 10%, inclusive, of a total length of the semiconductor chip in the first direction. Regarding Claim 8, Jun teaches the semiconductor chip of claim 6, but is silent regarding a length of the edge area in the first direction or a total length of the semiconductor chip in the first direction. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within their technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103. See also MPEP 2144.05. More specifically to this case, Jun shows that edge pad spacing and test pad diameter (which define a dimension of the edge pad area along the first direction) are result-effective variables because it reveals that insufficient spacing may result in unreliable alignment testing (see [0066-0067]) . Furthermore, the general effort of minimizing chip size is known in the art as this allows for increased chip density. A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal edge pad spacing and test pad diameter (which further define dimensions of the edge pad area) to minimize chip footprint while ensuring reliable alignment testing. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties. As such, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application, through routine optimization, to configure a length of the edge area in the first direction to be in a range between 9% and 10%, inclusive, of a total length of the semiconductor chip in the first direction. Regarding Claim 10, Jun teaches the semiconductor chip of claim 9, but is silent regarding a distance in the first direction between the data pad area and an edge positioned on a side of the edge area opposite from the main area. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within their technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103. See also MPEP 2144.05. More specifically to this case, Jun shows that edge pad spacing and test pad diameter (which define a dimension of the edge pad area along the first direction) are result-effective variables because it reveals that insufficient spacing may result in unreliable alignment testing (see [0066-0067]) . Furthermore, the general effort of minimizing chip size is known in the art as this allows for increased chip density. A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal edge pad spacing and test pad diameter (which further define dimensions of the edge pad area) to minimize chip footprint while ensuring reliable alignment testing. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties. As such, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application, through routine optimization, to configure a distance in the first direction between the data pad area and an edge positioned on a side of the edge area opposite from the main area is 6% or less of a total length of the semiconductor chip in the first direction. Regarding Claim 10, Jun teaches the semiconductor chip of claim 9, but is silent regarding a length of the edge area in the first direction or a total length of the semiconductor chip in the first direction. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within their technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103. See also MPEP 2144.05. More specifically to this case, Jun shows that edge pad spacing and test pad diameter (which define a dimension of the edge pad area along the first direction) are result-effective variables because it reveals that insufficient spacing may result in unreliable alignment testing (see [0066-0067]) . Furthermore, the general effort of minimizing chip size is known in the art as this allows for increased chip density. A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal edge pad spacing and test pad diameter (which further define dimensions of the edge pad area) to minimize chip footprint while ensuring reliable alignment testing. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties. As such, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application, through routine optimization, to configure a length of the edge area in the first direction to be in a range between 6% and 7%, inclusive, of a total length of the semiconductor chip in the first direction. Regarding Claim 13, Jun teaches the semiconductor chip of claim 12, but is silent regarding a length of the edge area in the first direction or a total length of the semiconductor chip in the first direction. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within their technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103. See also MPEP 2144.05. More specifically to this case, Jun shows that edge pad spacing and test pad diameter (which define a dimension of the edge pad area along the first direction) are result-effective variables because it reveals that insufficient spacing may result in unreliable alignment testing (see [0066-0067]) . Furthermore, the general effort of minimizing chip size is known in the art as this allows for increased chip density. A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal edge pad spacing and test pad diameter (which further define dimensions of the edge pad area) to minimize chip footprint while ensuring reliable alignment testing. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties. As such, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application, through routine optimization, to configure a length of the edge area in the first direction to be in a range between 6% and 10%, inclusive, of a total length of the semiconductor chip in the first direction. Regarding Claim 20, Jun teaches the semiconductor chip of claim 13, wherein the length of the second edge area in the first direction is equal the length of the first edge area in the first direction (shown Fig. 1). Regarding Claim 20, Jun teaches the semiconductor chip of claim 19, but is silent regarding a length of the edge area in the first direction or a total length of the semiconductor chip in the first direction. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within their technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103. See also MPEP 2144.05. More specifically to this case, Jun shows that edge pad spacing and test pad diameter (which define a dimension of the edge pad area along the first direction) are result-effective variables because it reveals that insufficient spacing may result in unreliable alignment testing (see [0066-0067]) . Furthermore, the general effort of minimizing chip size is known in the art as this allows for increased chip density. A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal edge pad spacing and test pad diameter (which further define dimensions of the edge pad area) to minimize chip footprint while ensuring reliable alignment testing. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties. As such, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application, through routine optimization, to configure a length of the edge area in the first direction to be in a range between 6% and 10%, inclusive, of a total length of the semiconductor chip in the first direction . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Corbett (US 20020024046 A1) teaches a semiconductor chip (10) comprising a main area and a peripheral area, wherein dimensions different edge areas are described in [0027] and a total length of a chip edge is about 0.275 inches (see [0039]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.P.B./Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/440,991 Page 2 Art Unit: 2893 Application/Control Number: 18/440,991 Page 3 Art Unit: 2893 Application/Control Number: 18/440,991 Page 4 Art Unit: 2893 Application/Control Number: 18/440,991 Page 5 Art Unit: 2893 Application/Control Number: 18/440,991 Page 6 Art Unit: 2893 Application/Control Number: 18/440,991 Page 7 Art Unit: 2893 Application/Control Number: 18/440,991 Page 8 Art Unit: 2893 Application/Control Number: 18/440,991 Page 9 Art Unit: 2893 Application/Control Number: 18/440,991 Page 10 Art Unit: 2893 Application/Control Number: 18/440,991 Page 11 Art Unit: 2893 Application/Control Number: 18/440,991 Page 12 Art Unit: 2893 Application/Control Number: 18/440,991 Page 13 Art Unit: 2893 Application/Control Number: 18/440,991 Page 14 Art Unit: 2893 Application/Control Number: 18/440,991 Page 15 Art Unit: 2893 Application/Control Number: 18/440,991 Page 16 Art Unit: 2893
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