DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 11/06/2025.
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on references such as Fujiwara et al. 20020097621 applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kim et al. 20060186446 in view of Fujiwara et al. 20020097621.
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Regarding claim 21, fig. 1 of Kim discloses a semiconductor device comprising:
a first semiconductor layer (par [0031] – 102b – first 102b from 100) provided above a substrate 100 in a first direction (Z) perpendicular to the substrate, extending in a second direction (Y – see fig. 1) parallel to the substrate, and having a first portion (as labeled by examiner above) between one end (left) of the first semiconductor layer and another end (right) of the first semiconductor layer in the second direction – see fig. 1;
a second semiconductor layer (second 102b from 100) provided above the first semiconductor layer in the first direction, extending in the second direction, and having a second portion (as labeled by examiner above) between one end of the second semiconductor layer and another end of the second semiconductor layer in the second direction;
a third semiconductor layer (third 102b from 100) provided above the second semiconductor layer in the first direction, extending in the second direction, and having a third portion (as labeled by examiner above) between one end of the third semiconductor layer and another end of the third semiconductor layer in the second direction;
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a first gate electrode 114 provided on first side surfaces of the first, second, and third semiconductor layers, provided on second side surfaces of the first, second, and third semiconductor layers, provided above the third semiconductor layer, and extending in the first direction, each of the second side surfaces opposite to a corresponding one of the first side surfaces in a third direction crossing the first and second directions;
a first contact 130 connected to the another end of the third semiconductor layer, the first contact extending in the first direction above the another end of the third semiconductor layer; and
wherein the first, second, and third semiconductor layers are electrically connected at their respective one ends (see connection to 130 at the right ends).
Kim does not disclose of an interconnection provided above the third semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction.
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However, fig. 3 of Fujiwara discloses semiconductor device comprising a semiconductor layer w (par [0099]) provided above a substrate SUB in a first direction (Z) perpendicular to the substrate, extending in a second direction (across the page) parallel to the substrate; a first contact SC connected to the semiconductor layer W, the first contact SC extending in the first direction above the semiconductor layer; and an interconnection MSL2 provided above the semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction (across the page).
Note that fig. 1 of Kim invention requires metallization layer to connect to B/L&S/D and Fujiwara teaches forming contact extending above W/L line and forming metallization to the contact and is applicable to Kim invention.
Note that Fujiwara discloses disclose MSL2 and MSL2 above the WL and Kim invention can be modified as such.
In view of such teaching, it would have been obvious to form a device of Kim further comprising an interconnection provided above the third semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction such as taught by Fujiwara in order to form interconnection to the third semiconductor layer and provide electrical current to the device.
Claim 42-45 and 47-48 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Doyle et al. 20070231997 in view of Fujiwara.
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Regarding claim 42, fig. 3 of Doyle discloses a semiconductor device comprising:
a first semiconductor layer disposed above a substrate in a first direction (Z - up and down the page), the first semiconductor layer having a first portion (bottom rectangular slap portion extending into the page as labeled by examiner above), a second portion (middle rectangular slap portion into the page as labeled by examiner above), and a third portion (top rectangular slap portion as labeled by examiner above) disposed in a second direction (Y - into the page) crossing the first direction in that sequence;
a second semiconductor layer disposed above the first semiconductor layer in the first direction, the second semiconductor layer having a fourth portion, a fifth portion, and a sixth portion disposed in the second direction in that sequence, the fifth portion disposed above the second portion in the first direction, the fifth portion separated from the second portion;
a third semiconductor layer disposed above the second semiconductor layer in the first direction, the third semiconductor layer having a seventh portion, an eighth portion, and a ninth portion disposed in the second direction in that sequence, the eighth portion disposed above the fifth portion in the first direction, the eighth portion separated from the fifth portion; and
a first gate electrode 17 including:
a first segment (as labeled by examiner above) disposed on first side surfaces of the second portion, the fifth portion, and the eighth portion,
a second segment (as labeled by examiner above) disposed on second side surfaces of the second portion, the fifth portion, and the eighth portion, each of the second side surfaces opposite to a corresponding one of the first side surfaces in a third direction (across the page) crossing the first direction and the second direction, and
a third segment coupled to the first segment and the second segment, the third segment disposed above the eighth portion of the third semiconductor layer in the first direction;
wherein the first portion, the fourth portion, and the seventh portion are electrically coupled to each other (as labeled by examiner above – electrically coupled).
Doyle does not disclose of a first contact connected to the ninth portion, the first contact extending in the first direction; and an interconnection provided above the eighth portion in the first direction, electrically connected to the first contact, and extending in the second direction.
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However, fig. 3 of Fujiwara discloses semiconductor device comprising a semiconductor layer w (par [0099]) provided above a substrate SUB in a first direction (Z) perpendicular to the substrate, extending in a second direction (across the page) parallel to the substrate; a first contact SC connected to the semiconductor layer W, the first contact SC extending in the first direction above the semiconductor layer; and an interconnection MSL2 provided above the semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction (across the page).
Note that fig. 1 of Kim invention requires metallization layer to connect to B/L&S/D and Fujiwara teaches forming contact extending above W/L line and forming metallization to the contact and is applicable to Kim invention.
In view of such teaching, it would have been obvious to form a device of Kim further comprising an interconnection provided above the third semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction such as taught by Fujiwara in order to form interconnection to the third semiconductor layer and provide electrical current to the device.
Regarding claim 43, Doyle discloses claim 42, but does not disclose of further comprising: a first contact connected to the third portion, the first contact extending in the first direction above the ninth portion in the first direction.
However, figs. 3 of Fujiwara discloses further comprising: a first contact BC connected to the semiconductor layer W, the first contact extending in the first direction above the semiconductor layer W in the first direction.
In view of such teaching, it would have been obvious to form a device of Doyle of further comprising: a first contact connected to the third portion, the first contact extending in the first direction above the ninth portion in the first direction such as taught by Fujiwara in order to electrically connecting a metal layer with the source/drain formed in the semiconductor layer.
Regarding claim 44, Doyle discloses wherein the first semiconductor layer includes a surface having a curvature in the third direction.
Regarding claim 47, Doyle discloses further comprising: a first memory cell (transistor is type of a memory cell) provided at an intersection between the first gate electrode and the second portion.
Regarding claims 45 and 48, Doyle does not disclose wherein a first dimension of the first semiconductor layer in the third direction is larger than a second dimension of the first semiconductor layer in the first direction; wherein a first width of the first semiconductor layer in the second direction is larger than a second width of the second semiconductor layer in the second direction.
Note that In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a device of Doyle comprising wherein a first dimension of the first semiconductor layer in the third direction is larger than a second dimension of the first semiconductor layer in the first direction; wherein a first width of the first semiconductor layer in the second direction is larger than a second width of the second semiconductor layer in the second direction in order to meet the applicant design for desired current flow.
Claims 21-25, 28, 32, 34-41, 43-44 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Doyle in view of Fujiwara.
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Regarding claim 21, fig. 3 of Doyle discloses a semiconductor device comprising:
a first semiconductor layer (as labeled by examiner above) provided above a substrate 11 in a first direction (up and down the page) perpendicular to the substrate, extending in a second direction (into the page) parallel to the substrate, and having a first portion (portion between 17) between one end (front end) of the first semiconductor layer and another end (back end) of the first semiconductor layer in the second direction;
a second semiconductor layer (as labeled by examiner above) provided above the first semiconductor layer in the first direction, extending in the second direction, and having a second portion (portion between 17) between one end (front end) of the second semiconductor layer and another end (back end) of the second semiconductor layer in the second direction;
a third semiconductor layer (as labeled by examiner above) provided above the second semiconductor layer in the first direction, extending in the second direction, and having a third portion between one end (front end) of the third semiconductor layer and another end (back end) of the third semiconductor layer in the second direction;
a first gate electrode 17 provided on first side (left side) surfaces of the first, second, and third semiconductor layers, provided on second side (right side) surfaces of the first, second, and third semiconductor layers, provided above the third semiconductor layer, and extending in the first direction, each of the second side surfaces opposite to a corresponding one of the first side surfaces in a third direction (across the page) crossing the first and second directions,
wherein the first, second, and third semiconductor layers are electrically connected at their respective one ends.
Doyle does not disclose of a first contact connected to the another end of the third semiconductor layer, the first contact extending in the first direction above the another end of the third semiconductor layer, an interconnection provided above the third semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction.
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However, fig. 3 of Fujiwara discloses semiconductor device comprising a semiconductor layer w (par [0099]) provided above a substrate SUB in a first direction (Z) perpendicular to the substrate, extending in a second direction (across the page) parallel to the substrate; a first contact SC connected to the semiconductor layer W, the first contact SC extending in the first direction above the semiconductor layer; and an interconnection MSL2 provided above the semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction (across the page).
Note that fig. 1 of Kim invention requires metallization layer to connect to B/L&S/D and Fujiwara teaches forming contact extending above W/L line and forming metallization to the contact and is applicable to Kim invention.
In view of such teaching, it would have been obvious to form a device of Kim further comprising an interconnection provided above the third semiconductor layer in the first direction, electrically connected to the first contact, and extending in the second direction such as taught by Fujiwara in order to form interconnection to the third semiconductor layer and provide electrical current to the device.
Regarding claim 22, Doyle and Fujiwara do not discloses of further comprising: a fourth semiconductor layer provided above the substrate in the first direction, arranged with the first semiconductor layer in the third direction, and extending in the second direction; a fifth semiconductor layer provided above the fourth semiconductor layer in the first direction and extending in the second direction; and a sixth semiconductor layer provided above the fifth semiconductor layer in the first direction and extending in the second direction.
However, Doyle of par [0044] discloses that referring to FIG. 3, in some embodiments, a MBT-FET 30 may be fabricated to have a tall fin with more than one neck, each neck located at a different height of the fin. The multiple-neck structure may provide the drive current of several MBT-FETs 10 to drive a large load. Although only three necks (31, 33, and 35) are shown, it is understood that any number of the necks may be formed to provide a desired drive current.
As such it would have been obvious to form a device of Doyle and Fujiwara further comprising: a fourth semiconductor layer provided above the substrate in the first direction, arranged with the first semiconductor layer in the third direction, and extending in the second direction; a fifth semiconductor layer provided above the fourth semiconductor layer in the first direction and extending in the second direction; and a sixth semiconductor layer provided above the fifth semiconductor layer in the first direction and extending in the second direction in order to provide a desired drive current.
Regarding claim 23, the resulting structure would have been one comprising wherein the first gate electrode is provided on third side surfaces of the fourth, fifth, and sixth semiconductor layers.
Regarding claim 24, the resulting structure would have been one comprising wherein the first gate electrode is provided above the sixth semiconductor layer.
Regarding claim 25, Doyle and Fujiwara do not discloses further comprising: a seventh semiconductor layer provided above the substrate in the first direction, arranged with the fourth semiconductor layer in the third direction, and extending in the second direction; an eighth semiconductor layer provided above the seventh semiconductor layer in the first direction and extending in the second direction; and a ninth semiconductor layer provided above the eighth semiconductor layer in the first direction and extending in the second direction.
However, Doyle of par [0044] discloses that referring to FIG. 3, in some embodiments, a MBT-FET 30 may be fabricated to have a tall fin with more than one neck, each neck located at a different height of the fin. The multiple-neck structure may provide the drive current of several MBT-FETs 10 to drive a large load. Although only three necks (31, 33, and 35) are shown, it is understood that any number of the necks may be formed to provide a desired drive current.
As such it would have been obvious to form a device of Doyle and Fujiwara further comprising: a seventh semiconductor layer provided above the substrate in the first direction, arranged with the fourth semiconductor layer in the third direction, and extending in the second direction; an eighth semiconductor layer provided above the seventh semiconductor layer in the first direction and extending in the second direction; and a ninth semiconductor layer provided above the eighth semiconductor layer in the first direction and extending in the second direction in order to provide a desired drive current,
Regarding claim 28, fig. 3 of Doyle discloses further comprising: a first insulating layer 15 provided between the first semiconductor layer and the substrate.
Regarding claim 32, fig. 3 of Doyle discloses further comprising: a transistor provided above the substrate.
Regarding claim 34, Doyle discloses further comprising: a second insulating layer 16 provided between the first semiconductor layer and the second semiconductor layer.
Regarding claim 35, fig. 3 of Doyle discloses further comprising: a first memory cell (the first semiconductor layer and the gate form a transistor which is forms a memory cell) provided at an intersection between the first gate electrode and the first semiconductor layer.
Regarding claim 36, fig. 3 of Doyle discloses wherein the first gate electrode covers a stack including the first, second, and third semiconductor layers stacked in the first direction.
Regarding claim 37, base on Fujiwara teaching of forming a contact, it would have been obvious to form a device of Doyle further comprising further comprising: a second contact electrically connected to the one ends of the first, second, and third semiconductor layers and extending in the first direction such as taught by Fujiwara in order to electrically connecting a metal layer with the source.
Regarding claim 38, the resulting structure would have been one wherein the second contact is electrically connected to the first side surfaces of the first, second, and third semiconductor layers.
Regarding claim 39, fig. 3 of Doyle discloses wherein the first semiconductor layer includes a surface having a curvature in the third direction.
Regarding claims 40-41, Doyle and Fujiwara do not disclose wherein a first dimension of the first semiconductor layer in the third direction is larger than a second dimension of the first semiconductor layer in the first direction; wherein a first width of the first semiconductor layer in the second direction is larger than a second width of the second semiconductor layer in the second direction.
Note that In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a device of Doyle and Fujiwara comprising wherein a first dimension of the first semiconductor layer in the third direction is larger than a second dimension of the first semiconductor layer in the first direction; wherein a first width of the first semiconductor layer in the second direction is larger than a second width of the second semiconductor layer in the second direction in order to meet the applicant design for desired current flow.
Claim 29 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Doyle and Fujiwara in view of Dakshina-Murthy 6864164 (Murthy).
Regarding claim 29, Doyle and Fujiwara disclose claim 21, but does not disclose wherein each of the first, second, and third semiconductor layers includes an epitaxial layer.
However, col. 4, ln51-58 of Murthy discloses that a narrow fin channel may be defined through the use of lateral epitaxy. In conventional FinFETs, fin width is typically defined by conventional etching processes that are difficult to control. Use of lateral epitaxy for fin formation, in accordance with this exemplary embodiment of the invention, improves control of FinFET fin width.
In view of such teaching, it would have been obvious to form a device of Doyle and Fujiwara comprising wherein each of the first, second, and third semiconductor layers includes an epitaxial layer such as taught by Murthy in order to have improvement of control of FinFET fin width.
Claim 46 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Doyle and Fujiwara in view of Murthy.
Regarding claim 46, Doyle and Fujiwara discloses claim 42, but does not disclose wherein each of the first, second, and third semiconductor layers includes an epitaxial layer.
However, col. 4, ln51-58 of Murthy discloses that a narrow fin channel may be defined through the use of lateral epitaxy. In conventional FinFETs, fin width is typically defined by conventional etching processes that are difficult to control. Use of lateral epitaxy for fin formation, in accordance with this exemplary embodiment of the invention, improves control of FinFET fin width.
In view of such teaching, it would have been obvious to form a device of Doyle and Fujiwara comprising wherein each of the first, second, and third semiconductor layers includes an epitaxial layer such as taught by Murthy in order to have improvement of control of FinFET fin width.
Claims 30-31 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Doyle and Fujiwara in view of Hsu et al. 20070230247.
Regarding claims 30-31, Doyle and Fujiwara disclose claim 21, but do not discloses further comprising: a second gate electrode provided on the first side surfaces of the first, second, and third semiconductor layers, provided on the second side surfaces of the first, second, and third semiconductor layers, provided above the third semiconductor layer, arranged with the first gate electrode in the second direction, and extending in the first direction; a third gate electrode provided on the first side surfaces of the first, second, and third semiconductor layers, provided on the second side surfaces of the first, second, and third semiconductor layers, provided above the third semiconductor layer, arranged with the second gate electrode in the second direction, and extending in the first direction.
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However, figs. 1A-1B of Hsu discloses a first gate 170 and a second gate 171 provided on a first side surface of a fin 180 in order to form multiple devices on the fin. Note forming multiple gates as taught by Hsu can be incorporated into Doyle’s device for the benefit of forming multiple devices.
In view of such teaching, it would have been obvious to form a device of Doyle and Fujiwara further comprising: a second gate electrode provided on the first side surfaces of the first, second, and third semiconductor layers, provided on the second side surfaces of the first, second, and third semiconductor layers, provided above the third semiconductor layer, arranged with the first gate electrode in the second direction, and extending in the first direction; a third gate electrode provided on the first side surfaces of the first, second, and third semiconductor layers, provided on the second side surfaces of the first, second, and third semiconductor layers, provided above the third semiconductor layer, arranged with the second gate electrode in the second direction, and extending in the first direction in order to form multiple devices such as taught by Hsu.
Claims 33 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Doyle and Fujiwara in view of Kang et al. 20050255656.
Regarding claim 33, Doyle and Fujiwara disclose claim 21, but does not disclose wherein the substrate includes a first region having the first gate electrode and a second region having a transistor, the transistor provided above the substrate, the first region being higher than the second region in the first direction.
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However, fig. 19 Kang discloses a device wherein a substrate includes a first region (region of 175) having the first gate electrode 195a and a second region having a transistor (region of 110), the transistor provided above the substrate, the first region being higher than the second region in the first direction.
In view of such teaching, it would have been obvious to form a device of Doyle and Fujiwara comprising wherein the substrate includes a first region having the first gate electrode and a second region having a transistor, the transistor provided above the substrate, the first region being higher than the second region in the first direction in order to form a stack device such as taught by Kang.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893