DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 4 and 17 are objected to because of the following informalities:
Claims 4 and 17 recite “1h-time”. However, this terms should be clarified. Appropriate correction is required.
Election/Restrictions
Applicant’s election without traverse of the species election requirement in the reply filed on 01/28/26 is acknowledged.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: a first conversion unit, second conversion unit and processing unit in claims 1-3 and 5-16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-10, 12-15, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US2019/0130210).
Regarding claim 1, Lee discloses an image processor, comprising:
a first conversion unit sequentially scanning input pixel data, storing the pixel data for each line, and outputting an M*N kernel matrix through the stored pixel data, M and N being integers greater than or equal to 2 ([0004; 0093-0095; 0105; 0153]: pipeline of pixel values are received row-by-row in raster scan order; See also pixel kernel 120/406/506 in Fig. 1b; 4-5);
an image processing circuit image-processing pixel data corresponding to the M*N kernel matrix on a processing unit basis (Fig. 1a and 2: See one of processing module 1-k or 206-214 corresponding to pixel kernel 120/406/506 in Fig. 1b; 4-5 with single, plurality or different color channels; [0004]); and
a second conversion unit reordering a result of the image-processing by the image processing circuit to correspond to a format of pixel data input to the first conversion unit and outputting the reordered result (Fig. 1a and 2: See one of other processing module 1-k or 206-214; [0127; 0167]: Lee teaches two different output order “when a row of pixel values have been determined then all of the processed pixel values in that row could be outputted together” and “the method could wait until all of the pixel values within an image have been processed before any of them are outputted).
Regarding claim 2, Lee discloses the image processor as claimed in claim 1, wherein the first conversion unit includes M line memories corresponding to a number of rows of the kernel matrix ([0004; 0090-0096; 0153]: See number of line store modules /banks).
Regarding claim 3, Lee discloses the image processor as claimed in claim 1, wherein: the first conversion unit simultaneously receives CH pieces of pixel data per cycle, and CH satisfies 2^n, and n is an integer greater than or equal to 1 ([0095-0096]: multiple lines of pixel values may be passed to image processing 204 at one or simultaneously thus 2^1 satisfies 2^n).
Regarding claim 5, Lee discloses the image processor as claimed in claim 1, wherein the second conversion unit includes a number of line memories corresponding to a row direction of the processing unit 1 ([0095-0096]: multiple lines of pixel values may be passed to image processing 204 at one or simultaneously. Lee also lines of pixels values, rows or equivalent columns of pixel that can be passed to processing 204).
Regarding claim 6, Lee discloses the image processor as claimed in claim 3, wherein the second conversion unit simultaneously outputs the CH pieces of pixel data per cycle ([0127; 0167]).
Regarding claim 7, the claim contains the same limitation as claimed in claim 1. Therefore, claim 7 is analyzed and rejected as claim 1. However, claim 7 further requires: “ An image processing device, comprising: an image sensor including a plurality of pixels and a color filter array on the plurality of pixels” ([0093; 0107]).
Regarding claim 8, Lee discloses the image processing device as claimed in claim 7, wherein: the color filter array includes pixels provided in units of Uy*Ux in each color unit, and Ux is an integer greater than or equal to 1, and Uy is an integer greater than or equal to 2 ([0093; 0107; 0141]: see single, plurality or different RGB color channels).
Regarding claim 9, Lee discloses the image processing device as claimed in claim 8, wherein: the first conversion unit simultaneously receives the input pixel data in the form of 1*CH, and CH satisfies 2^n, and n is an integer greater than or equal to 1 ([0095-0096]: multiple lines of pixel values may be passed to image processing 204 at one or simultaneously thus 2^1 satisfies 2^n).
Regarding claim 10, Lee discloses the image processing device as claimed in claim 9, wherein the first conversion unit: includes M line memories corresponding to a number of rows of the kernel matrix, and stores the input pixel data for each line in the M line memories ([0004; 0090-0096; 0153]: See number of line store modules /banks).
Regarding claim 12, Lee discloses the image processing device as claimed in claim 9, wherein the second conversion unit includes Uy line memories ([0004; 0090-0096; 0153]: See number of line store modules /banks).
Regarding claim 13, Lee discloses the image processing device as claimed in claim 12, wherein the second conversion unit: reorders the pixel data included in the Uy line memories, and sequentially outputs the pixel data in the form of 1*CH (Fig. 1a and 2: See one of other processing module 1-k or 206-214; [0127; 0167]: Lee teaches two different output order “when a row of pixel values have been determined then all of the processed pixel values in that row could be outputted together” and “the method could wait until all of the pixel values within an image have been processed before any of them are outputted).
Regarding claim 14, Lee discloses an image processing method, comprising: sequentially receiving, per cycle, CH pieces of pixel data output from an image sensor ([0004; 0093-0095; 0105; 0153]: pipeline of pixel values are received row-by-row in raster scan order; See also pixel kernel 120/406/506 in Fig. 1b; 4-5), and storing the pixel data in first to Mth line memories for each line ([0004; 0090-0096; 0153]: See number of line store modules /banks);
outputting the pixel data stored in the first line memory to the Mth line memory ([0004; 0090-0096; 0153]: See number of line store modules /banks that stored pixels corresponding to pixel kernel 120/406/506 in Fig. 1b; 4-5), in the form of an M*N kernel matrix ([0093; 0107; 0141]: see single, plurality or different RGB color channels);
setting a processing unit (Fig. 1b-2: 204), and
image-processing pixel data corresponding to the M*N kernel matrix using the processing unit (Fig. 1a and 2: See one of processing module 1-k or 206-214 corresponding to pixel kernel 120/406/506 in Fig. 1b; 4-5; [0004]); and
reordering the image-processed data, wherein CH satisfies 2^n, n is an integer greater than or equal to 1 (Fig. 1a and 2: See one of other processing module 1-k or 206-214; [0127; 0167]: Lee teaches two different output order “when a row of pixel values have been determined then all of the processed pixel values in that row could be outputted together” and “the method could wait until all of the pixel values within an image have been processed before any of them are outputted) , and M and N are integers greater than or equal to 2 ([0093; 0107; 0141]: see pixel kernel 120/406/506 in Fig. 1b; 4-5).
Regarding claim 15, Lee discloses the image processing method as claimed in claim 14, wherein the processing unit (204) is determined by a unit of pixels included in each one color unit of a color filter array of the image sensor (abstract).
Regarding claim 18, Lee discloses the image processing method as claimed in claim 16, wherein the reordering of the image-processed data includes storing the image-processed data line by line using line memories of the number corresponding to Uy ([0004; 0090-0096; 0153]: See number of line store modules /banks).
Regarding claim 19, Lee discloses the image processing method as claimed in claim 18, wherein the reordering of the image-processed data includes outputting data for each line when all data is stored in the line memories of the number corresponding to Uy ([0004; 0090-0096; 0153]: See number of line store modules /banks).
Regarding claim 20, Lee discloses the image processing method as claimed in claim 19, wherein the reordering of the image-processed data includes outputting data in units of CH pieces ([0127; 0167]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Stohr (US9886635).
Regarding claim 4, Lee fails to disclose the image processor as claimed in claim 1 further in combination with: “wherein the image processing circuit performs image processing by an area corresponding to half of the line per 1h-time”.
In an analogous of art, Stohr discloses an image processor performs the ½ scaling on the pixels forming the region of interest (ROI) by a vector method and shifts the pixels one by one in the left or right direction in each row or the upper or lower direction in each column until the straight line in one direction appears in the ½ scaled region of interest (ROI) (claims 7-8). In light of the teaching from Stohr, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to performs pixel shift and the ½ scaling on the pixels of Stohr. The modifications thus provide an image processor to performs the ½ scaling on the pixels forming the region of interest (Stohr: Abstract; claims 7-8).
Regarding claim 17, Lee fails to disclose the image processing method as claimed in claim 14 further in combination with: “wherein the image-processing includes performing image processing by an area corresponding to a half area of the line for 1h-time”.
In an analogous of art, Stohr discloses an image processor performs the ½ scaling on the pixels forming the region of interest (ROI) by a vector method and shifts the pixels one by one in the left or right direction in each row or the upper or lower direction in each column until the straight line in one direction appears in the ½ scaled region of interest (ROI) (claims 7-8). In light of the teaching from Stohr, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to performs pixel shift and the ½ scaling on the pixels of Stohr. The modifications thus provide an image processor to performs the ½ scaling on the pixels forming the region of interest (Stohr: Abstract; claims 7-8).
Allowable Subject Matter
Claims 11 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art of Lee discloses a processing module configured to: receive a plurality of pixel values, each of the received pixel values having a first number of bits; and implement processing of a particular pixel value. The prior art of Stohr (US9886635) discloses a processor to performs pixel shift and the ½ scaling on the pixels or region of interest. The prior art of Guo (US9508118) discloses methods for determining an image deforming area, where the image deforming area consists of a contracted sub-area and a stretched sub-area. The prior art of Singh (US10157454) discloses a first circuit configured to (i) receive an image in a raster order, where the image has a plurality of data values arranged in a plurality of raster lines. The prior art of Ruggiero (US7869666) discloses an image processing system and method, in which a plurality of image processing operations are dynamically controlled based on dynamically changing tag data associated with pixels being processed. The prior art of Fainstain (US2008/0158396) discloses a method for enhancing an image read from an image sensor in the digital domain includes analyzing a row or a column of the image. Thus, while many references teach camera systems having plurality of image processing modules to process images captured from an image sensor, none of the references alone or in combination, provide a motivation to teach the image processing device as claimed in claim 9 further in combination with: “wherein the processing unit is Uy * (CH / Ux)”.
Regarding claim 16, the prior art of Lee discloses a processing module configured to: receive a plurality of pixel values, each of the received pixel values having a first number of bits; and implement processing of a particular pixel value. The prior art of Stohr (US9886635) discloses a processor to performs pixel shift and the ½ scaling on the pixels or region of interest. The prior art of Guo (US9508118) discloses methods for determining an image deforming area, where the image deforming area consists of a contracted sub-area and a stretched sub-area. The prior art of Singh (US10157454) discloses a first circuit configured to (i) receive an image in a raster order, where the image has a plurality of data values arranged in a plurality of raster lines. The prior art of Ruggiero (US7869666) discloses an image processing system and method, in which a plurality of image processing operations are dynamically controlled based on dynamically changing tag data associated with pixels being processed. The prior art of Fainstain (US2008/0158396) discloses a method for enhancing an image read from an image sensor in the digital domain includes analyzing a row or a column of the image. Thus, while many references teach camera systems having plurality of image processing modules to process images captured from an image sensor, none of the references alone or in combination, provide a motivation to teach the image processing method as claimed in claim 15 further in combination with: “the unit of pixels included in the one color unit is Uy*Ux, the processing unit is Uy * (CH / Ux), and Ux is an integer greater than or equal to 1, and Uy is an integer greater than or equal to 2”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG H LAM whose telephone number is (571)272-7367. The examiner can normally be reached 9AM-5PM.
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/HUNG H LAM/Primary Examiner, Art Unit 2639 05/01/26
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