Prosecution Insights
Last updated: October 26, 2026
Application No. 18/441,291

DOHERTY AMPLIFIER CIRCUIT

Final Rejection §102
Filed
Feb 14, 2024
Priority
Oct 13, 2021 — JP 2021-168430 +1 more
Examiner
NGUYEN, HIEU P
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
2 (Final)
92%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1151 granted / 1250 resolved
+32.1% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
20 currently pending
Career history
1277
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
55.6%
+15.6% vs TC avg
§102
28.3%
-11.7% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1250 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 8-9 and 11are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lehtola (U.S. 2021/003661). Regarding claim 1, Lehtola (hereinafter, Ref~661) discloses (please see Figs. 1-5 and related text for details) a Doherty amplifier circuit (e.g., see 120 of Fig. 5) comprising: a carrier amplifier (centered by transistor 37a of Fig. 5) configured to amplify a first input high frequency signal (disposed at base of transistor 37a of Fig. 5); a peak amplifier (centered by transistor 37b of Fig. 5) configured to amplify a second input high frequency signal (disposed at base of transistor 37b of Fig. 5); a first bias circuit (25a of Fig. 5) configured to apply (via resistor 27a of Fig. 5) a first bias to the carrier amplifier; a second bias circuit (25b of Fig. 5) configured to apply (via resistor 27b of Fig. 5) a second bias to the peak amplifier; and a control circuit (113 of Fig. 5 can be read as the claimed circuit) configured to control the second bias circuit on the basis of an input high frequency signal (disposed at base of the detection transistor of 113 of Fig. 5) and a signal (disposed at collector the detection transistor of 113 of Fig. 5) indicating a drive level of the carrier amplifier, meeting claim 1. Regarding claim 2, Ref~661 supports the claimed “wherein the control circuit is configured to: control the second bias circuit such that the second bias circuit increases a bias current applied to the peak amplifier as the drive level increases, and control the second bias circuit such that the second bias circuit increases the bias current applied to the peak amplifier as power of an input high frequency signal increases as described, for instance, in paragraph [0018], since it is configured to adjust a bias of the peaking amplification stage, meeting claim 2. Regarding claim 8, Ref~661 supports the claimed “wherein the signal indicating the drive level of the carrier amplifier is output from the first bias circuit”, since said control circuit 113 is coupled (via resistor 27a of Fig. 5) to said first bias circuit as shown, meeting claim 8. Regarding claim 9, Ref~661 supports the claimed “wherein the control circuit further comprises a drive level detection circuit configured to output the signal indicating the drive level of the carrier amplifier on the basis of a high frequency signal output from the carrier amplifier”, since detection transistor can be read as the claimed circuit as it is configured detect the saturation level of said carrier amplifier as describe throughout the disclosure, meeting claim 9. Regarding claim 11, Ref~661 discloses the system with multiple-stages as shown in Fig. 11, thus supporting the claimed “…further comprising: a plurality of peak amplifiers that are connected in multiple stages; and a plurality of second bias circuits that are configured to apply biases to the plurality of peak amplifiers, wherein the control circuit is configured to control at least one of the plurality of second bias circuits to apply a bias to an initial-stage peak amplifier among the plurality of peak amplifiers and to control another of the plurality of second bias circuits to apply a bias to a final-stage peak amplifier among the plurality of peak amplifiers”, meeting claim 11. Allowable Subject Matter Claims 3-7 are allowed. Claims 10 and 12-13 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims. Response to Arguments Applicants’ argument filed 08/28/2026 has been fully considered but they are NOT persuasive. Applicant states that Lehtola does NOT teach “a control circuit configured to control the second bias circuit on the basis of an input high frequency signal and a signal indicating a drive level of the carrier amplifier”. However, the Examiner disagrees with the arguments due to the above broadly claimed limitations. Specifically, at collector terminal of the detection/carrier-replica transistor 113 of Fig. 5, there would be an amplified signal having both components/signals, namely a high frequency/RF component and/or DC component/signal provided to the collector by a power source, and said amplified signal would be considered as a replica/indicating drive level of the carrier amplifier 37a of Fig. 5. Conclusion THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Feb 14, 2024
Application Filed
May 29, 2026
Non-Final Rejection mailed — §102
Aug 28, 2026
Response Filed
Oct 09, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.2%)
1y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1250 resolved cases by this examiner. Grant probability derived from career allowance rate.

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