Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/18/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“an input interface for receiving data to be encoded; a data segmentation unit configured to segment the received data ….; a level hypervector selection unit configured to select, …; a permutation unit configured to apply permutation operations ….; a binary operation unit configured to perform a binary operation …; and an aggregation unit configured to aggregate ….”
in claim 17.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 12-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication NO. 20220374234 “Imani” and further in light of U.S. Patent NO. 11227656 “Karunaratne”.
Claim 1:
Imani teaches a method for encoding within a hyperdimensional computing framework, comprising: obtaining data to be encoded (i.e. para. [0009], This disclosure proposes StocHD, a novel end-to-end hyperdimensional system that supports accurate, efficient, and robust learning over raw data); segmenting the obtained data into a plurality of windows, wherein each window of the plurality of windows comprises a sequence of data elements (i.e. para. [0050], “FIG. 2 illustrates expansion of HDC functionality using stochastic arithmetic operations according to embodiments described herein. The solution proposed herein (referred to as StocHD) expands HDC functionality to the computing area, defining stochastic arithmetic operations over HDC vectors.”, wherein the raw data in segmented into plurality of features. Wherein the BRI for a plurality of windows encompasses that a window may be a sequence of features, wherein a sequence of features may have StocHD applied to generate a hyperdimensional vector for the sequence of features) ; for each window of the plurality of windows: for each data element within a particular window, selecting a (i.e. para. [0055], “ In HDC, the hypervectors are compositional—they enable computation in superposition, unlike standard neural representations. These HDC operations facilitate reasoning about and searching through input data that satisfy prespecified constraints”, wherein a hyperdimension vector is generated that represents the values of the features),
for each selected (i.e. para. [0089], “ StocHD supports permutation and row-parallel XOR operation over the high-dimensional features”, wherein it noted that a permutation operation is applied to the hypervectors. ) based on a sequential position of a corresponding data element within the window, wherein the applying results in a set of permuted level hypervectors for the particular window (i.e. para. [0089], “For example, in case of n extracted features,
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,StocHD encodes the information by:
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, where ρ.sup.n denotes n-bit rotational shift”, wherein it is noted that the degree of rotational shift applied to each features hypervector is determined by the sequential position within the feature chain. Wherein the final feature f.sub.n is permuted by an (n-1) -bt shift as show by (p.sup.n-1)),
performing a binary operation on the set of permuted (i.e. para. [0089], “StocHD supports permutation and row-parallel XOR operation over the high-dimensional features”, wherein it is noted that a (*) bitwise XOR operation may be performed on the permuted hypervectors) to generate a window hypervector that represents the sequence of data elements for that particular window (i.e. para. [0055], “ HDC encoding works based on a set of defined primitives. The goal is to exploit the same primitives to define stochastic computing-based arithmetic operations over HDC vectors. HDC is an algebraic structure; it uses search along with several key operations (and their inverses): Bundling (+) that acts as memorization during hypervector addition, Binding (*) that associates multiple hypervectors, and Permutation (ρ) which preserves the position by performing a single rotational shift”, wherein the position-specific rotational shift ensures that the order of the features is preserved. Wherein the BRI for a window hypervector encompasses the encoded query with a binary HDC class hypervector); and
aggregating the window hypervectors for each window of the plurality of windows to generate an encoded hypervector, wherein the encoded hypervector is representative of obtained data in a hyperdimensional vector space (i.e. para. [0057], “Given n numbers {a.sub.1, a.sub.2, . . . , a.sub.n} and their corresponding probability values, {p.sub.1, p.sub.2, p.sub.n−1} ∈ [0,1], where p.sub.n is defined by Σ.sub.i=1.sup.n p.sub.i=1, the probabilistic merging chooses the number a.sub.i with probability p.sub.i. This operation can be extended to operate n hypervectors, where each dimension of merged hypervector is selected by probabilistic merging of n elements located in the same dimension of given input hypervectors.”, wherein the finished query hypervectors may be merged to represent the obtained data within a hyperdimensional vector space).
While Imani teaches selecting a hypervector to represent raw data values belonging to a sequenced window of features and subsequently applying permutation and bitwise operations to the now high-dimensional features in order to preserve the representative positions in order improve the computational efficiency when performing feature extraction and encoding, Imani may not explicitly teach
for each data element within a particular window, selecting a level hypervector from a set of level hypervectors, wherein each level hypervector of the set of level hypervectors represents a quantized value of the respective data element in high- dimensional space.
However, Karunaratne teaches
for each data element within a particular window, selecting a level hypervector from a set of level hypervectors (i.e. Col. 1, lines 53-55, “the basis hypervectors have a dimension D and the memory crossbar array comprises D resistive devices per row. D is an integer. According to such an embodiment the basis hypervectors may be stored row by row in an efficient manner”, wherein the BRI for selecting a level hypervector encompasses selecting an appropriate basis hypervector to for each input channel data element) , wherein each level hypervector of the set of level hypervectors represents a quantized value of the respective data element in high- dimensional space (i.e. Col. 2, lines 18-23, The device is configured to generate the basis hypervectors by providing for each of the input channels a channel identity hypervector by providing for each of the plurality of signal quantization levels a signal level hypervectors).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add for each data element within a particular window, selecting a level hypervector from a set of level hypervectors, wherein each level hypervector of the set of level hypervectors represents a quantized value of the respective data element in high- dimensional space, with the specific permutation and bitwise operations of hypervectors of Imani, with how basis hypervectors are selected to represent data in a high-dimensional space. It is noted that Karunaratne further teaches that such basis hypervectors undergo a permutation operation in Col. 10, lines 39-45 in order to achieve temporally encoded hypervectors. One would have been motivated to combine the hypervector representation of Karunaratne with permutation and bitwise operations to achieve a high dimensional representation of a temporal sequence of raw data of Imani and would have had a reasonable expectation of success as the combination results in significant power and/or speed advantages compared to conventional von-Neumann approaches.
Claim 2:
Imani and Karunaratne teach the method of Claim 1.
Imani further teaches wherein the obtained data comprises at least one of textual data, image data, voice data, or sensor data (i.e. para. [0050], This framework translates all data points to hyperdimensional space, enabling both feature extraction and learning to be performed using uniform data representation. For example, convolution or histogram of gradient (HOG) are commonly used feature extractors for image data. StocHD exploits HDC arithmetic to revisit the feature extractor algorithm to high-dimensional space).
Claim 3:
Imani and Karunaratne teach the method of Claim 1.
wherein the binary operation executed on the set of permuted level hypervectors is at least one of a AND, OR, XOR, NAND, NOR, or XNOR operation (i.e. para. [0089], Next, StocHD supports permutation and row-parallel XOR operation over the high-dimensional features).
Claim 4:
Imani and Karunaratne teach the method of Claim 1.
wherein the permutation operation applied to each selected level hypervector is based on a predetermined number of positions reflective of an order of the sequence of data elements within the particular window (i.e. para. [0089], “For example, in case of n extracted features,
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,StocHD encodes the information by:
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, where ρ.sup.n denotes n-bit rotational shift”, wherein it is noted that the degree of rotational shift applied to each features hypervector is determined by the sequential position within the feature chain. Wherein the window that is a group of features would be represented in sequence and that groups of windows may be merged continuously).
Claim 5:
Imani and Karunaratne teach the method of Claim 1.
Karunaratne wherein the set of level hypervectors is predefined, each representing a distinct quantized value corresponding to possible values of data elements (i.e. Col. 2, lines 18-23, “The device is configured to generate the basis hypervectors by providing for each of the input channels a channel identity hypervector by providing for each of the plurality of signal quantization levels a signal level hypervectors…
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In the above formula BH.sub.m,l are the basis hypervectors, ID.sub.m are the channel identity hypervectors, SL.sub.l are the signal level hypervectors, M is the total number of input channels and L is the total number of signal quantization levels in the quantitative data signals. The symbol * represents a binding operation).
Claim 6:
Imani and Karunaratne teach the method of Claim 1.
Karunaratne further comprising associating each window hypervector with a unique identifier hypervector through a binary operation to incorporate global sequence information into the encoding (i.e. Col. 6, lines 56-60, The device 100 provides for each of the input channels 101 a channel identity hypervector ID.sub.m. Furthermore, the device provides 100 for each of the plurality of signal quantization levels a signal level hypervector SL.sub.l).
Claim 7:
Imani and Karunaratne teach the method of Claim 6.
Karunaratne further teaches wherein decoding the encoded hypervector includes utilizing the unique identifier hypervector to reconstruct the sequence of data elements from the encoded hypervector based on the global sequence information encoded by the unique identifiers (i.e. Col. 7, lines 59-65, The decoded row addresses correspond to the basis-hypervectors of the respective quantitative data signals 10. More particularly, the circular buffer 150 decodes the row address of the row line 113 which stores the basis hypervector BH.sub.m,l which corresponds to the respective signal quantization level and the input channel of the respective input signal).
Claim 8:
Imani and Karunaratne teach the method of Claim 1.
Imani further teaches wherein aggregating the window hypervectors includes a weighted aggregation based on a predetermined importance criterion assigned to each window (i.e. para. [0057], “Given n numbers {a.sub.1, a.sub.2, . . . , a.sub.n} and their corresponding probability values, {p.sub.1, p.sub.2, p.sub.n−1} ∈ [0,1], where p.sub.n is defined by Σ.sub.i=1.sup.n p.sub.i=1, the probabilistic merging chooses the number a.sub.i with probability p.sub.i. This operation can be extended to operate n hypervectors, where each dimension of merged hypervector is selected by probabilistic merging of n elements located in the same dimension of given input hypervectors.”, wherein the BRI for a weighted aggregation based on a predetermined importance criterion encompasses a sequence based importance, such that the merged n elements are located in the same dimension as the given input hypervectors).
Claim 9:
Imani and Karunaratne teach the method of Claim 1,.
Imani teaches further comprising normalizing the encoded hypervector to obtain a uniform vector magnitude across different instances of encoded data (i.e. para. [0055-0056, 0059], “In HDC, the hypervectors are compositional—they enable computation in superposition… A random hypervector is generated with elements ±1 such that +1 appears with probability p. This facilitates constructing HDC representations of arbitrary numbers via a D dimensional vector. … StocHD defines weighted accumulation over hypervectors… This can be extended to probabilistic merging of n HDC vectors
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and n-1 probabilities p.sub.1, p.sub.2, . . . , p.sub.n−1”, wherein the accumulation is effectively normalized to obtain a uniform vector magnitude results in the uniform superposition value of ±1 dimensional vector magnitude across the different input data).
Claim 12:
Claim 12 is system claim reciting similar limitations to claim 1 and is rejected for similar reasons.
Imani further teaches
An ASIC accelerator system for hyperdimensional computing (HDC) encoding (i.e. para. [0104], the processing device 1302, which may be a microprocessor, field programmable gate array (FPGA), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device)
Claim 13:
Imani and Karunaratne teach the system of Claim 12.
Karunaratne teaches further comprising a memory module communicatively coupled to the processor, wherein the memory module stores the set of level hypervectors (i.e. Col. 1, lines 53-55, the basis hypervectors have a dimension D and the memory crossbar array comprises D resistive devices per row. D is an integer. According to such an embodiment the basis hypervectors may be stored row by row in an efficient manner).
Claim 14:
Claim 14 is the system claim reciting similar limitations to Claim 1 and is rejected for similar reasons.
Claim 15:
Claim 15 is the system claim reciting similar limitations to Claim 2 and is rejected for similar reasons.
Claim 16:
Claim 16 is the system claim reciting similar limitations to Claim 3 and is rejected for similar reasons.
Claim 17:
Claim 17 is the system claim reciting similar limitations to Claim 1 and is rejected for similar reasons.
Imani further teaches
An ASIC accelerator system for hyperdimensional computing (HDC) encoding (i.e. para. [0104], the processing device 1302, which may be a microprocessor, field programmable gate array (FPGA), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device)
Claim 18:
Imani and Karunaratne teach the system of Claim 17.
Karunaratne teaches further comprising: an output interface configured to output the encoded hypervector (i.e. Col. 8, lines 9-12, he circular buffer 150 further comprises an output interface 302 having a single output 302 configured to provide sequentially a single output signal for decoding a respective row address of the memory crossbar array 110); a level hypervector memory for storing the set of level hypervectors (i.e. Col. 1, lines 53-55, the basis hypervectors have a dimension D and the memory crossbar array comprises D resistive devices per row. D is an integer. According to such an embodiment the basis hypervectors may be stored row by row in an efficient manner); and an identifier hypervector memory for storing identifier hypervectors used in associating window hypervectors with unique identifiers (i.e. Col. 2, lines 18-23, The device is configured to generate the basis hypervectors by providing for each of the input channels a channel identity hypervector by providing for each of the plurality of signal quantization levels a signal level hypervectors”, a unique channel identity hypervector serves as the unique identifier that identifies the temporal sequence of the windows)
Claim 19:
Imani and Karunaratne teach the system of Claim 17.
Imani further teaches wherein at least one of the data segmentation unit, the level hypervector selection unit, the permutation unit, the binary operation unit, or the aggregation unit is implemented by at least one processor configured to execute instructions for performing respective functions of that unit (i.e. para. [0104], “the processing device 1302 may be a microprocessor, or may be any conventional processor, controller, microcontroller, or state machine. The processing device 1302 may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration)”, wherein the program code for the units causes the associated processing device to carry out the steps necessary to implement the functions described herein).
Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication NO. 20220374234 “Imani”, in light of U.S. Patent NO. 11227656 “Karunaratne”, and further in light of Rachkovskij, D. A., & Kleyko, D. (2022). Recursive Binding for Similarity-Preserving Hypervector Representations of Sequences (2201.11691v2). arXiv. https://arxiv.org/abs/2201.11691v2, hereinafter “Rachkovskij”.
Claim 10:
Imani and Karunaratne teach the method of Claim 1.
Imani and Karunaratne may not explicitly teach
wherein adjacent windows of the plurality of windows have a shared subset of data elements at their interface so as to define an overlap of one or more final data elements from a first window and one or more beginning data elements of a subsequent window.
However, Rachkovskij teaches
wherein adjacent windows of the plurality of windows have a shared subset of data elements at their interface so as to define an overlap of one or more final data elements from a first window and one or more beginning data elements of a subsequent window (i.e. pg. 3. Section 2) Similarity:, “Let us consider HVs: ai = eai+eai+1+···+ eai+R−1 and ai+j = eai+j +eai+j+1 +···+eai+j+R−1. For |j| < R, ai and ai+j have R−|j| coinciding atomic HVs. For example, for j > 0 these are atomic HVs with indices from i +j to i+R−1 (the last atomic HVs from ai and the first atomic HVs from ai+j; for j < 0, the opposite is true). For |j| ≥ R, ai and ai+j have no coinciding atomic HVs. This is reflected in the value of the similarity measure between ai and ai+j when it is calculated based on the dot product”, wherein the BRI for an overlap encompasses having the first atomic HVs of a.sub.i+j have a similarity measure with the last atomic HVs of a.sub.i)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add wherein adjacent windows of the plurality of windows have a shared subset of data elements at their interface so as to define an overlap of one or more final data elements from a first window and one or more beginning data elements of a subsequent window, to the specific permutation and bitwise operations of hypervectors of Imani-Karunaratne, with the generating coinciding atomic hypervectors within a similarity radius of Rachkovskij. One would have been motivated to combine specific method of generating overlapping hypervectors of Rachkovskij with permutation operation of Imani-Karunaratne and would have had a reasonable expectation of success as the combination encodes a sequential proximity as adjacent steps will share matching bit values as the advantage of forming similarity-preserving HVs of sequences is that such representations can possibly be used with a plethora of methods from statistical learning, linear algebra, and computer science that were developed specifically for vectors (Rachkovskij, pg. 1. Introduction).
Claim 20:
Claim 20 is the system claim reciting similar limitations to Claim 10 and is rejected for similar reasons.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication NO. 20220374234 “Imani”, in light of U.S. Patent NO. 11227656 “Karunaratne”, and further in light of Šverko, Z., Vrankic, M., Vlahinić, S., & Rogelj, P. (2022). Dynamic Connectivity Analysis Using Adaptive Window Size. Sensors, 22(14), 5162. https://doi.org/10.3390/s22145162, hereinafter “Sverko”.
Claim 11:
Imani, Karunaratne, and Rachkovskij teach the method of Claim 10.
While Rachkovskij teaches finding a similarity measure that represents overlapping HV values between consecutive hypervectors, Imani, Karunaratne, and Rachkovskij may not explicitly teach
wherein a size of an overlapping portion between consecutive windows is adjusted according to a predetermined criterion related to sequential dependencies inherent in the obtained data.
However, Sverko teaches
wherein a size of an (i.e. pg. 1, Abstract, “The proposed RICI-imCPCC method (relative intersection of confidence intervals for the imaginary component of the complex Pearson correlation coefficient) is based on an adaptive window size… The proposed method overcomes these shortcomings by dynamically adjusting the window width using the RICI rule, which is based on the statistical properties of the area around the observed sample”, wherein the dynamic expansion and contraction of the window is based on the statistic RICI rule) related to sequential dependencies inherent in the obtained data (i.e. pg. 15-16, 4. Discussion and Conclusion, “With RICI-imCPCC and the ability to independently define the window width according to the statistical features of the phase angle difference between the two observed signals, we can precisely define the required window width for imCPCC estimation using the observed sample, which makes a precise estimate of synchronization or changes in information flow between the observed electrodes or brain regions smoother… RICI-imCPCC provides estimation results with high accuracy and good temporal resolution”, wherein the BRI for sequential dependencies inherent in the obtained data encompasses any data properties related to maintaining the temporal resolution)/
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to add wherein a size of an overlapping portion between consecutive windows is adjusted according to a predetermined criterion related to sequential dependencies inherent in the obtained data, to generation of an overlapping hypervector portions of Imani-Karunaratne-Rachkovskij, with the how the size of a sliding window that contains a specific number of samples is dynamically controlled by statistical properties inherent to the input data, as described by Sverko. One would have been motivated to combine the dynamic sliding windows of Sverko with generation of overlap of consecutive hypervectors of Imani-Karunaratne-Rachkovskij and would have had a reasonable expectation of success as the combination fixes the issue of a constant sliding window analysis method with a narrow window size, RICI-imCPCC is not affected by the noise… RICI-imCPCC provides estimation results with high accuracy and good temporal resolution (Sverko, pg. 16, 4. Discussion and Conclusions).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication NO. 20210064432 “BENMAKRELOUF”, teaches in para. [0009], Genetic Algorithm (GA) is used to dynamically determine an optimal size of a sliding window and an optimal number of predicted data within the real-time prediction of the resource demand. The data within the real-time prediction of the resource demand is adjusted based on an estimated probability of prediction errors and a variable padding, which is based on a mean of at least one previous standard deviation of the predicted data within the real-time prediction of the resource demand.
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/D.T./Examiner, Art Unit 2145
/CESAR B PAULA/Supervisory Patent Examiner, Art Unit 2145
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