DETAILED ACTION
This application is responsive to the following: the amendments and arguments made in amendment filed on December 18, 2025.
Claims 1-20 remain pending. Claims 1, 12, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on December 18, 2025 are entered. Claims 1-20 remain pending. The amendment to the specification over comes the objection set forth in the previous office action.
Claim Objections
Applicant is advised that should claims 12 be found allowable, claims 1 and 2 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-11, 12-14, and 16-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al (US 20240194274).
Regarding Independent Claim 1, Choi teaches an operating method of a nonvolatile memory device (Fig. 1: 100) including a plurality of cell strings (Fig. 2: CS11-CS42), each cell string of the plurality of cell strings including a plurality of memory cells (Fig. 2: MC1-6), connected between a bit line (Fig. 2: BL1-BL2) and a common source line (Fig. 2: CSL), and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method comprising:
applying a word line voltage to the plurality of word lines (Fig. 2: WL1-WL6);
classifying the plurality of word lines into a plurality of regions (Fig. 5: 1st area, 2nd Area, 3rd Area), each region of the plurality of regions including at least one of the word lines (Fig. 5; WL); and
recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions (Fig. 6: s640).
Regarding Claim 2, Choi teaches the limitations of Claim 1. Choi Further teaches wherein the classifying of the plurality of word lines comprises:
classifying the word lines in the central region of the plurality of regions into a first region (Fig. 5. 1st Area);
classifying word lines above the first region into a second region (Fig. 5. 2nd Area); and
classifying word lines below the first region into a third region (Fig. 5. 3rd Area).
Regarding Claim 3, Choi teaches the limitations of Claim 2. Choi further teaches wherein the recovering the voltages of the plurality of word lines comprises:
recovering voltages of word lines in the second region and the third region after a delayed amount of time while voltages of word lines in the first region are recovered (Fig. 7: s740).
Regarding Claim 4, Choi teaches the limitations of Claim 2. Choi further teaches wherein the recovering the voltages of the plurality of word lines comprises:
recovering voltages of the word lines in the first region (Fig. 7: s710); and
recovering voltages of the word lines in the second region and the third region (Fig. 7: s740).
Regarding Claim 5, Choi teaches the limitations of Claim 4. Choi Further teaches wherein the recovering the voltages of the plurality of word lines comprises:
simultaneously recovering the voltages of the word lines in the second region and third region (Fig. 7: s740).
Regarding Claim 7, Choi teaches the limitation of Claim 1. Choi further teaches wherein the plurality of cell strings are in rows and columns on the substrate (para 26 “the memory block BLKi may include a plurality of cell strings CS11 to CS41 and CS12 to CS42. The plurality of cell strings CS11 to CS41 and CS12 to CS42 may be arranged in row and column directions to form rows and columns.”),
string select transistors (Fig. 2: SST) of cell strings (Fig. 2: CS11-CS42) in one row are commonly connected to a string select line (Fig. 2: SS1-4),
ground select transistors (Fig. 2: GST) of cell strings of two or more rows are commonly connected to a ground select line (Fig. 2: GSL1-4), and
memory cells (Fig. 2: MC1-6) of the plurality of cell strings (Fig. 2: CS11-CS42) at the same height from the substrate are commonly connected to one of the plurality of word lines (Fig. 2: WL1-6).
Regarding Claim 8, Choi teaches the limitation of Claim 7. Choi teaches further recovering a voltage of the string select line and a voltage of the ground select line (Fig. 7: s740; Fig. 2: 2nd area and 3rd include SSL and GSL respectively. Thus, those lines are recovered as well).
Regarding Claim 9, Choi teaches the limitation of Claim 8. Choi further teaches: wherein the recovering the voltage of the string select line and the voltage of the ground select line comprises:
simultaneously recovering the voltage of the string select line and the voltage of the ground select (Fig. 7: s740).
Regarding Claim 10, Choi teaches the limitation of Claim 1. Choi further teaches, wherein the plurality of regions include a different number of word lines (Fig. 2 shows the 1st, and 3rd regions with 5 word lines and the second region with 4 word lines).
Regarding Claim 11, Choi teaches the limitations of Claim 1. Choi further teaches recovering the voltages of the plurality of word lines using a power supply voltage.
It is understood that the voltage generator (Fig. 1: 6) used in Choi to generate voltages for various operations would generate the voltages using a power supply. Thus, all operations are understood to use the power supply including the recovery operation. (para 24 “The voltage generator 6 may generate voltages (for example, a program voltage, a read voltage, an erase voltage, and so on) required for internal operation of the memory cell array 1 under control by the control circuit 7.”)
Regarding Independent Claim 12, Choi teaches an operating method of a nonvolatile memory device (Fig. 1: 100) including a plurality of cell strings (Fig. 2: CS11-CS42), each cell string of the plurality of cell strings including a plurality of memory cells (Fig. 2: MC1-6), connected between a bit line (Fig. 2: BL1-BL2) and a common source line (Fig. 2: CSL), and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method comprising:
applying a word line voltage to the plurality of word lines (Fig. 2: WL1-WL6);
classifying word lines in a central region among the plurality of word lines into a first region (Fig. 6: s610);
classifying word lines above the first region into a second region (Fig. 6: s620);
classifying word lines below the first region into a third region (Fig. 6: s630); and
recovering voltages of the plurality of word lines by recovering voltages of the word lines in the first region are before recovering voltages of word lines in the second region and the third region (Fig. 6: s640).
Regarding Claim 13, Choi teaches the limitation of Claim 12. Claim 13 is rejected for the same reasons as Claim 3.
Regarding Claim 14, Choi teaches the limitation of Claim 12. Claim 14 is rejected for the same reasons as Claim 4.
Regarding Independent Claim 18, Choi teaches a nonvolatile memory device (Fig. 1: 100) comprising:
a memory cell array (Fig. 1: 1) including
a plurality of memory blocks (Fig. 1: 1, BLK0-n), each memory block of the plurality of memory blocks including a plurality of cell strings (Fig. 2: CS11-CS42), each cell string of the plurality of cell strings including a plurality of memory cells (Fig. 2: MC1-6) connected in series and penetrating at least one string select line (Fig. 2: SSL1-4),
a plurality of word lines (Fig. 2: WL1-6), and
at least one ground select line (Fig. 2: GSL1-4) having a plate form and stacked on a substrate;
an address decoder (Fig. 1: 3) configured to
select a memory block (Fig. 1: 1, BLK0-n) of the plurality of memory blocks, and
provide driving voltages (Fig. 1: 6) to the at least one string select line, the plurality of word lines, and a ground select line of the selected memory block; and a control logic configured to
control the address decoder (Fig. 1: 3) during a program operation and a read operation,
classify the plurality of word lines into a plurality of regions (Fig. 6: s610-s630), and
sequentially recover voltages of word lines in a central region of the plurality of regions, voltages of word lines in a region above the central region, and voltages of word lines in a region below the central region (Fig. 6: s640).
Regarding Claim 19, Choi teaches the limitation of Claim 18. Claim 19 is rejected for the same reasons as claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 12-14, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 20210280261) in view of Seo (US 9640266).
Regarding Independent Claim 1, Yang teaches an operating method of a nonvolatile memory device (Fig. 3a: 301) including a plurality of cell strings (Fig. 2B: 200), each cell string of the plurality of cell strings including a plurality of memory cells (Fig. 2B: 101_1-101_N), connected between a bit line (Fig. 2B: BL) and a common source line (Fig. 2B: SL), and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method comprising:
applying a word line voltage to the plurality of word lines (Fig. 2B: WL_1-WL_N);
However, Yang fails to teach classifying the plurality of word lines into a plurality of regions, each region of the plurality of regions including at least one of the word lines.
Seo teaches a classifying the plurality of word lines into a plurality of regions (Fig. 1:STA_1-STA_i), each region of the plurality of regions including at least one of the word lines (Fig. 8: WL0-WLn).
The grouping the word lines based on location in a stack of memory cells is useful because the resistance of the stack is different based on location. Thus, different voltages may need to be applied during a recovery operation in order to most efficiently perform the operation. By grouping like cells in the stack together the operation can be carried out more efficiently optimizing power and speed.
Neither source teaches recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions.
However, Yang teaches multiple methods of sequentially recovering the voltages of the word lines from bottom to top (Fig. 1B: 111) and from top to bottom (Fig. 2A: 221) recovering word lines starting in in the middle and then moving toward the top and/or bottom represents and obvious change in the sequence. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.”
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Seo to the teachings of Yang to produce a nonvolatile memory where the recovery operation starts with a central region in the word line stack and then works outward on groups above or below the central stack.
Regarding Claim 2, Yang and Seo teach the limitations of Claim 1. Seo Further teaches wherein the classifying of the plurality of word lines comprises:
classifying the word lines in the central region of the plurality of regions into a first region (Fig. 8: STA_2);
classifying word lines above the first region into a second region (Fig. 8: STA_i); and
classifying word lines below the first region into a third region (Fig. 8: STA_1).
Regarding Claim 3, Yang and Seo teach the limitations of Claim 2.
Neither teaches wherein the recovering the voltages of the plurality of word lines comprises:
recovering voltages of word lines in the second region and the third region after a delayed amount of time while voltages of word lines in the first region are recovered.
However, Yang teaches multiple methods of sequentially recovering the voltages of the word lines from bottom to top (Fig. 1B: 111) and from top to bottom (Fig. 2A: 221) recovering word lines starting in in the middle and then moving toward the top and/or bottom represents and obvious change in the sequence. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.”
Regarding Claim 4, Yang and Seo teach the limitations of Claim 2. Yang further teaches wherein the recovering the voltages of the plurality of word lines (Fig. 2A: WL_1-WL_N)) comprises:
recovering voltages of the word lines in the first region (Fig. 2A: 221); and
recovering voltages of the word lines in the second region and the third region (Fig. 2A: 221).
Regarding Claim 5, Yang and Seo teach the limitations of Claim 4.
Neither teach wherein the recovering the voltages of the plurality of word lines comprises:
simultaneously recovering the voltages of the word lines in the second region and third region.
However, Yang teaches multiple methods of sequentially recovering the voltages of the word lines from bottom to top (Fig. 1B: 111) and from top to bottom (Fig. 2A: 221) recovering word lines starting in in the middle and then moving toward the top and/or bottom represents and obvious change in the sequence. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.”
Regarding Claim 7, Yang and Seo teach the limitations of Claim 1. Yang further teaches wherein the plurality of cell strings are in rows and columns on the substrate (para 9 “Bias potentials are applied to the column through a bottom side source line (SL) 104 and a source-gate-source (SGS) transistor 105. Here, bottom is understood to mean closer to the semiconductor chip substrate”),
string select transistors (Fig. 1B: 103) of cell strings (Fig. 1B: 100) in one row are commonly connected to a string select line (Fig. 2: SGD),
ground select transistors (Fig. 1B: 105) of cell strings of two or more rows are commonly connected to a ground select line (Fig. 1B: SGS), and
memory cells (Fig. 2: MC1-6) of the plurality of cell strings (Fig. 1B: 100) at the same height from the substrate are commonly connected to one of the plurality of word lines (Fig. 2: WL_1-WL_N).
Regarding Independent Claim 12, Choi teaches an operating method of a nonvolatile memory device (Fig. 3a: 301) including a plurality of cell strings (Fig. 2B: 200), each cell string of the plurality of cell strings including a plurality of memory cells (Fig. 2B: 101_1-101_N), connected between a bit line (Fig. 2B: BL) and a common source line (Fig. 2B: SL), and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method comprising:
applying a word line voltage to the plurality of word lines (Fig. 2B: WL_1-WL_N);
However, Yang fails to teach classifying the plurality of word lines into a plurality of regions, each region of the plurality of regions including at least one of the word lines.
Seo teaches a classifying the plurality of word lines into a plurality of regions (Fig. 1:STA_1-STA_i), each region of the plurality of regions including at least one of the word lines (Fig. 8: WL0-WLn).
classifying the word lines in the central region of the plurality of regions into a first region (Fig. 8: STA_2);
classifying word lines above the first region into a second region (Fig. 8: STA_i); and
classifying word lines below the first region into a third region (Fig. 8: STA_1).
Neither source teaches recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions.
However, Yang teaches multiple methods of sequentially recovering the voltages of the word lines from bottom to top (Fig. 1B: 111) and from top to bottom (Fig. 2A: 221) recovering word lines starting in in the middle and then moving toward the top and/or bottom represents and obvious change in the sequence. MPEP 2144.04(IV)(C) states
The rationale for combining the teachings of Yang and Seo is the same as in Claim 1.
Regarding Claim 13, Yang and Seo teach the limitation of Claim 12. Claim 13 is rejected for the same reasons as Claim 3.
Regarding Claim 14, Yang and Seo teach the limitation of Claim 12. Claim 14 is rejected for the same reasons as Claim 4.
Regarding Independent Claim 18, Yang teaches a nonvolatile memory device (Fig. 3a: 301) comprising:
a memory cell array (Fig. 3a: 302) including
a plurality of memory blocks (para 10 “flash memory is written to (technically referred to as “programming”) in units of blocks”), each memory block of the plurality of memory blocks including a plurality of cell strings (Fig. 2B: 200), each cell string of the plurality of cell strings including a plurality of memory cells (Fig. 2B: 101_1-101_N) connected in series and penetrating at least one string select line (Fig. 2B: SGD),
a plurality of word lines (Fig. 2B: WL_1-WL_N), and
at least one ground select line (Fig. 2B: SGS) having a plate form and stacked on a substrate;
Seo teaches an address decoder (Fig. 1: 120) configured to
select a memory block (Fig. 1: BLK1-BLKz) of the plurality of memory blocks, and
provide driving voltages (Fig. 1: 150) to the at least one string select line (Fig. 5: DSL), the plurality of word lines (Fig. 5: WL0-WLn), and a ground select line (Fig. 5: SL) of the selected memory block; and a control logic (Fig. 1: 140) configured to
control the address decoder (Fig. 1: 120) during a program operation and a read operation,
classify the plurality of word lines into a plurality of regions (Fig. 8: STA_1-STA_i), and
Neither source teaches recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions.
However, Yang teaches multiple methods of sequentially recovering the voltages of the word lines from bottom to top (Fig. 1B: 111) and from top to bottom (Fig. 2A: 221) recovering word lines starting in in the middle and then moving toward the top and/or bottom represents and obvious change in the sequence. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.”
The rationale for combining the teachings of Yang and Seo is the same as in Claim 1.
Regarding Claim 19, Yang and Seo teach the limitation of Claim 18. Claim 19 is rejected for the same reasons as claim 2.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20240194274) in view of Seo (US 9640266).
Regarding Claim 16, Choi teaches the limitations of Claim 12. Choi fails to teach classifying the word lines above the second region into a fourth region; and classifying the word lines below the third region into a fifth region.
However, Seo teaches a fourth and fifth region (Fig. 8: STA_i; col 12 lines 33-34 “The cell string may be divided into a plurality of single stacks STA_1 to STA_i”)
If a memory contains more than 3 stacks of memory cells than it would be obvious to apply the method taught in Choi to more stacks in order to improve the power consumption and speed of the memory by group WL based on like resistances, which correlates with location within the stack.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply teachings of Seo to the teachings of Choi to produce a memory with a fourth and fifth region.
Regarding Claim 17, Choi and Seo teach the limitations of Claim 16. Neither Choi nor Seo teach recovering voltages of the word lines in the fourth region and the fifth region.
However, MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.” Therefore, adding two additional recovery steps for additional regions to be recovered represents an obvious modification of the recovery method already established since there are no new or unexpected results from this change to the sequence of recovering a string of memory cells.
It would have been obvious prior to the filing date of the claimed invention to apply the teachings of Seo to the teachings of Choi to produce a method of recovering word line voltages in a fourth and fifth region.
Allowable Subject Matter
Claim 6, 15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6, 15, and 20 teach a recovery line connected to the word line. Choi does not teach a recovery line. Thus, these claims would be allowable if written in independent form.
Response to Arguments
Applicant's arguments filed December 18, 2025 have been fully considered but they are not persuasive.
Applicant’s basis for overcoming the rejection under Choi relies on invoking the common ownership statement however. Applicant has failed to invoke the temporal element of common owner ship statement as outlined under 35 U.S.C. 102. Therefore, the rejection under 35 U.S.C. is maintained.
With regards to applicant’s arguments with respect to the obviousness rejection under 35 U.S.C. 103 in view of Yang and Seo. Applicant argues that specification shows new and unexpected results. However, MPEP 2145(I) states “Arguments presented by applicant cannot take the place of evidence in the record.” While the specification can take the form of evidence this can only be done in comparison to the prior art which the specification fails to do. Applicant relies solely on Figs. 10 and 11 which show the disclosed invention compared to an unidentified “comparative example.” It is not clear what this comparative example is nor that it is representative of the prior art applied. Further the graphs representing this comparative example merely show that the “example embodiments” differ to some degree from the comparative example, but as the x and y axis are unitless. It cannot be determined if the supposed benefits of the disclosed invention are substantive enough to be considered new and unexpected results. Therefore, the argument that the invention overcomes the prior art by producing new and unexpected results is found to be unpersuasive. The rejection under 35 U.S.C. 103 is maintained.
Finally, the amendments are not found to overcome the double patenting objection. The entirety of claim 12 is contained within claims 1 and 2 and the only limitation not included is one that states that three groups of word lines (first, second, and third) all contain at least one word line. The concept that regions of word lines would contain one or more word lines does nothing to differentiate the claim as that concept is implicit in claim 12 in that the regions classified are all word line regions, which are implicitly understood to contain at least one word line.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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