Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-14 are presented for Examination.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over More et.al. (U.S Patent Application Publication 2011/0022859; hereinafter “More”; Reference cited as prior art in previous office action) in view of Rowley et.al. (U.S Patent Application Publication 2020/0050252; hereinafter “Rowley”; Reference cited as prior art in previous office action)
Regarding Claim 1, More discloses , A power management circuit comprising:
a sequencer including a logic circuit structured to control start up and shutdown of a plurality of power supply circuits [0017;” Depending on the various circuits forming the power domains there may be a need to power some domains before others in a device start-up procedure and/or remove power from some power domains before others in a shut-down process ..”, 0018; “Power management units may therefore be provided with a sequencer for activating and deactivating the power blocks which supply the various power domains within the device in a predetermined sequence…”,0019; “ FIG. 2 illustrates how a sequencer 201 may be arranged to control the power blocks109a-d illustrated in FIG. 1. The sequencer may be part of the PMIC control circuitry 111 and controls the power blocks by updating the output configuration settings 209a-d in the predetermined sequence which is appropriate for that power transition.”, 0168; “ For example an ON to SLEEP transition may involve switching power block 109a off in one time slot and switching power block 109b off in a subsequent time slot. This ensures that power supply to power domain 103a is stopped before the power domain 109b is depowered, i.e. before power supply is stopped. A SLEEP to OFF transition ...”, 0169; 0212; “An OFF to ON transition would usually be the reverse, i.e. power blocks 103c would be switched on in the first time slot (together with any necessary adjustment of the power level of the Alive power domains), followed by power blocks 103b and then 103a in order”, 0171; Fig.2 ];
a nonvolatile memory[ “a non-volatile memory (NVM) 115.”, 0158; Fig.1]; and
wherein the setting data includes first data specifying one or more power supply circuits [0019; ” The sequencer may control the power blocks by updating the configuration settings via the serial control interface on the PMIC for communicating with the power blocks and/or the enable/disable signals could be provided on dedicated enable/disable signal lines.”, 0172; The sequence in which the power blocks are controlled is stored in the NVM 115 and,..”, 0173;0181; ” The sequence for all of the integrated power blocks and any connected external power blocks should ideally be stored in memory, such as the NVM 115 for use in a boot sequence and the sequencer should ideally be adapted to allow for sequencing of all of these power blocks. ...”, 0213; “the power management apparatus is arranged such that the duration of the predetermined delay is configurable. A PMIC may for example be configurable by on-chip non-volatile memory NVM such as one-time programmable (OTP) memory providing configuration data for on-chip control registers. The delay may be configurable to any desired duration or, at least, any duration within a set range. Alternatively, the predetermined delay may be configurable between a plurality of pre-set values.”, 0034; 0036; ( i.e. the predetermined delay settings corresponds to the setting data and the power blocks are turned on / off according to the settings data. Hence each of the power supply circuits/ power blocks are assigned to the respective settings.) ] , and
wherein the sequencer is structured to, control the one or more power supply circuits according to a predetermined sequence [0034; 0172-0173; 0181; “ The control circuitry may therefore be arranged to receive, via command and control signal lines 112, information regarding the power requirements of the power domains 103a-d from one or more of the various device sub-systems 117a-d and to control the outputs of power blocks 109a-d accordingly. The control signal lines 112 could comprise a serial communication bus or a number of hardware signal lines. The control signal lines may also be used to communicate control information back to the power domains.”, 0152; “.. Circuitry 502 is arranged to receive any power state transition command, wherever generated, including by the PMIC itself. On receipt of a power state transition command a suitable control signal is sent to delay circuitry 501. At the same time at least one control signal indicating a power state transition is sent, via a non-delayed path, to the command and control lines 112. ..”, 0178; Fig.1, 5( i.e. the control circuitry receives power state transition commands / events through the control signal lines 112 and controls the power blocks according to the sequence stored in the memory)].
However More does not expressly disclose a plurality of control pins, each of the control pins being associated with a different event, and each of the control pins being configured to receive an event signal that is asserted when the corresponding event occurs, power supply circuits assigned to each of the plurality of control pin, when an event signal input to any of the control pins is asserted, control the one or more power supply circuits assigned to the control pin on which the event signal is asserted.
In the same field of endeavor(e.g. a power management system includes a memory component storing a plurality of configuration profiles and Selectively activating a configuration profile based on signals received via corresponding configuration pins. Each of the configuration profile corresponds to a different set of operating characteristics of a subsystem and outputting a voltage signal with a magnitude corresponding to the operation characteristics), Rowley teaches ,
a plurality of control pins[“The power management component 213 can include a non-volatile memory (NVM) 214, a power supply 216, and/or configuration pins 208A to 208N.”, 0027; Fig.2], each of the control pins being associated with a different event, and each of the control pins being configured to receive an event signal that is asserted when the corresponding event occurs[ “The NVM 214 can store configuration profiles. The configuration profiles can include protocols, sets of operating voltages, ..In some embodiments, the configuration profiles can include power management specifications, which can manage power consumed by the host system and/or computer component. Other non-limiting examples of configuration profiles can include profiles that include power mode (e.g., sleep mode) sequencing,. ..”, 0028; “For example, application of a logical “1” (or physical voltage above a predetermined threshold voltage value) to configuration pin 208A (while configuration pins 208B and 208N have a logical value of “0” applied thereto) can correspond to a particular configuration profile being selected…”, 0030; ” the NVM 314 (e.g., the configuration profiles CONFIG_0 to CONFIG_N) can be selectively activated by the configuration pins shown and described in connection with FIG. 2. For example, the configuration profiles stored in the NVM 314 can be accessed through use of the configuration pins described in FIG. 2.”, 0042; “a configuration selection signal can be received to one or more power management configuration pins of the PMIC to selectively activate one of the configuration profiles. .a bootstrap configuration pin can be a pin that is activated as part of a bootstrap operation, as described above. In some embodiments, selective activation of the configuration profile can further include outputting a voltage signal with a magnitude corresponding to the particular set of operating characteristics from the PMIC”, 0047; Table 1; ( i.e. corresponding to a boot strap event the pins are selectively activated and the respective configuration profile is selected )], power supply circuits assigned to each of the plurality of control pin[ 0034;“one or more of the configuration pins 208A to 208N can be physically coupled (e.g., hardwired) to a voltage signal and/or a ground reference potential to cause selective activation of a configuration profile stored by the power management component 213. By choosing which configuration pins among the configuration pins 208A to 208N are coupled to the voltage signal and the ground reference potential, a particular configuration profile can be selectively activated.,”, 0035; ( i.e. assigning power to each of the pin with respect to an event) when an event signal input to any of the control pins is asserted, control the one or more power supply circuits assigned to the control pin on which the event signal is asserted [“The selection signals can cause the configuration pins 208A to 208N to be selectively activated to perform a bootstrapping operation to select the desired configuration profile stored by the power management component 213. For example, the configuration pins 208A to 208N can be selectively activated to cause a configuration profile corresponding to characteristics of the host system or memory sub-system to be enabled. In some embodiments, the configuration pins 208A to 208N can be selectively operated by selection signals generated by a host system, memory sub-system, and/or a controller”, 0033;” the power management component 213 can further include one or more output signal paths 221A to 221N. The output signal paths 221A to 221N can be configured to pass control signals externally from the power management component 213 to a memory sub-system, such as memory sub-system 110 illustrated in FIG. 1, herein.,..”, 0038; “The control signals passed via the output signal paths 221A to 221N can have different voltages, signal strengths, etc. corresponding thereto. For example, a magnitude of a voltage signal passed via output signal path 221A can have a different magnitude than a voltage passed via output signal path 221B. The control signals can comprise regulated signals to provide power or other configuration information to one or more components of the memory sub-system. For example, the control signals can provide power (e.g., an operating voltage) or other configuration information to the memory sub-system according a selected configuration profile”, 0039 Table 1; (i.e. based on the event the corresponding pins are selectively asserted to apply respective voltage / power to the subsystems according to the respective voltage signal assigned to the pins. Therefore, the activated pins assigned to a configuration profile , control the operating voltage or the power supply to the subsystems.).]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of More with Rowley. Rowley’s teaching of dynamically selecting a configuration profile based on the requirements of various subsystems will substantially improve More’s system to control the power domains by selecting a configuration profile based on the usage and voltage requirements of the device.
Regarding claim 3, Rowley teaches ,wherein the plurality of control pins are two control pins[ 0033].
Regarding Claim 4, More discloses wherein the setting data includes second data specifying an activation start timing for each of the plurality of power supply circuits in association with assertion of a corresponding event signal[0055; 0130; 0171; 0182; 0187];.
Regarding Claim 5, More discloses wherein the setting data includes third data specifying a shutdown start timing for each of the plurality of power supply circuits based on negation of a corresponding event signal[ 0017-0018; 0176].
Regarding Claim 6, More discloses a register structured to be accessed by an external controller[0152-0153; 0183], wherein the first data specifies which one of the plurality of control pins each of the plurality of power supply circuits is assigned to or is not assigned to, and a power supply circuit t is turned on or off according to a value of the register[0152;0175-0176];.
Rowley teaches, wherein the first data specifies which one of the plurality of control pins each of the plurality of power supply circuits is assigned to or is not assigned to, and a circuit that is not assigned to any of the plurality of control pins[0024; 0028; 0033; 0038]
Regarding Claim 11, More discloses, at least one timer circuit corresponding to the at least one event signal, wherein the at least one timer circuit starts an operation with assertion of the corresponding event signal as a trigger[0178-0180; Fig.5], and asserts a time slot signal at a predetermined plurality of timings[ 0054; 0063;0167], and the plurality of power supply circuits are associated with one of the plurality of timings generated by the at least one timer circuit [0182; 0213].
Regarding Claim 12, More discloses the plurality of power supply circuits [0150].
Regarding Claim 13, More discloses wherein the power management circuit is integrated on one semiconductor substrate [0059; 0147; Fig.1 102].
Regarding Claim 14, More discloses an electronic device comprising the power management circuit according to claim 1[0147; Fig.1]
Claims 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over More in view of Rowley as applied to claim 1 further in view of Ohnuma (U.S Patent Application Publication 2019/0179789; Reference cited as prior art in previous office action)
Regarding claim 7, More discloses sequencer activating of the plurality of power supply circuits[0168-0169; Fig.1] , Setting data[0181;0213] as outlined in claim 1.
However More, Rowley does not expressly disclose, a reset pin, wherein the sequencer negates a reset signal of the reset pin and the data defining a time until the reset signal is negated after the activation of the plurality of power supply circuits is completed.
In the same field of endeavor(an information processing apparatus including a connection terminal capable of being connected to various kinds of electronic devices having different functions and controlling the power supply to the connected devices ), Ohnuma teaches,
a reset pin, wherein the sequencer negates a reset signal of the reset pin, and the fourth data defining a time until the reset signal is negated [ 0039; “.. That is, to turn on the power of the optional device A, the extension function execution unit 20 performs sequential processes including first transmitting a power-on request signal to the optional device A, waiting for 100 ms, and then negating the reset terminal assigned the terminal number 2”, 0072; Fig.4A].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of More in view of Rowley with Ohnuma . Ohnuma ’s teaching of controlling the power supplied to the devices through a connector including a predetermined number of connection terminals will substantially enhance More in view of Rowley’s system to supply power with a particular voltage to the different subsystems by detecting the connection path of the devices based on the plurality of terminals whose locations and roles are fixedly set in advance[0087].
Regarding claim 8, More discloses sequencer [0168-0169; Fig.1]
Ohnuma teaches , wherein the at least one control pin includes a plurality of control pins[0039; Fig.3B], and when a predetermined one of the plurality of control pins is negated, negates the reset signal after a lapse of a predetermined time[0072; Fig.4A] .
Claims 9, 10 are rejected under 35 U.S.C. 103 as being unpatentable over More in view of Rowley as applied to claim 1 further in view of Purcell et.al. (U.S Patent Application Publication 2015/0370296; hereinafter “Purcell”)
Regarding Claim 9, More discloses , sequencer activating of the plurality of power supply circuits[0168-0169; Fig.1] , Setting data[0181;0213] as outlined in claim 1
However More does not expressly disclose, a fault pin, asserts a fault signal of the fault pin, and defining a time until the fault signal is asserted.
In the same field of endeavor(e.g. a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command), Purcell teaches,
a fault pin, asserts a fault signal of the fault pin, and defining a time until the fault signal is asserted [“ The controller 329 may include logic 334 to determine whether a power good indication (e.g., POWER_GOOD) from the voltage regulator modules indicates that the power group has been successfully enabled or disabled, and flip-flops 336, 338 having clock input terminals ..and the second flip-flop 338 may include an output terminal to output onto the fault bus a fault indication (e.g., SLAVE_FAULT_N)”, 0037; “ the slave power sequencers 202a . . . 202n may output to the fault bus 220 an indication of a fault. A fault may occur, for example, during power-up in which at least one of the voltage regulator modules 206, 208 or power groups 210, 212 fail to power up during a power sequencing protocol, during runtime in which at least one of the voltage regulator modules 206, 208 or power groups 210, 212 fails or performs incorrectly, or an overcurrent or otherwise fatal event. In various examples, a fault may be a failure to perform a power sequence state within a predetermined time period (e.g., if powering up or down a power group takes longer than a predetermined time period). In some of these examples, the watchdog timer 241a . . . 214n may be set for the predetermined time period.”, 0029; 0033].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of More in view of Rowley with Purcell. Purcell’s teaching of a power sequencing protocol with the master power sequencer, having full knowledge of the number of slave power sequencers and the number of power groups controlled by each of the slave power sequencers will substantially enhance More in view of Rowley’s system to maintain the proper timing and voltage inter-relationships during all operating conditions of the power control blocks based on the command.
Regarding claim 10, More discloses wherein the at least one control pin includes a plurality of control pins, and when a predetermined one of the plurality of control pins is negated, the sequencer negates the fault signal after a lapse of a predetermined time. [ “ may then enter the reset state (e.g., MASTER_STATE[n:0] and slave_state[n:0], respectively), and the slave power sequencers 202a . . . 202n may clear any fault indications (e.g., by releasing the SLAVE_FAULT_N signal). ..”, 0042; ( i.e clearing / negating the fault signal)].
However, Purcell does not expressly disclose negating after lapse of predetermined time.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Purcell to negate after lapse of predetermined time, since it has been held to be within the general skill of a worker in the art to select the component on the basis of its suitability for the intended use as a matter of design choice.
Response to Arguments
Applicant’s arguments with respect to the amended limitations of claim(s) 1 have been considered but are moot because the arguments do not apply to More in view of Rowley references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Woolley et al., U.S Patent Application Publication 2015/0199520, teaches system and methods for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of `pre-boot` information, such as the Reset Control Word and pre-boot processor configuration data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/PHIL K NGUYEN/ Primary Examiner, Art Unit 2176