Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 directed to figures 3-5I, 8A, 9-10B & 12A in the reply filed on 3/17/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 8, 10, 11, 13 and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mitarai (US PG. Pub. 2025/0254790).
Regarding claim 1 – Mitarai teaches a printed circuit board (figs. 1-15 [title] Mitarai states, “glass circuit board”) comprising: a glass layer (1 [paragraph 0053] Mitarai states, “glass substrate 1”) having a through-hole (H [paragraph 0053] Mitarai states, “through holes H”) penetrating between an upper surface and a lower surface thereof (see fig. 1); a through-via (combination of elements 23 & 15 shown within the through hole H) including a via metal layer (23 [paragraph 0050] Mitarai states, “feed-through wiring 23…copper”) disposed on a wall surface of the through-hole (H) and a first insulating material (15 [paragraph 0043] Mitarai states, “embedded resin 15 are made of an insulating resin material such as epoxy resin”) disposed in at least a portion of a space between portions of the via metal layer (23) in the through-hole (H); a first wiring layer (21 [paragraph 0044] Mitarai states, “first core wiring 21”) disposed on the upper surface (1a) of the glass layer (1), at least a portion of the first wiring layer (21) being connected to an upper side of the through-via (first wiring layer 21 is shown connected to via metal layer 23); a second wiring layer (22 [paragraph 0044] Mitarai states, “second core wiring 22”) disposed on the lower surface (1b) of the glass layer (1), at least a portion of the second wiring layer (22) being connected to a lower side of the through-via (second wiring layer 22 is shown connected to via metal layer 23); and a second insulating material (14 [paragraph 0043] Mitarai states, “The first resin layer 11, the second resin layer 12, the third resin layer 13, the fourth resin layer 14, and the embedded resin 15 are made of an insulating resin material such as epoxy resin”) covering at least a portion of an external surface (see exterior side surfaces of glass layer 1) of the glass layer (1), wherein the first (15) and second (14) insulating materials include substantially the same material (As quoted above both are formed of epoxy resin).
Regarding claim 7 – Mitarai teaches the printed circuit board according to claim 1, further comprising: a third insulating material (figs. 2 & 15, 50 [paragraph 0055] Mitarai states, “The processed glass epoxy substrate will be referred to as a frame substrate. The frame substrate 50 is an example of “frame” of the present disclosure”) covering at least a portion of an external surface (external side surface of second insulating layer 14) of the second insulating material (14), wherein the third insulating material (glass epoxy) includes a material different from the first and second insulating materials (epoxy resin of elements 14 and 15).
Regarding claim 8 – Mitarai teaches the printed circuit board according to claim 7, wherein the third insulating material (figs. 2 & 15, 50) has an elastic modulus greater than that of the first and second insulating materials (the third insulating material being glass epoxy will have a greater elastic modulus than that of the epoxy resin).
Regarding claim 10 – Mitarai teaches the printed circuit board according to claim 1, further comprising: one or more first insulating layers (fig. 1, 41 [paragraph 0049] Mitarai states, “first interlayer insulating film 41”) disposed on upper surfaces of each of the glass layer (1) and the second insulating material (14), and covering at least a portion of the first wiring layer (21); and one or more second insulating layers (42 [paragraph 0049] Mitarai states, “second interlayer insulating film 42”) disposed on lower surfaces of each of the glass layer (1) and the second insulating material (14), and covering at least a portion of the second wiring layer (22).
Regarding claim 11 – Mitarai teaches the printed circuit board according to claim 10, further comprising: one or more third wiring layers (fig. 1, 31 [paragraph 0050] Mitarai states, “first multilayer wiring 31”) disposed on or within the one or more first insulating layers (41); one or more first via layers (see vias connecting different third wiring layers 31) penetrating through at least one of the one or more first insulating layers (41), respectively; one or more fourth wiring layers (32 [paragraph 0050] Mitarai states, “second multilayer wiring 32”) disposed on or within the one or more second insulating layers (42); and one or more second via layers (see vias connecting different fourth wiring layers 32) penetrating through at least one of the one or more second insulating layers (42), respectively (claimed structure shown in figure 1).
Regarding claim 13 – Mitarai teaches a printed circuit board (figs. 1-15 [title] Mitarai states, “glass circuit board”) comprising: a through-via (fig. 1, combination of elements 23 & 15 shown within the through hole H) including a via metal layer (23 [paragraph 0050] Mitarai states, “feed-through wiring 23…copper”) and a first insulating material (15 [paragraph 0043] Mitarai states, “embedded resin 15 are made of an insulating resin material such as epoxy resin”) disposed in at least a portion of a space between portions of the via metal layer (23); a glass layer (1 [paragraph 0053] Mitarai states, “glass substrate 1”) including a first through-portion (H [paragraph 0053] Mitarai states, “through holes H”) in which the through-via is disposed (see fig. 1); a second insulating material (14 [paragraph 0043] Mitarai states, “The first resin layer 11, the second resin layer 12, the third resin layer 13, the fourth resin layer 14, and the embedded resin 15 are made of an insulating resin material such as epoxy resin”) including a second through-portion (see “second through-portion” shown between the left and right layer 14) in which the through-via (15/23) and the glass layer (1) are disposed; a first wiring layer (21 [paragraph 0044] Mitarai states, “first core wiring 21”) disposed on an upper surface of the glass layer (1), at least a portion of the first wiring layer (21) being connected to an upper side of the through-via (23); a second wiring layer (22 [paragraph 0044] Mitarai states, “second core wiring 22”) disposed on a lower surface of the glass layer (1), at least a portion of the second wiring layer (22) being connected to a lower side of the through-via (23); a first insulating layer (41 [paragraph 0049] Mitarai states, “first interlayer insulating film 41”) disposed on upper surfaces of each of the glass layer (1) and the second insulating material (14), and covering at least a portion of the first wiring layer (21); and a second insulating layer (42 [paragraph 0049] Mitarai states, “second interlayer insulating film 42”) disposed on lower surfaces of each of the glass layer (1) and the second insulating material (14), and covering at least a portion of the second wiring layer (22), wherein the first (15) and second (14) insulating materials include substantially the same material (As quoted above both are formed of epoxy resin).
Regarding claim 15 – Mitarai teaches the printed circuit board according to claim 13, further comprising: a third insulating material (figs. 2 & 15, 50 [paragraph 0055] Mitarai states, “The processed glass epoxy substrate will be referred to as a frame substrate. The frame substrate 50 is an example of “frame” of the present disclosure”) including a third through-portion (see through-portion having the glass layer 1 and second insulating material 14 therein as shown in figure 15) in which the through-via (15/23), the glass layer (1) and the second insulating material (14) are disposed, wherein the third insulating material (glass epoxy) includes a material different from the first (15) and second insulating materials (14; epoxy resin of elements 14 and 15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitarai in view of Fushie et al. (US PG. Pub. 2013/0062210).
Regarding claim 2 – Mitarai teaches the printed circuit board according to claim 1, but fails to explicitly teach wherein the glass layer includes plate glass.
Fushie teaches wherein the glass layer (fig. 1, 2) includes plate glass ([claim 1] Fushie states, “a glass substrate comprising a plate glass base material”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a glass layer as taught by Mitarai with the glass layer includes plate glass as taught by Fushie because plate glass is known to have high temperature resistance and dimensional stability.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitarai in view of Cho et al. (US PG. Pub. 2020/0058569).
Regarding claim 12 – Mitarai teaches the printed circuit board according to claim 11, but fails to teach further comprising: a first resist layer disposed on an upper surface of a first insulating layer disposed on an uppermost side of the one or more first insulating layers, and having a first opening exposing at least a portion of a third wiring layer disposed on an uppermost side of the one or more third wiring layers; and a second resist layer disposed on a lower surface of a second insulating layer disposed on a lowermost side of the one or more second insulating layers, and having a second opening exposing at least a portion of a fourth wiring layer disposed on a lowermost side of the one or more fourth wiring layers.
Cho teaches a printed circuit board (fig. 3, 100A) further comprising: a first resist layer (124 [paragraph 0050] Cho states, “layer 124 may be an insulating material, and in this case, a solder resist”) disposed on an upper surface of a first insulating layer (121) disposed on an uppermost side of the one or more first insulating layers (121), and having a first opening (124h [paragraph 0046] Cho states, “openings 124h”) exposing at least a portion of a third wiring layer (122) disposed on an uppermost side of the one or more third wiring layers (122); and a second resist layer (134 [paragraph 0056] Cho states, “layer 134 may be an insulating material, and in this case, a solder resist”) disposed on a lower surface of a second insulating layer (131) disposed on a lowermost side of the one or more second insulating layers (131), and having a second opening (134h [paragraph 0052] Cho states, “openings 134h”) exposing at least a portion of a fourth wiring layer (132) disposed on a lowermost side of the one or more fourth wiring layers (134).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a glass layer with third and fourth wirings within first and second insulating layers as taught by Mitarai with the first and second resist layers being formed on the first and second insulating layers with openings to expose the third and fourth wiring as taught by Cho because solder resist layers will prevent shorting between adjacent contact pads as well as prevent contamination from entering the interior of the PCB.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitarai.
Regarding claim 14 – Mitarai teaches the printed circuit board according to claim 13, wherein the second insulating material (figs. 1, 14) includes an Ajinomoto Build-up Film (ABF) ([paragraph 0060] Mitarai states, “The embedded resin 53 may be supplied in any form, e.g., in liquid or film form, according to a method such as printing or lamination with no particular restrictions. However, in view of the transmission characteristics and reliability of the wiring and affinity with the interlayer insulating film, a laminate of ABF (Ajinomoto Build-up Film) manufactured by Ajinomoto Fine-Techno Co., Inc. is used as an example”).
Mitarai fails to teach wherein the first insulating material include an Ajinomoto Build-up Film (ABF).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first insulating material being made of an Ajinomoto Build-up Film (ABF), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Ajinomoto Build-up Film (ABF) is known to be a high performance insulating material having low thermal expansion, ease of processing and durability.
Claim(s) 17-18, 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US PG. Pub. 2022/0384326) in view of Imayoshi (US PG. Pub. 2018/0166354).
Regarding claim 17 – Yang teaches a printed circuit board (fig. 10K) comprising: a glass layer (901 [paragraph 0095] Yang states, “glass substrate 901”) having a through-hole (through hole have through via 907 therein) penetrating between an upper surface and a lower surface thereof (see fig. 10K); a through-via (907 [paragraph 0097] Yang states, “interconnection metal layer 907”) including a via metal layer (903-906 [paragraph 0168] Yang states, “adhesion metal layer 903”) disposed on a wall surface of the through-hole and a first insulating material (908 [paragraph 0171] Yang states, “insulating dielectric layer 908”); a first wiring layer (upper wiring 27 [paragraph 0071] Yang states, “metal layer 27”) disposed on the upper surface of the glass layer (901), at least a portion of the first wiring layer (upper wiring 27) being connected to an upper side of the through-via (907); a second wiring layer (lower wiring 27) disposed on the lower surface of the glass layer (901), at least a portion of the second wiring layer (lower wiring 27) being connected to a lower side of the through-via (907); and a second insulating material (922 [paragraph 0145] Yang states, “polymer layer 922”) including a through-hole (see through-hole that contains the glass layer 901) in which the glass layer (901) is disposed and being in contact with the glass layer (901), wherein upper surfaces of each of the glass layer (901), the first insulating material (908), the second insulating material (922), and the via metal layer (903-906) are substantially coplanar with each other (claimed structure shown in figure 10K).
Yang fails to teach a through-via including a via metal layer disposed on a wall surface of the through-hole and a first insulating material disposed in at least a portion of a space between portions of the via metal layer in the through-hole.
Imayoshi teaches a printed circuit board (fig. 1, 100) having a through-via (see through via through glass layer 1) including a via metal layer (2 [paragraph 0075] Imayoshi states, “the first or second conductive layer 2 or 5 and the through electrode 3 may contain one of copper”) disposed on a wall surface of the through-hole and a first insulating material (14 [paragraph 0076] Imayoshi states, “hole-filling resin 14…polyimide”) disposed in at least a portion of a space between portions of the via metal layer (2) in the through-hole (claimed structure shown in figure 1).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a through via including a via metal layer and a first insulating material as taught by Yang with the first insulating material disposed in at least a portion of a space between portions of the via metal layer in the through hole as taught by Imayoshi because the first insulating material allows for controlling the coefficient of thermal expansion and “lessens or even avoids the local concentration of stress on the fine wires to provide sufficient reliability” [paragraph 0038]. Having vias with similar CTEs to that of the glass substrate will prevent the glass from cracking.
Regarding claim 18 – Yang in view of Imayoshi teach the printed circuit board according to claim 17, wherein lower surfaces of each of the glass layer (Yang; fig. 10K, 901), the first insulating material (908), the second insulating material (922), and the via metal layer (903) are substantially coplanar to each other (claimed structure shown in figure 10K).
Regarding claim 20 – Yang in view of Imayoshi teach the printed circuit board according to claim 17, wherein the via metal layer (Yang; fig. 10K, 903-906) includes a first seed layer (904 [paragraph 0096] Yang states, “seed metal layer 904”) disposed on the wall surface of the through-hole and a first metal layer (906 [paragraph 0096] Yang states, “bulk metal layer 906”) disposed on a side surface of the first seed layer (904), the first wiring layer (upper wiring 27) includes a second seed layer (upper seed layer 28b [paragraph 0147] Yang states, “seed layer 28b”) disposed on the upper surface of the glass layer (901) and a second metal layer (upper metal layer 40 [paragraph 0147] Yang states, “copper layer 40”) disposed on an upper surface of the second seed layer (28b), and the second wiring layer (lower wiring layer 27) includes a third seed layer (lower seed layer 28b) disposed on the lower surface of the glass layer (901) and a third metal layer (lower metal layer 40) disposed on a lower surface of the third seed layer (claimed structure shown in figure 10K).
Regarding claim 21 – Yang in view of Imayoshi teach the printed circuit board according to claim 20, wherein the second seed layer (Yang; fig. 10K, upper seed layer 28b) covers at least a portion of upper surfaces of each of the first seed layer (904), the first metal layer (906), and the first insulating material (908), and the third seed layer (lower seed layer 28b) covers at least a portion of lower surfaces of each of the first seed layer (904), the first metal layer (906), and the first insulating material (906; figure 10K shows the left wiring layers above and below glass layer 901 covering the entire through via of the glass layer 901).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Imayoshi as applied to claim 17 above, and further in view of Fushie et al.
Regarding claim 19 – Yang in view of Imayoshi teach the printed circuit board according to claim 17, but fails to explicitly teach wherein the glass layer includes plate glass.
Fushie teaches wherein the glass layer (fig. 1, 2) includes plate glass ([claim 1] Fushie states, “a glass substrate comprising a plate glass base material”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a glass layer as taught by Yang in view of Imayoshi with the glass layer includes plate glass as taught by Fushie because plate glass is known to have high temperature resistance and dimensional stability.
Allowable Subject Matter
Claims 3-6, 9, 16 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rho et al. (US PG. Pub. 2023/0307304) discloses a packaging substrate.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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