Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4,7-10,12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ooi et al (PG Pub 2012/0164810 A1).
Regarding claim 1, Ooi teaches a method of manufacturing a semiconductor device, comprising the steps of: forming a mask pattern (31/30, figs. 7-28) on a substrate (90); implanting a first impurity for a body region (123) into the substrate by using the mask pattern; implanting a second impurity for a first impurity region (124) into the substrate after implanting the first impurity; removing (fig. 22) the mask pattern; performing a first thermal process (paragraph [0071], fig. 14) on the substrate, forming a pre-body region and a pre- first impurity region in the substrate, and forming a gate insulating film (126) on the substrate; forming a first gate electrode and a second gate electrode (110, fig. 22, paragraph [0079]) spaced apart from each other on the gate insulating film; and performing a second thermal process (paragraph [0112]) on the substrate in which the pre-body region and the pre-first impurity region have been formed, and forming the body region and the first impurity region.
Regarding claim 2, Ooi teaches the method of claim 1, further comprising: performing a second ion implantation step (fig. 24, paragraph [0101]) for forming a second impurity region (125) within the first impurity region after the first thermal process is performed.
Regarding claim 3, Ooi teaches the method of claim 2, wherein the first impurity region is formed within the body region, and the second impurity region is formed within the first impurity region (fig. 22).
Regarding claim 4, Ooi teaches the method of claim 1, wherein, with the body region and the first impurity region formed, a channel region (CL, under middle gate 110; another one under left gate 110, fig. 22) is formed, the channel region being a portion of the body region, wherein the channel region overlaps with each of the first gate electrode and the second gate electrode in a first direction (vertical direction) and overlaps with the first impurity region in a second direction (horizontal direction), and wherein the first direction intersects the second direction.
Regarding claim 7, Ooi teaches the method of claim 1, wherein the first impurity region is formed within the body region (fig. 22).
Regarding claim 8, Ooi teaches the method of claim 1, wherein the step of performing the first ion implantation comprises: performing a first implantation process for the body region (123); and performing a second implantation process for the first impurity region (124).
Regarding claim 9, Ooi teaches the method of claim 8, wherein the second implantation process is performed after the first implantation process is performed (figs. 8-12).
Regarding claim 10, Ooi teaches the method of claim 8, wherein in the first implantation process, a first type of material is implanted, and in the second implantation process, a second type of material that is different from the first type is implanted (paragraph [0071]).
Regarding claim 12, Ooi teaches the method of claim 1, further comprising the step of: forming a buffer insulating film (silicon nitride 50 or 50a, paragraph [0056]) on the substrate before forming the mask pattern.
Regarding claim 13, Ooi teaches the method of claim 12, further comprising: after the step of performing the first ion implantation is performed, removing the mask pattern (figs. 13 and 26); removing the buffer insulating film (figs. 13 and 26); and performing a second thermal process (paragraph [0102]) on the substrate.
Regarding claim 14, Ooi teaches the method of claim 13, wherein the performing the second thermal process to form the body region and the first impurity region (activate implanted dopants, paragraphs [0070][0102]).
Regarding claim 15, Ooi teaches the method of claim 14, wherein the first gate electrode and the second gate electrode are formed after the pre-body region and the pre-first impurity region are formed in the substrate (figs. 22-28, paragraphs [0042]-[0047]), and the step of performing the first thermal process (figs. 7-14, paragraph [0072]) is performed on the substrate in which the pre-body region and the pre-first impurity region have been formed.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1,2,6, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (PG Pub 2019/0386117 A1) and Ooi et al (PG Pub 2012/0164810 A1).
Regarding claim 1, Lee teaches a method of manufacturing a semiconductor device, comprising the steps of: forming a mask pattern (800, figs. 6-10) on a substrate (140); implanting a first impurity for a body region (260 or 270, paragraphs [0065][0066]) into the substrate by using the mask pattern; implanting a second impurity for a first impurity region (280) into the substrate after implanting the first impurity; removing (fig. 10) the mask pattern; forming a pre-body region and a pre- first impurity region (260 or 270, and 280 before activating annealing in Ooi) in the substrate, and forming a gate insulating film (300a/300b/300) on the substrate; forming a first gate electrode and a second gate electrode (320a and 320b, paragraph [0066]) spaced apart from each other on the gate insulating film; and forming the body region and the first impurity region.
Lee does not teach performing a first thermal process on the substrate.
Lee teaches isolation regions are LOCOS (210, paragraph [0060]).
It is well known in the art that LOCOS are formed by a thermal oxidation process.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include in Lee’s device a step of performing a first thermal process on the substrate for the benefit of forming isolation regions 210.
Lee does not teach performing a second thermal process on the substrate in which the pre-body region and the pre-first impurity region have been formed.
In the same field of endeavor, Ooi teaches performing a second thermal process on the substrate in which the pre-body region and the pre-first impurity region have been formed, to activate implanted dopants (paragraphs [0004][0066][0067]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include in Lee’s device a step of performing a first thermal process performing a second thermal process on the substrate in which the pre-body region and the pre-first impurity region have been formed, for the benefit of activating implanted dopants.
Regarding claim 2, Lee teaches the method of claim 1, further comprising: performing a second ion implantation step (245, fig. 9, paragraph [0070]) for forming a second impurity region (290) within the first impurity region after the first thermal process is performed.
Regarding claim 6, Lee teaches the method of claim 2, wherein the second ion implantation step is performed using the first gate electrode and the second gate electrode spaced apart from each other as masks (fig. 9).
Regarding claim 21, the claim method of claim 1, further comprising: implanting a third impurity (245, fig. 9) into a portion of the first impurity region between the first gate electrode and the second gate electrode, with the first gate electrode and the second gate electrode as masks.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ooi et al (PG Pub 2012/0164810 A1) as applied to claim 10 above, and further in view of Kushida (US Patent 5,750,429).
Regarding claim 11, Ooi remains as applied in claim 10.
Ooi does not teach in the first implantation process, boron is implanted, and in the second implantation process, arsenic is implanted.
Ooi teaches in the first implantation process, p-type dopant is implanted (paragraph [0095]), and in the second implantation process, n-type dopant is implanted (paragraph [0095]).
In the same field of endeavor, Kushida teach to use boron as a p-type dopant and arsenic as an n-type dopant (column 5, lines 24-30).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to implant boron in the first implantation process and to implant arsenic in the second implantation process, for the benefit of forming p-type and n-type regions, respectively.
Allowable Subject Matter
Claim 20 is allowed.
Claim 5 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior art does not teach
“a material implanted to form the body region is of a different type from a material implanted to form the first impurity region and the second impurity region” (claim 5);
“forming a contact penetrating to the first impurity region and the second impurity region” (claim 22);
“forming a buffer insulating film on a substrate; forming a mask pattern on the buffer insulating film; implanting a first impurity for a body region into the substrate by using the mask pattern; implanting a second impurity for a first impurity region into the substrate after implanting the first impurity; removing the mask pattern and the buffer insulating film; performing a first thermal process on the substrate… and forming a gate insulating film on the substrate; forming a first gate electrode and a second gate electrode spaced apart from each other on the gate insulating film; performing a second thermal process on the substrate in which the pre-body region and the pre-first impurity region have been formed…; and implanting a third impurity into a portion of the first impurity region between the first gate electrode and the second gate electrode, with the first gate electrode and the second gate electrode as masks” (claim 20).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 7/14/26 have been fully considered but they are not persuasive. Applicant’s arguments do not seem to apply to the current application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
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/FEIFEI YEUNG LOPEZ/ Primary Examiner, Art Unit 2899
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