DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 02/14/2024.
Claims 1-10 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “optionally storing said data output that is encrypted in a storage means in the compute environment;” it is unclear whether “storing said data output that is encrypted in a storage means in the compute environment;” is required making it indefinite.
For the purposes of compact prosecution examiner will interpret the claim limitation “storing said data output that is encrypted in a storage means in the compute environment;” as required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, and 6-10 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1:
Claims 1-4, and 6-9 are directed to a method and falls within the statutory category of process; Claim 10 is directed to machine which falls within the statutory category of machines.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1 and 10: The limitations “selecting, in said HPC machine, [the computing] resources for carrying out said computing job”, “isolating said compute environment from a rest of the HPC machine so that interaction with said compute environment is restricted to said client”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally select a device to complete a certain task while considering qualities of that resource. Further, a person can choose a compute environment for a single job to execute on.
Therefore, yes, Claims 1 and 10 recite judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A prong 2:
Claims 1 and 10: The judicial exceptions are not integrated into practical applications. In particular, the claims recite the following additional elements – “said resources forming a compute environment comprising one or several computing nodes”, “wherein the HPC machine is configured to carry out a method for carrying out the computing job for a client on a said HPC machine” and “performing computation of the computing job in said compute environment;”, is a recitation of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)). Further “computing resources that carry out the computing job, said computing resources comprising at least one computation node, and a quarantine manager;” recites a field of use which generally links the use of a judicial exception to a particular technological environment (MPEP § 2106.05(h)).
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that the Claims 1 and 10 not only recite a judicial exception but that the claims are directed to a judicial exception as a judicial exception has not been integrated into a practical application.
Step 2B:
Claims 1 and 10: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components, field of use/technological environment.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 1 and 10 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding Claim 2 and 3: “loading data to be computed in storage means located in the compute environment, in encrypted form” reciting insignificant extra-solution data gathering activity, MPEP § 2106.05(g) and “decrypting the data that is loaded”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person mentally decrypt encrypted data. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 2 and 3 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more, performing a well understood, routine, and conventional task of data gathering. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network … iv. Storing and retrieving information in memory”. See MPEP § 2106.05(d)(II). Therefore, Claims 2 and 3 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding Claim 4: “checking compliance of at least one component of the compute environment to at least one technical specification specific to the computing job,” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can check if components are compliant with the requirements of a job. “in case said at least one component is not compliant, configuring said at least one component rendering said at least one component compliant with said at least one technical specification”, is a recitation of generic computing components and functions merely being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)). With regard to integration into practical application and whether additional elements amount to significantly more, Claims 4 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 4 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding Claim 6: “comprising flagging at least one component of the compute environment as non-accessible;” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can flag certain components as non-accessible. “deploying at least one system-level configuration inside said compute environment; deploying at least one environmental-level configuration outside said compute environment to at least one network component and/or to an interconnect component”, reciting insignificant extra-solution data storage and transmission activity, MPEP § 2106.05(g). With regard to integration into practical application and whether additional elements amount to significantly more, Claims 6 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more, performing a well understood, routine, and conventional task of data gathering. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network … iv. Storing and retrieving information in memory”. See MPEP § 2106.05(d)(II). Therefore, Claims 6 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding Claim 7: “encrypting data output by the computation of the computing job,” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally encrypt data output from a computer, and “optionally storing said data output that is encrypted in a storage means in the compute environment; while the compute environment is in an isolated state”, reciting insignificant extra-solution data storage activity, MPEP § 2106.05(g). With regard to integration into practical application and whether additional elements amount to significantly more, Claims 7 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more, performing a well understood, routine, and conventional task of data gathering. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network … iv. Storing and retrieving information in memory”. See MPEP § 2106.05(d)(II). Therefore, Claims 7 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding Claim 8: “de-isolating the compute environment from the rest of the HPC machine so that the interaction with said compute environment is restored” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can use multiple compute resources in order to execute a single job. With regard to integration into practical application and whether additional elements amount to significantly more, Claims 8 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claims 8 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding Claim 9: “cleaning the compute environment by deleting residual data regarding the computing job in at least one component of the compute environment”, reciting insignificant extra-solution data storage activity, MPEP § 2106.05(g). With regard to integration into practical application and whether additional elements amount to significantly more, Claims 9 fail both prongs of Step 2A, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more, performing a well understood, routine, and conventional task of data gathering. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. iv. Storing and retrieving information in memory”. See MPEP § 2106.05(d)(II). Therefore, Claims 9 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Rogers et al. (US 20230094125 A1) (hereinafter Rogers).
Regarding Claim 1, Rogers teaches:
A method for carrying out a computing job for a client on a High Performance Computing (HPC) machine,
“one or more PPUs 3300 are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications”, (Rogers: ¶444), “a work descriptor (WD) 1684 contained in process element 1683 can be a single job requested by an application or may contain a pointer to a queue of jobs”, (Rogers: ¶275), “compute services 3816 may be leveraged by applications to perform super-computing or other high-performance computing (HPC) tasks”, (Rogers: ¶518), “provides an ability to preempt processing of a job”, (Rogers: ¶284), “leverage parallel processing units (PPUs), such as graphics processing units (GPUs), to execute user code or perform other operations”, (Rogers: ¶056), “PPUs can be included as hardware in server computer systems in data centers that provide computing resources to users over one or more networks”, (Rogers: ¶057), “a trusted execution environment (TEE) 106 with access to multiple accelerators” … “a server computer system includes a central processing unit (CPU) 102 and a parallel processing unit (PPU), such as a graphics processing unit (GPU) 104. In one example, the server computer system is included in a data center and leveraged to provide computing resources to users of a computing resource service provider …”, (Rogers: ¶059), “the hypervisor can provide the TEE 106 with access to the GPU 104 by at least providing virtualization of the GPU 104”, (Rogers: ¶060), “components within the TEE 106 (e.g., applications 108A-108N” … “can communicate with the GPU 104 over the system bus 120 using driver(s) 110”, (Rogers: ¶061), “data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and/or inferencing”, (Rogers: ¶127). Examiner notes: the PPU, GPU and TEE can all be a part of a server computer system that can be used as a data center or HPC environment/machine.
said method comprising: selecting, in said HPC machine, resources for carrying out said computing job,
“memory or storage resources that may be configured or allocated to support one or more workloads” … “provide compute resources to support one or more workloads”, (Rogers: ¶120), “resource manager 1026 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 1028 and job scheduler 1022”, (Rogers: ¶122).
said resources forming a compute environment comprising one or several computing nodes,
“…data center infrastructure layer 1010 may include a resource orchestrator 1012, grouped computing resources 1014, and node computing resources (“node C.R.s”) 1016(1)-1016(N)” … “may include, but are not limited to, any number of central processing units (“CPUs”) or other processors”, (Rogers: ¶119), “several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads”, (Rogers: ¶120).
and performing computation of the computing job in said compute environment;
“leverage parallel processing units (PPUs), such as graphics processing units (GPUs), to execute user code or perform other operations…”, (Rogers: ¶056), “compute service(s) 3816 may be leveraged to perform parallel processing (e.g., using a parallel computing platform 3830) for processing data through one or more of applications and/or one or more tasks of a single application”, (Rogers: ¶518).
and, before the performing the computation of the computing job, isolating said compute environment from a rest of the HPC machine so that interaction with said compute environment is restricted to said client.
“The cryptographic key is used to isolate the guest operating system 112 from the hypervisor 114. In addition, in various examples, the cryptographic key used to isolate the guest operating system 112 from the hypervisor 114 is managed by the CPU”, (Rogers: ¶059), “the secure processor 132 creates or causes to be created the protected memory region 136 and/or GPU trust boundary 126”, (Rogers: ¶062), “the secure microcontroller encrypts data from the protected memory region of the PPU and stores the data in a memory region accessible to the CPU”, (Rogers: ¶058), “management unit of the GPU prevents access to the protected memory ranges of the GPU from entities”, (Rogers: ¶084).
Regarding Claim 2, Rogers teaches:
before the isolating, loading data to be computed in storage means located in the compute environment, in encrypted form.
“encrypts data using the shared key and stores the encrypted data in a memory region accessible to the PPU, the secure microcontroller then obtains the encrypted data”, (Rogers: ¶058), “cryptographic material (e.g., a cryptographic key) is used to encrypt the TEE 106 and data within a secure 116 region of the system memory” … “the cryptographic key is used to isolate the guest operating system 112 from the hypervisor 114”, (Rogers: ¶059), “the shared cryptographic key is used to encrypt data for transmission between the CPU and GPU”, (Rogers: ¶087).
Regarding Claim 3, Rogers teaches:
after the isolating, decrypting the data that is loaded.
“the secure microcontroller then obtains the encrypted data, decrypts the encrypted data with the shared key and stores the results in the protected memory region of the PPU”, (Rogers: ¶058), “the GPU may be operating in the secure execution mode (e.g., enclave mode)” … “limiting or blocking access to one or more memory ranges of the GPU memory”, (Rogers: ¶084), “the process 600, decrypts the encrypted data with the shared cryptographic key”, (Rogers: ¶092), “the process 700, provides the decrypted data to the TEE. In one example, the encrypted data includes a result of an operation performed by the GPU”, (Rogers: ¶094).
Regarding Claim 4, Rogers teaches:
before the isolating checking compliance of at least one component of the compute environment to at least one technical specification specific to the computing job, and in case said at least one component is not compliant, configuring said at least one component rendering said at least one component compliant with said at least one technical specification.
“a scheduler may be used to track resource requirements of applications or containers, current usage or planned usage of these resources, and resource availability” … “allocate resources to different applications and distribute resources between and among applications in view of requirements and availability of a system” … “may determine resource availability and distribution based on constraints imposed on a system (e.g., user constraints), such as quality of service (QoS), urgency of need for data outputs (e.g., to determine whether to execute real-time processing or delayed processing)”, (Rogers: ¶517), “the virtual machine and/or a component thereof (e.g., application software, guest operating system, drivers, etc.) performs one or more checks to determine the GPU is operating in the secure execution mode and authenticates the GPU”, (Rogers: ¶086), “scheduler 2110 ensures that processing cluster array 2112 is properly configured and in a valid state before tasks are distributed to a cluster of processing cluster array 2112”, (Rogers: ¶325), “resource orchestrator 1012 may configure or otherwise control one or more node C.R.s 1016(1)-1016(N) and/or grouped computing resources 1014”, (Rogers: ¶121), “resource orchestrator 1012 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion”, (Rogers: ¶125), “dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unit 3208A-N or 3207A-N)”, (Rogers: ¶426).
Regarding Claim 5, Rogers teaches:
preventing access to said compute environment to any third party; preventing the compute environment from sending data to outside the compute environment; preventing the compute environment from receiving data from outside the compute environment.
“the GPU 104 must be idle (e.g., no other virtual machines and/or tenants are accessing or otherwise utilizing the GPU 104)” … “the secure processor 132 prevents access to the GPU 104”, (Rogers: ¶062), “a memory management unit of the GPU 236 prevents access to a memory region where the cryptographic key is stored to any entity that is not the secure processor 232”, (Rogers: ¶075), “a memory management unit of the GPU 336 prevents access to the secure 320 region of the GPU memory 304 by at least preventing access from across the system bus. In such examples, the memory management unit prevents access to the secure 320 region of the GPU memory 304 based at least in part on a hardware identifier or other identifier of the entity attempting to access the secure 320 region of the GPU memory 304” … “the memory management unit returns a fault or other error if an unauthorized entity attempts to access the secure 320 region of the GPU memory 304”, (Rogers: ¶080), “a write protect memory region is generated that blocks access to the PPU memory from other computing devices (e.g., from a CPU accessing the PPU memory across a system bus or other communication channel)”, (Rogers: ¶056).
Regarding Claim 6, Rogers teaches:
flagging at least one component of the compute environment as non-accessible;
“writes data to the non-volatile memory of the GPU indicating that, on reset, the GPU is to enter the secure execution mode”, (Rogers: ¶084), “the secure processor 232, in various embodiments, generates an attestation indicating the GPU 236 is operating within the secure execution mode”, (Rogers: ¶073), “the request (e.g., data indicating an operating mode to the GPU) is recorded in GPU memory (e.g., non-volatile memory (PROM) attached to the GPU)”, (Rogers: ¶089). Examiner notes: the data is indicating whether GPU is in secure execution mode which determines if it is accessible or not.
deploying at least one system-level configuration inside said compute environment;
“data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030 and an application layer 1040”, (Rogers: ¶118), “data center infrastructure layer 1010 may include a resource orchestrator 1012, grouped computing resources 1014, and node computing resources (“node C.R.s”) 1016(1)-1016(N)”, (Rogers: ¶119), “resource orchestrator 1012 may configure or otherwise control one or more node C.R.s 1016(1)-1016(N)”, (Rogers: ¶121), “, framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026 and a distributed file system 1028” … “configuration manager 1024 may be capable of configuring different layers such as software layer 1030 and framework layer 1020 including Spark and distributed file system 1028 for supporting large-scale data processing”, (Rogers: ¶122), “software layer 1030 may include software used by at least portions of node C.R.s 1016(1)-1016(N), grouped computing resources 1014, and/or distributed file system 1028 of framework layer 1020”, (Rogers: ¶123). Examiner notes: configuration manager is being interpreted as the system-level configuration.
deploying at least one environmental-level configuration outside said compute environment to at least one network component and/or to an interconnect component.
“application and/or container (or image thereof) may be individually developed, modified, and deployed”, (Rogers: ¶517), “node C.R.s 1016(1)-1016(N) may include, but are not limited to” … “memory storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input/output (“NW I/O”) devices”, (Rogers: ¶119), “I/O switch 2016 can be used to provide an interface mechanism to enable connections between I/O hub 2007 and other components”, (Rogers: ¶319), “In at least one embodiment, a backbone may include a computer vision network on-chip that interconnects a PVA and a DLA to memory (e.g., using APB)”, (Rogers: ¶168), “a GPU may be communicatively coupled to host processor/cores over a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink)”, (Rogers: ¶352). Examiner notes: Resource orchestrator is being interpreted as the environmental-level configuration.
Regarding Claim 7, teaches:
encrypting data output by the computation of the computing job, and optionally storing said data output that is encrypted in a storage means in the compute environment; while the compute environment is in an isolated state.
“the memory copy 238 includes data from an output buffer 226 within the secure 220 region of the GPU memory 204 and encrypted by a secure processor 232”, (Rogers: ¶071), “the secure processor 232 generates a cryptographic key to encrypt the data in the output buffer 226 and generate the encrypted results 210” … “a compute engine 234 generates the data stored in the output buffer 226”, (Rogers: ¶072), “the encrypted data includes a result of an operation performed by the GPU”, (Rogers: ¶094), “FIG. 7 illustrates an example process for copying data within a trusted execution environment including multiple accelerators, according to at least one embodiment;”, (Rogers: ¶008), Fig 8), “the GPU, when operating in secure execution mode, creates the protected memory region such that plain text data within the protected memory region is inaccessible to unauthorized entities”, (Rogers: ¶092), “graphics acceleration module 1646 to save and restore context state. In at least one embodiment, this pointer is optional if no state is required to be saved between jobs or when a job is preempted”, (Rogers: ¶286).
Regarding Claim 8, teaches:
after the computing job is carried out, de-isolating the compute environment from the rest of the HPC machine so that the interaction with said compute environment is restored.
“FIG. 5 illustrates an example process for terminating a trusted execution environment including multiple accelerators, according to at least one embodiment;”, (Rogers: ¶006, Fig. 5), “Terminating the virtual machine, for example, includes releasing physical hardware used to support the virtual machine” … “when the virtual machine is terminated, the TEE is destroyed and the GPU is disconnected from the virtual machine and/or TEE”, (Rogers: ¶088), “writes a request to disable the secure execution mode on the GPU” … “writing this request causes the GPU to exit a secure execution mode at the next GPU reset” … “the system executing the process 500, resets the GPU. For example, the secure processor causes the GPU to perform a soft reset”, (Rogers: ¶089), “context management circuit 1648 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved, and a second thread is stored so that a second thread can be executed by a graphics processing engine)”, (Rogers: ¶265).
Regarding Claim 9, teaches:
cleaning the compute environment by deleting residual data regarding the computing job in at least one component of the compute environment.
“The process 500, at block 502, includes detecting a virtual machine exit. In various embodiments, the TEE includes a virtual machine executing an application for a tenant, after execution of the application or at any point the tenant terminates execution of the virtual machine. Terminating the virtual machine, for example, includes releasing physical hardware used to support the virtual machine”, (Rogers: ¶088), “the system executing the process 500 deletes the GPU memory. In one example, all contents of the GPU memory are deleted…”, (Rogers: ¶089).
Regarding Claim 10, teaches:
A High Performance Computing (HPC) machine that carries out a computing job,
“one or more PPUs 3300 are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications”, (Rogers: ¶444), “a work descriptor (WD) 1684 contained in process element 1683 can be a single job requested by an application or may contain a pointer to a queue of jobs”, (Rogers: ¶275), “compute services 3816 may be leveraged by applications to perform super-computing or other high-performance computing (HPC) tasks”, (Rogers: ¶518), “provides an ability to preempt processing of a job”, (Rogers: ¶284), “leverage parallel processing units (PPUs), such as graphics processing units (GPUs), to execute user code or perform other operations”, (Rogers: ¶056), “PPUs can be included as hardware in server computer systems in data centers that provide computing resources to users over one or more networks”, (Rogers: ¶057), “a trusted execution environment (TEE) 106 with access to multiple accelerators” … “a server computer system includes a central processing unit (CPU) 102 and a parallel processing unit (PPU), such as a graphics processing unit (GPU) 104. In one example, the server computer system is included in a data center and leveraged to provide computing resources to users of a computing resource service provider …”, (Rogers: ¶059), “the hypervisor can provide the TEE 106 with access to the GPU 104 by at least providing virtualization of the GPU 104”, (Rogers: ¶060), “components within the TEE 106 (e.g., applications 108A-108N” … “can communicate with the GPU 104 over the system bus 120 using driver(s) 110”, (Rogers: ¶061), “data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and/or inferencing”, (Rogers: ¶127). Examiner notes: the PPU, GPU and TEE can all be a part of a server computer system that can be used as a data center or HPC environment/machine.
said HPC machine comprising: computing resources that carry out the computing job, said computing resources comprising at least one computation node, and a quarantine manager;
“…data center infrastructure layer 1010 may include a resource orchestrator 1012, grouped computing resources 1014, and node computing resources (“node C.R.s”) 1016(1)-1016(N)” … “may include, but are not limited to, any number of central processing units (“CPUs”) or other processors”, (Rogers: ¶119), “several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads”, (Rogers: ¶120), “the cryptographic key used to isolate the guest operating system 112 from the hypervisor 114 is managed by the CPU 102 and not exposed or otherwise accessible to the hypervisor 114”, (Rogers: ¶059), “the protected memory region is managed by the memory management unit such that the compute engine of the GPU is allowed to access the protected memory region, but is unable to write to other memory regions after accessing the protected memory region”, (Rogers: ¶085). Examiner notes: the CPU and GPU both act as quarantine managers by being in charge of protected/ isolated memory regions.
wherein the HPC machine is configured to carry out a method for carrying out the computing job for a client on a said HPC machine, said method comprising selecting, in said HPC machine, the computing resources for carrying out said computing job,
“memory or storage resources that may be configured or allocated to support one or more workloads” … “provide compute resources to support one or more workloads”, (Rogers: ¶120), “resource manager 1026 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 1028 and job scheduler 1022”, (Rogers: ¶122).
While Rogers does not explicitly teach a HPC selecting resources for carrying out a computing job, it does teach a PPU employing a HPC to perform whatever job needed to be completed. “compute services 3816 may be leveraged by applications to perform super-computing or other high-performance computing (HPC) tasks”, (Rogers: ¶518). This is similar because the PPU is essentially an orchestrator or middle man for carrying out said job. It would be obvious to remove the middleman and have the HPC perform execution of the jobs
said computing resources forming a compute environment comprising one or several computing nodes;
“…data center infrastructure layer 1010 may include a resource orchestrator 1012, grouped computing resources 1014, and node computing resources (“node C.R.s”) 1016(1)-1016(N)” … “may include, but are not limited to, any number of central processing units (“CPUs”) or other processors”, (Rogers: ¶119), “several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads”, (Rogers: ¶120).
performing computation of the computing job in said compute environment;
“leverage parallel processing units (PPUs), such as graphics processing units (GPUs), to execute user code or perform other operations…”, (Rogers: ¶056), “compute service(s) 3816 may be leveraged to perform parallel processing (e.g., using a parallel computing platform 3830) for processing data through one or more of applications and/or one or more tasks of a single application”, (Rogers: ¶518).
and, before the performing the computation of the computing job, isolating said compute environment from a rest of the HPC machine so that interaction with said compute environment is restricted to said client.
“The cryptographic key is used to isolate the guest operating system 112 from the hypervisor 114. In addition, in various examples, the cryptographic key used to isolate the guest operating system 112 from the hypervisor 114 is managed by the CPU”, (Rogers: ¶059), “the secure processor 132 creates or causes to be created the protected memory region 136 and/or GPU trust boundary 126”, (Rogers: ¶062), “the secure microcontroller encrypts data from the protected memory region of the PPU and stores the data in a memory region accessible to the CPU”, (Rogers: ¶058), “management unit of the GPU prevents access to the protected memory ranges of the GPU from entities”, (Rogers: ¶084).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIHAB ALAM whose telephone number is (571)272-8705. The examiner can normally be reached Mon - Fri 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached at (571) 272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHIHAB ALAM/Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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