Prosecution Insights
Last updated: October 25, 2026
Application No. 18/441,649

METHODS AND SYSTEMS TO OPTICALLY REALIZE NEURAL NETWORKS

Final Rejection §103§112
Filed
Feb 14, 2024
Priority
Sep 01, 2021 — continuation of PCTCA2021051212
Examiner
DUNAY, CHRISTOPHER E
Art Unit
2875
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Canada Co. Ltd.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
579 granted / 757 resolved
+8.5% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
33 currently pending
Career history
788
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
52.3%
+12.3% vs TC avg
§102
22.1%
-17.9% vs TC avg
§112
21.6%
-18.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 757 resolved cases

Office Action

§103 §112
DETAILED ACTION Response to Amendment The applicant’s amendment filed 9/9/2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1 and 3-20 rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without the limitations of claims 2, 21, and 22, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). In regard to claims 1, 12, and 20, it appears that the absence of the digital-analog conversion is critical to the applicant’s invention—the lack of a conversion is required for the optimization disclosed. This must be included in the independent claims before allowance. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bangari et al (Digital Electronics and Analog Photonics for Convolutional Neural Networks). In regard to claim 1 and 12, Bangari et al disclose an analog computing platform operative to implement at least one layer of a neural network, the analog computing platform comprising: an interface operative to receive elements of a first matrix and elements of a second matrix in the analog domain; and a layered neural network including at least one optical processing chip operative to optically perform multiply-and-accumulate (MAC) operations with the matrix elements in the analog domain. Bangari et al fail to disclose a Field Analog Vision module. However, it would have been obvious to one of ordinary skill in the art at the time of filing to implement any interface operative to receive elements of a first matrix and elements of a second matrix in the analog domain in order to implement the procedure of Bangari et al. In regard to claim 3 and 14, Bangari et al fail to explicitly disclose a summation unit operative to add bias values over the results of MAC operations, and wherein at least one layer of a neural network is a convolutional layer, the matrix elements include elements of a kernel matrix. However, it would have been obvious to one of ordinary skill in the art at the time of filing to provide biases and a convolution layer in order to provide model flexibility and to work with spatial data. In regard to claim 4 and 15, Bangari et al fail to explicitly disclose a summation unit operative to add bias values over the results of MAC operations, and wherein at least one layer of a neural network is a fully connected layer, the matrix elements include elements of a kernel matrix. However, it would have been obvious to one of ordinary skill in the art at the time of filing to use connected layers in order to combine features and to improve decision making. In regard to claim 5 and 16, Bangari et al fail to explicitly disclose at least one layer of a neural network is a batch normalization layer, the matrix elements include learned parameters, and the results of the MAC operations are biased by a learned parameter. However, it would have been obvious to one of ordinary skill in the art at the time of filing to use batch normalization in order to rescale data. In regard to claim 6 and 17, Bangari et al fail to explicitly disclose a CMOS circuit, wherein at least one layer of a neural network is a max pooling layer, and the CMOS circuit includes one or more comparators configured to identify in a matrix the matrix element having the maximum value. However, it would have been obvious to one of ordinary skill in the art at the time of filing to use a comparator and pooling layer in order to reduce dimensionality. In regard to claim 7 and 18, Bangari et al fail to explicitly disclose at least one layer of a neural network is an average pooling layer, the first matrix includes a number k2 of elements, the second matrix is constructed such that each of its elements is 1/k2, and the MAC operation between the elements of the first matrix and the elements of the second matrix results in an average value for the elements in the first matrix. However, it would have been obvious to one of ordinary skill in the art at the time of filing to use average pooling in order to reduce computation and smooth noise. In regard to claim 8, 9, and 19, Bangari et al fail to explicitly disclose a CMOS circuit, wherein at least one layer of a neural network includes a rectified linear unit (ReLU) non-linear function, and the CMOS circuit is configured to perform a ReLU non-linear function over one or more matrix elements, or as recited in claim 9, a CMOS circuit, wherein at least one layer of a neural network includes a sigmoid function, and the CMOS circuit is configured to perform a sigmoid function over one or more matrix elements. However, it would have been obvious to one of ordinary skill in the art at the time of filing to use ReLU or a sigmoid in order to model non-linear features. In regard to claim 10, Bangari et al fail to explicitly disclose at least two different layers of a neural network, implemented in concatenation. However, it would have been obvious to one of ordinary skill in the art at the time of filing to use concatenation in order connect layers. In regard to claim 11, Bangari et al fail to explicitly disclose matrix elements include point coordinates from a point cloud. However, it would have been obvious to one of ordinary skill in the art at the time of filing to use point coordinates in order to model spatial data. In regard to claim 13, Bangari et al fail to explicitly disclose the MAC operations with the matrix elements is optically performed in series. However, it would have been obvious to one of ordinary skill in the art at the time of filing to perform calculations in series in order to limit hardware requirements. (Things can only be performed in series or in parallel. This choice is at least obvious to try.) Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bangari et al (Digital Electronics and Analog Photonics for Convolutional Neural Networks) in view of Casas et al (US 10,997,502 B1). In regard to claim 20, Bangari et al disclose a system in which the processing of data is performed with a layered neural network implemented on an analog computing platform operative to optically perform at least one multiply-and-accumulate (MAC) operation with matrix elements received via an interface, the matrix elements including point cloud data from the system. Bangari et al fail to disclose a LiDAR system. Casas et al teaches a LiDAR system in which the processing of data is performed with a layered neural network to perform at least one multiply-and-accumulate (MAC) operation with matrix elements received via an interface, the matrix elements including point cloud data from the LiDAR system. It would have been obvious to one of ordinary skill in the art at the time of filing to apply the optical system of Bangari et al to the LiDAR system of Casas et al in order to optimize the LiDAR system. Bangari et al fail to disclose a Field Analog Vision module. However, it would have been obvious to one of ordinary skill in the art at the time of filing to implement any interface operative to receive elements of a first matrix and elements of a second matrix in the analog domain in order to implement the procedure of Bangari et al. Allowable Subject Matter Claim 2, 21, and 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 9/9/2026 have been fully considered but they are not persuasive. The interface of Bangari et al can broadly be any type of module. Finding a particular use is routine optimization. Further, the lack of conversion of analog-digital data appears critical to the applicant’s invention, and must be included in the independent claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E DUNAY whose telephone number is (571)270-1222. The examiner can normally be reached 7:00 am - 6:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James (Jong-Suk) Lee can be reached at 571-272-7044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER E DUNAY/ Primary Examiner, Art Unit 2875
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Prosecution Timeline

Feb 14, 2024
Application Filed
Jun 22, 2026
Non-Final Rejection mailed — §103, §112
Sep 09, 2026
Response Filed
Oct 15, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
90%
With Interview (+14.0%)
1y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 757 resolved cases by this examiner. Grant probability derived from career allowance rate.

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