DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 8-9, 12-14, 16-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, US PGPub 2016/0034413, in view of Ryu, US PGPub 2022/0012192.
With respect to claim 1, Park teaches a storage device comprising:
a memory configured to store first protocol data (par. 99, the memory of the second electronic device 120 stores ID_CODE) and first link data corresponding to a first host (par. 104, the memory of the second electronic device 120 stores linkup information); and
a switch (par. 215 and fig. 13, controller 225) connected to the memory (par. 215 and fig. 13, nonvolatile memory 221), and configured to:
read the first protocol data from the memory based on second protocol data being received from the first host (pars. 97-99 the second electronic device 120 receives the ID_CODE from the first electronic device 110 (first host) and compares it to previously stored ID_CODEs in its memory), and
perform a link-up process with the first host by using the first link data based on the first protocol data matching the second protocol data (pars. 99-105, the express linkup occurs when the received ID_CODE matches a stored ID_CODE, using the linkup information (first link data)).
Park fails to teach performing the link-up process to obtain second link data and link-up with the first host according to the second link data, based on the first protocol data and the second protocol data not matching, and store the second link data and the second protocol data of an established link in the memory based on link-up with the first host being completed.
Ryu teaches:
perform the link-up process to obtain second link data and link-up with the first host according to the second link data, based on the first protocol data and the second protocol data not matching (pars. 86-88 and fig. 6, when a change of protocol is required because the second protocol doesn’t match the first protocol, configuration (link) data is obtained and reconfiguration is performed), and
store the second link data and the second protocol data of an established link in the memory based on link-up with the first host being completed (pars. 116-122 and fig. 11, the configuration data CD3 is stored in the memory device. Pars. 93-96 describe the protocol data in the form of a packet DIN, which is also stored).
It would have been obvious to one of ordinary skill in the art, having the teachings of Park and Ryu before him before the earliest effective filing date, to modify the storage linking system of Park with the storage linking system of Ryu, in order to store more suitable configuration data, which may be a newer version of the determined protocol, as taught by Ryu in par. 121.
With respect to claim 2, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 1, wherein the switch is further configured to determine whether the first protocol data is stored in the memory based on the second protocol data being received from the first host, and compare the second protocol data with the first protocol data based on determining the first protocol data is stored in the memory (pars. 97-100 the second electronic device 120 receives the ID_CODE from the first electronic device 110 (first host) and compares it to previously stored ID_CODEs in its memory and performs the express linkup when there is a match).
With respect to claim 3, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 1, wherein the first link data indicates a preset value set in a previous link-up process (par. 99, “…when the first electronic device 110 is a widely used electronic device manufactured by a well-known manufacturer, the second electronic device 120 have preciously stored the value of the identification code ID_CODE to identify the first electronic device 110”), and
wherein the switch is further configured to perform the link-up process by using the preset value (pars. 99-105, the express linkup occurs when the received ID_CODE matches a stored ID_CODE).
With respect to claim 8, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 1, further comprising:
a controller configured to control a data operation based on a request from the first host (par. 215 and fig. 13, controller 225); and
a non-volatile memory configured to store, erase, or output data based on a control of the controller (par. 215 and fig. 13, nonvolatile memory 221).
With respect to claim 9, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 8, wherein the switch is further configured to, when link-up with the first host is completed, transmit a command of the first host to the controller (par. 134 and 138 and fig. 7, when the express linkup state is entered in step S450, the INFO is sent from the first electronic device 110 (first host) to the second electronic device 110, which contains the controller 224, as discussed above), and
wherein the controller is further configured to control the non-volatile memory based on the command (pars. 217-218, the controller stores the ID_CODEs in the non-volatile memory).
With respect to claim 12, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 1, wherein the memory is further configured to store third protocol data and third link data corresponding to a second host (par. 156, the first electronic device stores the linkup information INFO from the second electronic device. Par. 80 describes the second electronic device as a host), and
wherein the switch is further configured to perform a link-up process with the second host based on the third protocol data and the third link data (par. 155, the express linkup set based on the received linkup information INFO).
With respect to claim 13, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 12, wherein the switch is further configured to, based on fourth protocol data being received from the second host, read the third protocol data from the memory, and based on the third protocol data matching the fourth protocol data, read the third link data and perform a link-up process with the second host by using the third link data (pars. 149-155, and fig. 8, the first electronic device 110 receives the response signal S530, sees if the linkup information is stored, receives the linkup information INFO and performs the express linkup).
With respect to claim 14, Park a storage device comprising:
a non-volatile memory (par. 215 and fig. 13, nonvolatile memory 221) configured to store first protocol data (par. 104, the memory of the second electronic device 120 stores linkup information) and first link data corresponding to a first host in a switch region (par. 99, the memory of the second electronic device 120 stores ID_CODE, the first host being the first electronic device 110);
a switch connected with the first host (par. 215 and fig. 13, controller 225), and configured to, based on second protocol data being received from the first host, determine whether the first protocol data and the second protocol data match, and, based on determining the first protocol data and the second protocol data match, perform a link-up process by using the first link data to establish a link with the first host (pars. 97-105 second electronic device 120 receives the ID_CODE from the first electronic device 110 (first host) and compares it to previously stored ID_CODEs in its memory, and the express linkup occurs when the received ID_CODE matches a stored ID_CODE),
a controller configured to receive a packet from the first host over the link, and perform a data operation on the non-volatile memory based on the packet (par. 141, step S490, the second electronic device 120 stores the linkup information INFO received from the first electronic device 110 (first host), in the memory area. This process is further described in pars. 217-218, where the controller stores the ID_CODEs in a non-volatile memory).
Park fails to teach based on determining the first protocol data and the second protocol data do not match, perform a link-up process to obtain second link data, link-up with the first host according to the second link data, and record the second protocol data and the second link data in the switch region.
Ryu teaches:
based on determining the first protocol data and the second protocol data do not match, perform a link-up process to obtain second link data, link-up with the first host according to the second link data (pars. 86-88 and fig. 6, when a change of protocol is required because the second protocol doesn’t match the first protocol, configuration (link) data is obtained and reconfiguration is performed), and record the second protocol data and the second link data in the switch region (pars. 116-122 and fig. 11, the configuration data CD3 is stored in the memory device. Pars. 93-96 describe the protocol data in the form of a packet DIN, which is also stored).
It would have been obvious to one of ordinary skill in the art, having the teachings of Park and Ryu before him before the earliest effective filing date, to modify the storage linking system of Park with the storage linking system of Ryu, in order to store more suitable configuration data, which may be a newer version of the determined protocol, as taught by Ryu in par. 121.
With respect to claim 16, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 14,
wherein the second protocol data and third link data correspond to a second host, wherein the non-volatile memory is further configured to store third protocol data and the third link data corresponding to the second host in the switch region (par. 156, the first electronic device stores the linkup information INFO from the second electronic device. Par. 80 describes the second electronic device as a host), and
wherein the switch is further configured to, based on the second host being connected, perform a link-up process with the second host based on the third protocol data and the third link data (par. 155, the express linkup set based on the received linkup information INFO).
With respect to claim 17, Park and Ryu teach the limitations of the parent claim. Park further teaches the storage device of claim 14, wherein the controller is further configured to perform the data operation on a data region excluding the switch region in the non-volatile memory (par. 218, the nonvolatile memory stores the ID_CODEs).
With respect to claim 19, Park teaches an electronic system comprising:
a plurality of hosts (par. 14, the hosts, one of which is first electronic device 110, as described in par. 214);
a memory configured to store link data corresponding to at least one host of the plurality of hosts (par. 99, memory area to store ID_CODEs);
a switch (par. 215 and fig. 13, controller 225) configured to establish a link with the at least one host based on the link data, and receive a command and data from the at least one host while the link is established (pars. 97-100 the second electronic device 120 receives the ID_CODE from the first electronic device 110 (first host) and compares it to previously stored ID_CODEs in its memory and performs the express linkup when there is a match); and
a storage device (par. 214, storage device 220) configured to perform a data operation based on the command and the data (pars. 97-100 the second electronic device 120 receives the ID_CODE from the first electronic device 110 (first host) and compares it to previously stored ID_CODEs in its memory and performs the express linkup when there is a match).
Park fails to teach wherein the switch is further configured to perform a link-up process with a first host of the plurality of hosts to obtain first link data and link-up with the first host according to the first link data, based on the link data not comprising link data of the first host, and, based on a link with the first host being established, store the first link data of the established link in the memory.
Ryu teaches:
wherein the switch is further configured to perform a link-up process with a first host of the plurality of hosts to obtain first link data and link-up with the first host according to the first link data, based on the link data not comprising link data of the first host (pars. 86-88 and fig. 6, when a change of protocol is required because the second protocol doesn’t match the first protocol, configuration (link) data is obtained and reconfiguration is performed), and, based on a link with the first host being established, store the first link data of the established link in the memory (pars. 116-122 and fig. 11, the configuration data CD3 is stored in the memory device).
It would have been obvious to one of ordinary skill in the art, having the teachings of Park and Ryu before him before the earliest effective filing date, to modify the storage linking system of Park with the storage linking system of Ryu, in order to store more suitable configuration data, which may be a newer version of the determined protocol, as taught by Ryu in par. 121.
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Ryu, as applied to claims 1 and 3 above, in view of Cho et al., US PGPub 2023/0176989.
With respect to claim 4, Park and Ryu teach all limitation of the parent claim, but fail to teach wherein the switch is further configured to determine whether an order of states executed in the link-up process matches the reference order. Cho further teaches the storage device of claim 3, wherein the first link data indicates a reference order of states of the link-up process, and
wherein the switch is further configured to determine whether an order of states executed in the link-up process matches the reference order (pars. 49-50 determining whether the reference sequence is determined to match and the link is successful).
It would have been obvious to one of ordinary skill in the art, having the teachings of Park, Ryu and Cho before him before the earliest effective filing date, to modify the storage linking system of Park and Ryu with the storage linking system of Cho, in order to configure a link with parameters optimized for an operating environment at a current time point, and the performance of the PCIe interface may be improved, as taught by Cho in par. 85.
With respect to claim 5, Park, Ryu and Cho teach the limitations of the parent claims. Cho further teaches the storage device of claim 4, wherein the switch is further configured to re-execute the link-up process while performing the link-up process based on the order of states not matching the reference order (pars. 49-50, when the result of the comparison with the reference sequence is determined not to match, the PCIe controller may repeatedly adjust the PHY parameters until the result of comparison with the reference sequence is determined to match each other and the link is reconfigured).
With respect to claim 6, Park and Ryu teach all limitations of the parent claim, but fail to teach transmitting an identification signal to the first host, based on third protocol data being received from the first host in response to the identification signal determining whether the first protocol data and the third protocol data match; and based on determining the first protocol data and the third protocol data do not match, re-executing the link-up process. Cho further teaches the storage device of claim 1, wherein the switch is further configured to:
transmit an identification signal to the first host (par. 43, the storage device 40 and graphics processing device 50 exchange data, any of the data can be considered an identification signal, such as the lane number);
based on third protocol data being received from the first host in response to the identification signal determine whether the first protocol data and the third protocol data match (pars. 49-50, determining whether a changed PHY value at one of the devices still matches the previously stored PHY data); and
based on determining the first protocol data and the third protocol data do not match, re-execute the link-up process (pars. 44-50, when a PHY value changes (third protocol data) and therefore the new PHY value does not match the original PHY value (first protocol data), the PCIe controller reconfigures (re-executes) the link-up process).
It would have been obvious to one of ordinary skill in the art, having the teachings of Park, Ryu and Cho before him before the earliest effective filing date, to modify the storage linking system of Park and Ryu with the storage linking system of Cho, in order to configure a link with parameters optimized for an operating environment at a current time point, and the performance of the PCIe interface may be improved, as taught by Cho in par. 85.
With respect to claim 7, Park, Ryu and Cho teach the limitations of the parent claims. Cho further teaches the storage device of claim 6, wherein the switch is further configured to, based on a link being re-established with the first host, obtain third link data and record the third link data in the memory (par. 83, “When the link-up is successfully performed, states actually executed by the LTSSM, among the states 300 to 310, and an execution sequence thereof until the link-up is successfully performed may be stored in an internal memory of the PCIe controller as a reference sequence,” this data being the second link data, and the internal memory corresponding to the memory of the claim. Since this occurs after a link-up is successfully performed, it occurs after the re-executed link-up process that occurs in pars 44-50, as described above in the rejection of claim 6).
Claim(s) 11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and Ryu, as applied to claims 1, 14, and 17 above, in view of Moshayedi, US PGPub 2009/0327591.
With respect to claim 11, Park and Ryu teach the limitations of the parent claims. Park further teaches the storage device of claim 1, wherein the switch is further configured to store the second link data and the second protocol data in the memory (par. 225, the linkup information is stored in the memory cells of the nonvolatile memory 221). While it is likely the standard flash memory of Park is single level cell memory, Park fails to specifically disclose it is SLC memory. Moshayedi teaches storing frequently accessed data (corresponding to the second link data and second protocol data of Park) in a Single Level Cell (SLC) manner (par. 9).
It would have been obvious to one of ordinary skill in the art, having the teachings of Park, Ryu and Moshayedi before him before the earliest effective filing date, to modify the storage device of Park and Ryu with the storage device of Moshayedi, in order to store the second link data and the second protocol data in SLC memory, as SLC can be erased many more times than MLC flash, which makes it the logical choice for frequently accessed data, as taught by Moshayedi in pars. 6-9.
With respect to claim 18, Park and Ryu teach the limitations of the parent claims. Park further teaches the storage device of claim 17, wherein the controller is further configured to store the first protocol data and the first link data in the switch region (pars. 223-225, the identification codes and linkup data are stored in the memory cells of the nonvolatile memory 221), and perform the data operation in the data region (pars. 220-221, data is stored in the 3D memory array with stacked memory cells). Park fails to specifically disclose data stored to the switch region is stored is in a SLC manner, or data stored to the data region is stored is in an MLC manner. Moshayedi teaches storing frequently accessed data (corresponding to the first protocol data and first link data of Park) in a Single Level Cell (SLC) manner (par. 9), and static data (corresponding to the data operation) in a Multi-Level Cell (MLC) manner (par. 9).
It would have been obvious to one of ordinary skill in the art, having the teachings of Park, Ryu and Moshayedi before him before the earliest effective filing date, to modify the storage device of Park and Ryu with the storage device of Moshayedi, in order to store the first protocol data and first link data in SLC memory, as SLC can be erased many more times than MLC flash, which makes it the logical choice for frequently accessed data, and store data operation data in MLC memory, as MLC data is less expensive than SLC data, which makes it a logical choice for less frequently accessed data, as taught by Moshayedi in pars. 6-9.
Response to Arguments
Applicant's arguments filed 10/08/2025 have been fully considered but they are not persuasive. Applicant’s remarks on pages 7-9 are directed towards Park, Cho, and Moshayedi allegedly failing to teach “perform the link-up process to obtain second link data and link-up with the first host according to the second link data, based on the first protocol data and the second protocol data not matching, and store the second link data and the second protocol data of an established link in the memory based on link-up with the first host being completed.” These arguments are moot, as the new Ryu reference has been used to teach these amended limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cho, US PGPub 2024/0126663 teaches a link training and status state machine configured to perform a link-up. Qian et al., US Patent 10,237,819 teaches a link control process for an SSIC device.
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/RYAN DARE/Examiner, Art Unit 2132