DETAILED ACTION
This office action is in response to applicant’s amendment filed on May 11, 2026. Claims 1-17, and 19-21 are under consideration.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “a photonic integrated circuit located within the waveguide” as described in the specification.
Figs. 5-12 appear to show different embodiments of the disclosed hermetic package for a PIC and laser die. Each figure has a “housing layer 503/604/704/804/904/1004/1105/1204. Each housing layer contains three small squares (not labeled) and one long rectangle 504/606//705/806/906/1006/1106/1206. Each long rectangle is labeled with “photonic integrated circuit” or “waveguide”. The Specification designates 705/806/906/1006/1206 as waveguide may include a photonic integrated circuit. If the photonic integrated circuit and waveguide are contained in the same housing layer, then the figures should clearly show and label both components.
Fig. 7 contains inaccurate details:
Laser cavity 703 is not within laser die 702. It is not clear how a laser cavity not integrated in the laser die 702 layer would function and operate, since “laser die” is commonly known as the laser chip in the art.
“[P]illars 708a, 708b may be utilized to set a height of a laser die (not shown) relative a photonic integrated circuit (Pgpub 2024/0295690, Para [0088]). The laser die 702 is shown and the pillars are not providing height alignment because the laser cavity 703 appears to be offset from the housing laser 704.
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: reference number ‘1106’ in Fig. 11 is not described in the Specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17, and 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “waveguide” (claims 1, 8, and 15) requires a guiding core and a cladding layer for total internal refraction of the optical signal to remain within the core. The waveguide (504/606//705/806/906/1006/1106/1206) shown in the Figs. 5-12 does not show this guiding features. Element 609 is disclosed as the silicon dioxide cladding element, but it is unclear whether 609 provides cladding for waveguide 606 or whether 609 is equivalent as 604.
The limitation “a photonic integrated circuit located within the waveguide” (claims, 1, 8, and 15) is not clearly disclosed for the understanding of the light path from the laser cavity through the waveguide and/or photonic integrated circuit without obstructions from the electronic components (e.g., conductors, vias, driver circuit). The figures and the Specification do not provide any clarity to the limitation noted above.
For examination purposes, the examiner shall consider the limitation to recite—a photonic integrated circuit located within the waveguide layer--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Lebby (US 10,162,111 B1, herein “Lebby”) in view of Osenbach et al. (US 9,784,933 B2, herein “Osenbach”).
Regarding claim 1, Lebby discloses an apparatus, comprising:
a housing layer (semiconductor wafer 130);
a waveguide layer (growth of epitaxial layers 132 to define laser/waveguide structures, Col. 8, lines 52-55);
a photonic integrated circuit (emitter/detector 136, modulator 138, mux/demux 140) located within the waveguide layer (132);
a laser die (36) to implement at least one laser in conjunction (together) with the photonic integrated circuit (detector, modulator 138, mux/demux 140, Lebby discloses the laser can be integrated in wafer 30 (Col. 6, lines 4-6) or a separate component (die) as shown in Fig. 4C, wherein the photonic devices are in electrical communication via electrical interconnect layers 34, thus the photonic components are in conjunction with the laser die (Col. 6, lines 20-34); wherein a vertical height of the laser die relative to an input of the photonic integrated circuit is set such that the laser die is aligned with respect to the input of the photonic integrated circuit and configured to emit an optical signal that couples into the photonic integrated circuit (Fig. 4C-4D shows the photonic components are aligned at the same height having the waveguide layer running through components at the same height. The spot size converter 42 is in optical alignment with spherical lens formed in depression 46 which suggests the spot size converter receives optical signal from emitter through modulator and through mux/demux which are in alignment with spot size converter 42);
a cover wafer (lid 14 is formed of semiconductor or metal, Abstract) attached to the housing layer (130), the cover wafer (lid 14) to hermetically cover the waveguide and the laser die; and
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a base substrate (base 12) attached to the laser die and the housing layer (base 12 is between the laser die and the substrate 130).
However, Lebby does not disclose the base substrate comprising a through-wafer via element coupled to the laser die to provide electrical coupling for the laser die.
Osenbach teaches a substrate (210 supporting PIC-SIP shown in Top View in Fig. 7B) having a base substrate (630/620/610) attached to the laser die (InP photonics 330) and the housing layer (605), the base substrate (630/620/610) comprising a through-wafer via element (etched second dielectric layer 620 facilitate forming one or more vias that provide an electrical connection to a metal interconnect 615, Col. 11, lines 1-9, Fig. 6C).
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the Lebby’s dielectric insulator and interconnect layers (Fig. 4A) can be modified to be formed on the base layer as shown by Osenbach such that through-wafer vias can be etched through the dielectric layer. One motivation for electrically connecting the photonic integrated circuits with vias is to shorten the signal paths which lower parasitic effects which improve signal integrity at high frequencies.
Claim 2. Lebby in view of Osenbach (herein “Lebby/Osenbach”) teach the invention of claim 1 and Lebby further discloses the cover wafer comprises a pocket (chamber 64 in Fig. 4L) to house the laser die (emitter 36).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lebby/Osenbach as applied to claim 1 and claim 15 above, and further in view of Ohashi et al. (US 2019/0211242 A1, herein “Ohashi”).
Lebby/Osenbach teach the invention of claim 1, Osenbach further teaches the cover wafer is attached to the housing layer via an epoxy layer (Osenbach: Col. 9, lines 13-16). However, Lebby/Osenbach do not explicitly teach the epoxy layer is transparent.
Ohashi teaches bonding substrates using adhesive known in the art as IZO film, indium zinc oxide film, bonded to a polymer layer (Para [0051]). Indium-zinc oxide is a transparent ceramic material. Indium-zinc is oxygenated by sputtering argon to the indium-zinc ceramic substrate; thus, the resulting substrate is a doped-oxide. Ohashi further teaches using epoxy as an additive to the photosensitive adhesive composition (Para [0039]- [0041]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention for Lebby/Osenbach to select a transparent epoxy as taught by Ohashi for the purpose of allowing light signals to pass. One would be motivated to select a transparent epoxy to allow light to pass through the hermetically sealed cavity without obstruction. Furthermore, the doped oxide layer alters electrical properties of the bonded layer and provides corrosion protection at the bond side of the oxide layer.
Claims 7-8, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lebby/Osenbach as applied to claim 1 above, and further in view of Amberger et al. (WO 2023/020735 A1, herein “Amberger”).
Regarding claim 7, Lebby/Osenbach teach the invention of claim 1, but Lebby/Osenbach does not teach the base substrate further comprises an emission window.
Amberger teaches a packaging arrangement wherein the base substrate (4) comprises an emission window (6) for directing light from laser source (12a) out through the emission window (6) (see machine translation, on page 11, first full paragraph).
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention modify the base substrate of Lebby/Osenbach with the base substrate (4) provided with an emission window, as shown in Amberger’s integrated package. One motivation would be to providing an emission window on the base substrate to facilitate vertical backside optical coupling and easy co-packing with electronics since the emission window enables the PIC to face down or interface directly onto silicon interposers and host processors via flip-chip bonding.
Regarding claim 8, Lebby discloses an apparatus, comprising:
a housing layer (semiconductor wafer 130);
a waveguide layer (growth of epitaxial layers 132 to define laser/waveguide structures, Col. 8, lines 52-55);
a photonic integrated circuit (emitter/detector 136, modulator 138, mux/demux 140) located within the waveguide layer (132);
a laser die (36) to implement at least one laser in conjunction (together) with the photonic integrated circuit (detector, modulator 138, mux/demux 140, Lebby discloses the laser can be integrated in wafer 30 (Col. 6, lines 4-6) or a separate component (die) as shown in Fig. 4C, wherein the photonic devices are in electrical communication via electrical interconnect layers 34, thus the photonic components are in conjunction with the laser die (Col. 6, lines 20-34); wherein a vertical height of the laser die relative to an input of the photonic integrated circuit is set such that the laser die is aligned with respect to the input of the photonic integrated circuit and configured to emit an optical signal that couples into the photonic integrated circuit (Fig. 4C-4D shows the photonic components are aligned at the same height having the waveguide layer running through components at the same height. The spot size converter 42 is in optical alignment with spherical lens formed in depression 46 which suggests the spot size converter receives optical signal from emitter through modulator and through mux/demux which are in alignment with spot size converter 42);
a cover wafer (lid 14 is formed of semiconductor or metal, Abstract) attached to the housing layer (130), the cover wafer (lid 14) to provide hermetic covering to the waveguide and the laser die; and
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a base substrate (base 12) attached to the laser die and the housing layer (base 12 is between the laser die and the substrate 130).
However, Lebby does not disclose the base substrate comprising a through-wafer via element coupled to the laser die to provide electrical coupling for the laser die.
Osenbach teaches a substrate (210 supporting PIC-SIP shown in Top View in Fig. 7B) having a base substrate (630/620/610) attached to the laser die (InP photonics 330) and the housing layer (605), the base substrate (630/620/610) comprising a through-wafer via element (a metal connection strip that provides an electrical connection to the metal interconnect 615, Col. 11, lines 1-9, Fig. 6C).
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the Lebby’s dielectric insulator and interconnect layers (Fig. 4A) can be modified to be formed on the base layer as shown by Osenbach such that through-wafer vias can be etched through the dielectric layer. One motivation for electrically connecting the photonic integrated circuits with vias is to shorten the signal paths which lower parasitic effects which improve signal integrity at high frequencies.
Lebby/Osenbach does not teach the base substrate further comprises an emission window adjacent to the housing layer.
Amberger teaches a packaging arrangement wherein the base substrate (4) comprises an emission window (6) adjacent to the housing layer (13) for directing light from laser source (12a) out through the emission window (6) (see machine translation, on page 11, first full paragraph).
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention modify the base substrate of Lebby/Osenbach with the base substrate (4) provided with an emission window, as shown in Amberger’s integrated package. One motivation would be to providing an emission window on the base substrate to facilitate vertical backside optical coupling and easy co-packing with electronics since the emission window enables the PIC to face down or interface directly onto silicon interposers and host processors via flip-chip bonding.
Claim 10. Lebby/Osenbach/Amberger teach the invention of claim 8, and Lebby further discloses the cover wafer comprises a pocket (chamber 64 in Fig. 4L) to house the laser die (emitter 36).
Claims 11. Lebby/Osenbach/Amberger teach the invention of claim 8, and Lebby further discloses the emitter (36) includes vertical cavity surface emitting laser (VCSEL) (Col. 6, lines 34-42).
Claims 9, 12-13, 15-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lebby/Osenbach in view of Amberger as applied to claim 8 above, and further in view of Venkatesan et al. (US 2023/0228953 A1, herein “Venkatesan”).
Regarding claims 9, Lebby/Osenbach in view of Amberger (herein “Lebby/Osenbach/Amberger”) teach the invention of claims 8, but Lebby/Osenbach/Amberger do not teach at least one pillar located in a trench area of the base substrate to set the vertical height of the laser die relative to the input of the photonic integrated circuit. Lebby/Osenbach/Amberger do not teach the metal connection element is provided in the trench area of the base substrate and adjacent to the at least one pillar.
Venkatesan teaches a self-aligned photonic waveguide circuit. Fig. 1 shows a PIC chip (102) wherein a cavity (148) is formed on a base substrate (101). Alignment pillar (134) is formed within the cavity to facilitate mounting and alignment of optical devices in alignment with, for example, the patterned planar waveguides (144). Venkatesan also teaches the optical device(s) may be a semiconductor laser (Para [0004]), which would need a power source to driving said laser, thus implies a metal connection element is provided for the laser adjacent to the pillar.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the pillars in Venkatesan PIC chip would be modifiable to the packaged photonic integrated substrate of Lebby/Osenbach/Amberger. The pillars in Venkatesan can be provided in the cavity (320) where laser (410) is mounted (Osenbach: Fig. 4). Lebby/Osenbach/Amberger recognizes vertical offset for providing optical alignments. Lebby shows in Fig. 4H negative vertical offset is provided for spherical lens, isolator, and lens 58 to maintain optical alignment with the waveguide layer and photonic components. Therefore, it would have been obvious to one having ordinary skill in the art to recognize positive vertical offset provided by pillars in Venkatesan would be provide positive vertical alignment in the cavity of Lebby/Osenbach/Amberger’s device. One motivation for aligning the laser beam emission with the waveguide layer is to provide efficient optical coupling.
Claims 12-13. Venkatesan further teaches a silicon dioxide cladding element (138) on top of the base substrate. The intermetal dielectric layer (136) is formed from electrically insulating material such as silicon dioxide (Paras [0058] and [0079]). Furthermore, Venkatesan teaches electrical contacts (630 in Fig. 6B) are formed at the top surface (605) to accommodate electrical connections to mounted devices and to other locations on the interposer-based PIC, via wire bonding or other metallization schemes. Electrical contacts (630) may also facilitate mounting of the interposer to another interposer, sub-mount, or other device (Para [0109]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to recognize the material design and construction as recited in claims 12-13 are known semiconductor manufacturing material and processes. One would be motivated to use silicon dioxide as the cladding element because silicon dioxide is transparent with a lower refractive index than silicon waveguide, it’s a known dielectric material, and thermally resistant. Furthermore, Venkatesan teaches the motivation for providing the metal connection strip on top of the silicon dioxide cladding element and on top of the base substrate to facilitate mounting of the interposer to another interposer, sub-mount, or other device (Para [0109]).
Regarding claims 15 and 19, Lebby discloses an apparatus, comprising:
a housing layer (semiconductor wafer 130);
a waveguide layer (growth of epitaxial layers 132 to define laser/waveguide structures, Col. 8, lines 52-55);
a photonic integrated circuit (emitter/detector 136, modulator 138, mux/demux 140) located within the waveguide layer (132);
a laser die (36) to implement at least one laser in conjunction (together) with the photonic integrated circuit (detector, modulator 138, mux/demux 140, Lebby discloses the laser can be integrated in wafer 30 (Col. 6, lines 4-6) or a separate component (die) as shown in Fig. 4C, wherein the photonic devices are in electrical communication via electrical interconnect layers 34, thus the photonic components are in conjunction with the laser die (Col. 6, lines 20-34); wherein a vertical height of the laser die relative to an input of the photonic integrated circuit is set such that the laser die is aligned with respect to the input of the photonic integrated circuit and configured to emit an optical signal that couples into the photonic integrated circuit (Fig. 4C-4D shows the photonic components are aligned at the same height having the waveguide layer running through components at the same height. The spot size converter 42 is in optical alignment with spherical lens formed in depression 46 which suggests the spot size converter receives optical signal from emitter through modulator and through mux/demux which are in alignment with spot size converter 42);
a cover wafer (lid 14 is formed of semiconductor or metal, Abstract) attached to the housing layer (130), the cover wafer (lid 14) to provide hermetic covering to the waveguide and the laser die; and
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a base substrate (base 12) attached to the laser die and the housing layer (base 12 is between the laser die and the substrate 130).
However, Lebby does not disclose the base substrate attached to the laser die and the housing layer, wherein the base layer comprises a trench area and a metal connection element coupled to the laser die.
Osenbach teaches a substrate (210 supporting PIC-SIP shown in Top View in Fig. 7B) having a base substrate (630/620/610) attached to the laser die (InP photonics 330 or 410) set within cavity (320), the base substrate (630/620/610) comprising a through-wafer via element (a metal connection strip that provides an electrical connection to the metal interconnect 615, Col. 11, lines 1-9, Fig. 6C).
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the Lebby’s dielectric insulator and interconnect layers (Fig. 4A) can be modified to be formed on the base layer as shown by Osenbach such that through-wafer vias can be etched through the dielectric layer. One motivation for electrically connecting the photonic integrated circuits with vias is to shorten the signal paths which lower parasitic effects which improve signal integrity at high frequencies.
Lebby/Osenbach do not teach the base substrate further comprises an emission window adjacent to the housing layer.
Amberger teaches a packaging arrangement wherein the base substrate (4) comprises an emission window (6) adjacent to the housing layer (13) for directing light from laser source (12a) out through the emission window (6) (see machine translation, on page 11, first full paragraph).
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention modify the base substrate of Lebby/Osenbach with the base substrate (4) provided with an emission window, as shown in Amberger’s integrated package. One motivation would be to providing an emission window on the base substrate to facilitate vertical backside optical coupling and easy co-packing with electronics since the emission window enables the PIC to face down or interface directly onto silicon interposers and host processors via flip-chip bonding.
Lebby/Osenbach/Amberger do not teach at least one pillar located in a trench area of the base substrate to set the vertical height of the laser die relative to the input of the photonic integrated circuit. Lebby/Osenbach/Amberger do not teach the metal connection element is provided in the trench area of the base substrate and adjacent to the at least one pillar.
Venkatesan teaches a self-aligned photonic waveguide circuit. Fig. 1 shows a PIC chip (102) wherein a cavity (148) is formed on a base substrate (101). Alignment pillar (134) is formed within the cavity to facilitate mounting and alignment of optical devices in alignment with, for example, the patterned planar waveguides (144). Venkatesan also teaches the optical device(s) may be a semiconductor laser (Para [0004]), which would need a power source to driving said laser, thus implies a metal connection element is provided for the laser adjacent to the pillar.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the pillars in Venkatesan PIC chip would be modifiable to the packaged photonic integrated substrate of Lebby/Osenbach/Amberger. The pillars in Venkatesan can be provided in the cavity (320) where laser (410) is mounted (Osenbach: Fig. 4). Lebby/Osenbach/Amberger recognizes vertical offset for providing optical alignments. Lebby shows in Fig. 4H negative vertical offset is provided for spherical lens, isolator, and lens 58 to maintain optical alignment with the waveguide layer and photonic components. Therefore, it would have been obvious to one having ordinary skill in the art to recognize positive vertical offset provided by pillars in Venkatesan would be provide positive vertical alignment in the cavity of Lebby/Osenbach/Amberger’s device. One motivation for aligning the laser beam emission with the waveguide layer is to provide efficient optical coupling.
Claim 16. Lebby/Osenbach/Amberger/Venkatesan teach the invention of claim 15, and Lebby further discloses the cover wafer comprises a pocket (chamber 64 in Fig. 4L) to house the laser die (emitter 36).
Claim 20. Lebby/Osenbach/Amberger/Venkatesan teach the invention of claim 15, and Lebby further discloses the emitter (36) includes vertical cavity surface emitting laser (VCSEL) (Col. 6, lines 34-42).
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lebby/Osenbach/Amberger/Venkatesan as applied to claims 12 and 15 above, and further in view of Ohashi.
Lebby/Osenbach/Amberger/Venkatesan teach the invention of claim 12, but the combined teaching is silent to the cover wafer is attached to the housing layer and the silicon dioxide cladding element via a bonding oxide layer.
Ohashi teaches bonding substrates using adhesive known in the art as IZO film, indium zinc oxide film, bonded to a polymer layer (Para [0051]). Indium-zinc oxide is a transparent ceramic material. Indium-zinc is oxygenated by sputtering argon to the indium-zinc ceramic substrate; thus, the resulting substrate is a doped-oxide. Ohashi further teaches using epoxy as an additive to the photosensitive adhesive composition (Para [0039]- [0041]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention for Lebby/Osenbach/Amberger/Venkatesan to select a transparent epoxy as taught by Ohashi for the purpose of allowing light signals to pass. One would be motivated to select a transparent epoxy to allow light to pass through the hermetically sealed cavity without obstruction. Furthermore, the doped oxide layer alters electrical properties of the bonded layer and provides corrosion protection at the bond side of the oxide layer.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lebby/Osenbach as applied to claim 1 above, and further in view of Venkatesan.
Lebby/Osenbach teach the invention of claim 1, but Lebby/Osenbach do not teach at least one pillar located in a trench area of the base substrate to set the vertical height of the laser die relative to the input of the photonic integrated circuit.
Venkatesan teaches a self-aligned photonic waveguide circuit. Fig. 1 shows a PIC chip (102) wherein a cavity (148) is formed on a base substrate (101). Alignment pillar (134) is formed within the cavity to facilitate mounting and alignment of optical devices in alignment with, for example, the patterned planar waveguides (144). Venkatesan also teaches the optical device(s) may be a semiconductor laser (Para [0004]), which would need a power source to driving said laser, thus implies a metal connection element is provided for the laser adjacent to the pillar.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the pillars in Venkatesan PIC chip would be modifiable to the packaged photonic integrated substrate of Lebby/Osenbach/Amberger. The pillars in Venkatesan can be provided in the cavity (320) where laser (410) is mounted (Osenbach: Fig. 4). Lebby/Osenbach/Amberger recognizes vertical offset for providing optical alignments. Lebby shows in Fig. 4H negative vertical offset is provided for spherical lens, isolator, and lens 58 to maintain optical alignment with the waveguide layer and photonic components. Therefore, it would have been obvious to one having ordinary skill in the art to recognize positive vertical offset provided by pillars in Venkatesan would be provide positive vertical alignment in the cavity of Lebby/Osenbach/Amberger’s device. One motivation for aligning the laser beam emission with the waveguide layer is to provide efficient optical coupling.
Response to Arguments
Applicant’s arguments with respect to claims 1-17 and 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bovington (US 2022/0075131 A1) teaches pillars and spacers for vertically aligning the laser die to couple into the photonic integrated circuit input.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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