DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement(s) filed on February 14, 2024 have all been considered and made of record (note the attached copy(ies) of form PTO-1449).
Drawings
Fourteen sheets of drawings were filed on February 14, 2024 and have been accepted by the examiner.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1, 2, 7, 8, 10, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gallup et al. (US 2005/0063642 A1, herein “Gallup”).
Regarding claim 1, Gallup discloses an apparatus (structure 100), comprising:
a housing layer (sub-mount wafer 120) comprising a waveguide (“wafer is made of silicon and/or other materials that are transparent to the wavelength of the optical signals from lasers 110”, [0024]), the waveguide including a photonic integrated circuit (“wafer 120 also includes circuit elements such as bonding pads 122 and electrical traces or vias that connect lasers 110 to external terminals”);
a laser die to implement at least one laser in conjunction with the photonic integrated circuit (monitor chip 515 in Fig. 6 for monitoring of the laser in the laser 510 to ensure consistent output, Para [0045]);
a cover wafer (cap wafer 130) attached to the housing layer (bonded to sub-mount wafer 120, Para [0029]), the cover wafer to hermetically cover the photonic integrated circuit and the laser die (Para [0020]); and
a base substrate attached to the laser die and the housing layer (Para [0023]), the base substrate comprising a through-wafer via element coupled to the laser die to provide electrical coupling for the laser die (Para [0024]).
PNG
media_image1.png
268
713
media_image1.png
Greyscale
Claim 2. Gallup discloses the cover wafer (130) comprises a pocket (pocket 140) to house the laser die (110).
Claim 7. Gallup discloses the sub-mount wafer is transparent to laser signals, thus, the entire surface is an emission window.
Claims 8. Gallup discloses an apparatus, comprising:
a housing layer (sub-mount wafer 120) comprising a waveguide (“wafer is made of silicon and/or other materials that are transparent to the wavelength of the optical signals from lasers 110”, [0024]), the waveguide including a photonic integrated circuit (“wafer 120 also includes circuit elements such as bonding pads 122 and electrical traces or vias that connect lasers 110 to external terminals”);
a laser die to implement at least one laser in conjunction with the photonic integrated circuit (monitor chip 515 in Fig. 6 for monitoring of the laser in the laser 510 to ensure consistent output, Para [0045]);
a cover wafer (cap wafer 130) attached to the housing layer (bonded to sub-mount wafer 120, Para [0029]), the cover wafer to provide hermetic covering to the photonic integrated circuit and the laser die (Para [0020]);
a base substrate attached to the laser die and the housing layer (Para [0023]), the base substrate comprising an emission window (560 in Fig. 5) adjacent to the housing layer; and
a metal connection strip to electrically couple the laser die (bonding pads 115, 122, and the associated wire in Fig. 1).
Claim 10. Gallup discloses the cover wafer (cap wafer 130) comprises a pocket to house the laser die (110).
Regarding claim 15. Gallup discloses an apparatus (Fig. 7), comprising:
a housing layer (sleeve 720) comprising a waveguide (sub-mount 520 is made of silicon and/or other materials that are transparent to the wavelength of the optical signals from lasers 110, [0024]), the waveguide including a photonic integrated circuit (sub-mount 520 also includes circuit elements such as bonding pads and electrical traces or vias that connect lasers 110 to external terminals, refer to Fig. 1 as the embodiment of Fig. 7 does not show the details) and a laser die (510);
a base substrate (520) attached to the laser die (510) and the housing layer (sleeve 720), the base substrate (520) comprising an emission window (post 560) adjacent to the housing layer (720); and
a metal connected element coupled to the laser die (through-wafer element coupled to the laser die to provide electrical coupling for the laser die (Para [0024]).
Claim 16. Gallup discloses the cover wafer (530) comprises a pocket to house the laser die (540).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gallup in view of Ohashi et al. (US 2019/0211242 A1, herein “Ohashi”).
Regarding claims 4-6, and 17 Gallup discloses the invention of claim 1 and claim 15, but Gallup is silent to the cover wafer is attached to the housing layer via a bonding using a transparent doped metal oxide layer.
Ohashi teaches a photosensitive adhesive composition wherein the first substrate is bonded to a second substrate which includes a silicon wafer coated with indium zinc oxide film, also known as IZO film bonded to a polymer layer (Para [0051]). Indium-zinc is a transparent ceramic material. Indium-zinc is oxygenated by sputtering Argon to the Indium-zinc ceramic substrate, thus the resulting substrate is a doped oxide.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adopt the bonding technique as disclosed by Ohashi to the bonding of the cap wafer and sub-mount wafer in Gallup invention. One motivation for using IZO film adhesive the transparency of Indium Zinc Oxide, the doped oxide layer alters electrical properties of the bonded layer, and most importantly is the corrosion protection at the bond site of an oxide layer.
Regarding claim 3, Gallup in view Ohashi teach a transparent adhesive layer and Ohashi further teaches using epoxy as an additive to the photosensitive adhesive composition (Para [0039]-[0041]). The added epoxy ingredient improves the versatility of Ohashi’s photosensitive adhesive composition since one advantage of an epoxy is strong bonding, low shrinkage, and environmental resistance which are all benefits for photonics manufacturing.
Claims 9, 11-14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gallup in view of Venkatesan et al. (US 2023/0228953 A1, herein “Venkatesan”).
PNG
media_image2.png
618
440
media_image2.png
Greyscale
Regarding claims 9 and 18-19, Gallup discloses the invention of claim 8 and claim 15, but Gallup does not disclose at least one pillar located in a trench area of the base substrate to set a height of the laser die relative to the photonic integrated circuit. The metal connection element (electrical contacts 131) is provided in the trench area (148) of the base substrate and adjacent to the at least one pillar (134).
Venkatesan teaches a self-aligned photonic waveguide circuit. Fig. 1 shows a PIC chip (102) wherein a cavity (148) is formed on a base substrate (101). Alignment pillar (134) is formed within the cavity to facilitate mounting and alignment of optical devices in alignment with, for example, the patterned planar waveguides (144). Venkatesan also teaches the optical devices may be a semiconductor laser (Para [0004]), which would need a power source to driving said laser.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the pillars in Venkatesan PIC chip would be modifiable to the laser mount in Gallup to change the emission direction of the laser (110). By providing vertical and horizontal alignments, as taught by Venkatesan, the PIC device can reduce in size and not rely on beam deflector to redirect the emission beam. One motivation for aligning the laser beam emission horizontally and vertically to integrate directly to planar waveguides and electrical interconnect layer.
Regarding claims 11 and 20, Gallup discloses the laser in claim 8 and claim 15, however, Gallup does not explicitly disclose the laser has a cavity.
Venkatesan indirectly teach the laser that is compatible with the PIC shown in Figs. 1A-1B can be a semiconductor laser fabricated from gallium arsenide and indium phosphide materials (Para [0004]). Thus, Venkatesan indirectly teaches the semiconductor laser compatible with the PIC device comprises a laser cavity.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the taught gallium arsenide and indium phosphide laser in Venkatesan disclosure would necessarily comprise a laser cavity because the cavity is essential for light amplification and oscillation. The cavity confine light, allowing reflections to build up laser emission within the semiconductor structure.
Claims 12-13. Venkatesan further teaches a silicon dioxide cladding element (138) on top of the base substrate. The intermetal dielectric layer (136) is formed from electrically insulating material such as silicon dioxide (Paras [0058] and [0079]). Furthermore, Venkatesan teaches electrical contacts (630 in Fig. 6B) are formed at the top surface (605) to accommodate electrical connections to mounted devices and to other locations on the interposer-based PIC, via wire bonding or other metallization schemes. Electrical contacts (630) may also facilitate mounting of the interposer to another interposer, sub-mount, or other device (Para [0109]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the material design and construction as recited in claims 12-13 are known semiconductor manufacturing material and processes. One would be motivated to use silicon dioxide as the cladding element because silicon dioxide is transparent with a lower refractive index than silicon waveguide, it’s a known dielectric material, and thermally resistant. Furthermore, Venkatesan teaches the motivation for providing the metal connection strip on top of the silicon dioxide cladding element and on top of the base substrate to facilitate mounting of the interposer to another interposer, sub-mount, or other device (Para [0109]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gallup in view of Venkatesan as applied to claim 12 above, and further in view of Ohashi.
Gallup in view of Venkatesan teach the invention of claim 12 and Gallup further teaches bonding the sub-mount wafer (120) to the cap wafer ( 130) with an adhesive (Para [0029]). However, Gallup in view of Venkatesan is silent to the adhesive is an oxide layer.
Ohashi teaches a photosensitive adhesive composition wherein the first substrate is bonded to a second substrate which includes a silicon wafer coated with indium zinc oxide film, also known as IZO film bonded to a polymer layer (Para [0051]). Indium-zinc is a transparent ceramic material. Indium-zinc is oxygenated by sputtering Argon to the Indium-zinc ceramic substrate, thus the resulting substrate is a doped oxide.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adopt the bonding technique as disclosed by Ohashi to the bonding of the cap wafer and sub-mount wafer in the invention as taught by Gallup in view of Venkatesan. One motivation for using IZO film adhesive the transparency of Indium Zinc Oxide, the doped oxide layer alters electrical properties of the bonded layer, and most importantly is the corrosion protection at the bond site of an oxide layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874