The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim(s) 1-20 has/have been examined.Claim(s) 1-20 have been rejected.
Response to Arguments
The arguments submitted February 26, 2026 have been fully considered but are not persuasive.
Regarding the 112a rejection, Applicant has argued that the term “thimbles” refers to ejector pins as described in the specification; Applicant argues that “thimbles” and “ejector pins” perform identical structural and functional roles. The examiner respectfully disagrees. The words "thimble" and "ejector pin" are not identical words. While the scope of each may be very similar, two words that are different cannot have exactly identical meanings at all levels. Whether one term encompasses the other or how their scopes may overlap is unclear. Applicant may submit a dictionary definition and attest to that definition. Absent a dictionary definition, arguments based on assertions of how one of ordinary skill in the art would define a term are not persuasive. Therefore the term "thimble", having not been described in the specification or the claims as originally filed, lacks a clear written description. The examiner recommends simply reciting "ejector pins" which has clear support in the specification and an allegedly identical scope.
Regarding the 103 rejection, Applicant argues that Bhatia uses BMC to load firmware from an external SD card to recover its operation and Bhatia does not make use of a test interface. The examiner notes that this aspect of the claim is addressed using secondary reference Wang, which teaches use of an interface that is used in BIOS testing.
Regarding the use of official notice, Applicant argues that the use of official notice directed to electrical connector pads is insufficient because the claimed test pads are specifically for use with a test connector on a test fixture during testing. The examiner respectfully disagrees that this is a deficiency in the rejection. Bhatia teaches a connector, while Wang teaches a test fixture used for testing. While the official notice is directed to generic PCB pads, the implementation of these generic PCB pads in a connection to a test fixture is obvious due to the description of the connection and test fixture in references Bhatia and Wang.
Applicant argues that the use of official notice directed to electrical connector pads is insufficient because the use of test pads for providing startup data during memory testing are specific pads and their configuration goes beyond general knowledge of connector pads. The examiner respectfully disagrees. The arguments are directed to limitations not found in the claims. During prosecution claims are given their broadest reasonable interpretation in view of the specification. As described in the rejection, generic pads are well known in the art, and the specific use of the generic pads, including testing usage which causes the pads to be test pads, is addressed by other references in the rejection.
Applicant argues that the use of official notice directed to electrical connector pads is insufficient because the test interface is designed for temporary contact during testing, not permanent connectivity, which is a different structure. The examiner respectfully disagrees.
The specification describes the test pads as flat metal pads (paragraph 69) that may be of most any shape (paragraph 70). While the test pads may be covered and flexibly arranged (paragraph 71), these limitations are not recited in the claim.
Absent further limitation in the specification, the claimed test pads are interpreted as being connective pads which are used during testing.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 13, 19 and 20 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Note that dependent claims not specifically addressed below inherit the deficiency of the parent claim and do not remedy the issue.
Claims 13 and 19 recite language of a test connector comprising thimbles. The term "thimble" is not recited in the specification or in the claims as originally filed. It lacks written description.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 8, 11, 13-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bhatia (PG-PUB 2025/0028601) in view of Wang (Foreign Patent TW 201310229) (Note that citations to Wang use the attached English translation of the reference) and Wikipedia’s Boot ROM (historical version published July 22, 2023).
Regarding claim 1, Bhatia discloses a memory apparatus, comprising:
a main circuit board comprising an interface configured to receive first startup data (Figure 1, host 180 has an interface to BMC 102); and
a memory controller disposed on the main circuit board and connected to the interface (Figure 1, the memory 184 and its associated controller are disposed on the host and connected to the firmware images accessible by the BMC), wherein the memory controller stores second startup data (Figure 1, storage 185 stores active and recovery images 191), and
the memory controller is configured to:
attempt to acquire the second startup data (see abstract, an initial boot is attempted from active firmware image);
in response to determining that acquiring the second startup data fails, acquire the first startup data through the interface (paragraph 58, if active and recovery BIOS images fail to boot, obtain a BIOS image from eMMC card or SD card, this data is obtained through the BMC interface as in Figure 1); and
perform an initialization operation on the memory apparatus according to the first startup data (paragraph 58, the BIOS image from eMMC card or SD card is flashed onto active and recovery partitions of the SPI flash storage for use). wherein the initialization operation comprises executing a memory program (paragraphs 26 and 27, a BIOS performs a POST and runs other UEFI boot services) and a bootloader to complete system initialization (paragraph 28, bootstrap loader is read which loads an OS into memory).
Bhatia does not expressly disclose the memory apparatus wherein the interface is a test interface for testing.
Wang teaches a test fixture having a BMC that can control the switching between a main BIOS and a backup BIOS for performing for testing BIOS (first few paragraphs).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the firmware failover system disclosed by Bhatia such that the host is in contact connection with a test connector on a test fixture having a BMC, as taught by Wang. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, testing of BIOS allows for confirmation of the correct functionality of the BIOS, and use of a test fixture to do so may save time when performing BIOS testing (Wang, third paragraph).
Bhatia does not expressly disclose the memory apparatus wherein the interface comprises a plurality of pads disposed on the main circuit board and configured for contact connection with a connector on a fixture. Bhatia teaches that the host is connected to BMC via USB (Figure 1, paragraph 21).
The examiner has taken official notice that it is well known in the art for a USB connector to include pads for electrical linking to a PCB (see, for example, NPL from StackExchange describing soldering USB port pads). This noticed fact has not been argued, only the sufficiency of the fact with respect to the scope of the claim.
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware loading disclosed by Bhatia such that USB connection to a test fixture BMC is done via conductive pads, as is well known in the art. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, conductive pads are often used to connect components to a PCB.
One of ordinary skill in the art would understand that generic connector pads (as in the official notice above), when used for a USB connector (as in Bhatia), and implemented for use with a test interface, as described by Wang, could be considered test pads.
Bhatia does not expressly disclose the memory apparatus wherein the memory program is a read-only memory program.
Wikipedia’s Boot ROM teaches use of a read-only memory used for booting a computer, the boot ROM storing initial loading code at a fixed location (first two paragraphs).Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware disclosed by Bhatia in view of Wang such that the initialization code run in conjunction with a BIOS POST routine is run off a boot ROM, as taught by Wikipedia’s Boot ROM. This modification would have been obvious because a boot ROM typically loads a bootloader (first paragraph of Wikipedia’s boot ROM) and a boot ROM provides functionality for initializing hardware busses and peripherals (Wikipedia’s boot ROM section Operation, second paragraph) validating a bootloader (Wikipedia’s boot ROM section Operation, fourth paragraph), detecting suspend-to-RAM mode (Wikipedia’s boot ROM section Suspend to RAM).
Regarding claim 7, Bhatia in view of Wang discloses the memory apparatus of claim 1, wherein the memory controller is further configured to:
after being powered on, acquire the second startup data (Bhatia paragraph 58, an active BIOS image load is attempted before fallback to another source); and
when succeeding in acquiring the second startup data, perform the initialization operation on the memory apparatus according to the second startup data (Bhatia paragraph 58, an active BIOS image load is attempted).
Regarding claim 8, Bhatia in view of Wang discloses the memory apparatus of claim 1, wherein the main circuit board comprises a first side and a second side disposed oppositely, the memory controller is disposed on the first side of the main circuit board, and the test interface is disposed on the first side or the second side of the main circuit board (the examiner has taken official notice that it is well known in the art for a PCB to have a front and back side; the memory controller may be on a first side of the PCB, while the test interface may be on the same first side or a second side).
Regarding claim 11, Bhatia discloses a fixture, comprising:
a substrate (paragraph 22, components may be on a SoC);
a startup data storage device disposed on the substrate, wherein first startup data is stored in the startup data storage device (paragraph 58, BMC can obtain a fallback BIOS from SD Card) for a memory controller (Figure 1, the memory 184 and its associated controller are disposed on the host and connected to the firmware images accessible by the BMC) to perform an initialization operation that comprises executing a memory program (paragraphs 26 and 27, a BIOS performs a POST and runs other UEFI boot services) and a bootloader to complete system initialization (paragraph 28, bootstrap loader is read which loads an OS into memory); and
a connector disposed on the substrate and connected with the startup data storage device (paragraph 58, SD card connector), wherein the connector is configured for contact connection with an interface on a memory apparatus (paragraph 58, the SD card connector is connected to the BMC and SD card memory).
Bhatia does not expressly disclose the fixture wherein the fixture is a test fixture, the substrate, connector and interface are for use in testing, and wherein the test interface comprises a plurality of test pads disposed on the main circuit board.
Wang teaches a test fixture having a BMC that can control the switching between a main BIOS and a backup BIOS for performing for testing BIOS (first few paragraphs).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the firmware failover system disclosed by Bhatia such that the host is in contact connection with a test connector on a test fixture having a BMC, as taught by Wang. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, testing of BIOS allows for confirmation of the correct functionality of the BIOS, and use of a test fixture to do so may save time when performing BIOS testing (Wang, third paragraph).
Bhatia does not expressly disclose the memory apparatus wherein the interface comprises a plurality of pads disposed on the main circuit board and configured for contact connection with a connector on a fixture. Bhatia teaches that the host is connected to BMC via USB (Figure 1, paragraph 21).
The examiner has taken official notice that it is well known in the art for a USB connector to include pads for electrical linking to a PCB (see, for example, attached NPL from StackExchange describing soldering USB port pads). This noticed fact has not been argued, only the sufficiency of the fact with respect to the scope of the claim.
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware loading disclosed by Bhatia such that USB connection to a test fixture BMC is done via conductive pads, as is well known in the art. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, conductive pads are often used to connect components to a PCB.
One of ordinary skill in the art would understand that generic connector pads (as in the official notice above), when used for a USB connector (as in Bhatia), and implemented for use with a test interface, as described by Wang, could be considered test pads.
Bhatia does not expressly disclose the memory apparatus wherein the memory program is a read-only memory program.
Wikipedia’s Boot ROM teaches use of a read-only memory used for booting a computer, the boot ROM storing initial loading code at a fixed location (first two paragraphs).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware disclosed by Bhatia in view of Wang such that the initialization code run in conjunction with a BIOS POST routine is run off a boot ROM, as taught by Wikipedia’s Boot ROM. This modification would have been obvious because a boot ROM typically loads a bootloader (first paragraph of Wikipedia’s boot ROM) and a boot ROM provides functionality for initializing hardware busses and peripherals (Wikipedia’s boot ROM section Operation, second paragraph) validating a bootloader (Wikipedia’s boot ROM section Operation, fourth paragraph), detecting suspend-to-RAM mode (Wikipedia’s boot ROM section Suspend to RAM).
Regarding claim 13, Bhatia in view of Wang discloses the test fixture of claim 11, wherein the test connector comprises:
a plurality of thimbles each being configured for contact connection with one test pad in the test interface (Bhatia paragraph 58, the BMC connects to a SD card; it would be clear to one of ordinary skill in the art that a SD card connector includes multiple pins; it is unclear how a SD card connector pins differ from thimbles).
Regarding claim 14, Bhatia in view of Wang discloses the test fixture of claim 11, further comprising:
a processor disposed on the test substrate (Bhatia paragraph 58, BMC receives BIOS firmware from SD card);
a first conversion interface connected with the signal processor (Bhatia paragraph 58, the BMC has an interface for a SD card); and
a second conversion interface connected with the signal processor and configured to connect with an input/output connector of the memory apparatus (Bhatia Figure 1, the BMC has an interface to the host 180),
wherein the second conversion interface is different from the first conversion interface (Bhatia Figure 1, the BMC interface to the host is different than its interface to SD card).
Regarding claim 15, Bhatia in view of Wang discloses the test fixture of claim 14 wherein a switch is disposed between the test connector and the startup data storage device (Bhatia paragraph 58, the BMC acts as a switch to selectively connect and read data from SD card); and
after the memory apparatus outputs a startup data load failure signal, the switch is closed to enable the startup data storage device (Bhatia paragraph 58, when other BIOS images fail to load, BMC connects and loads data from SD card).
Regarding claim 16, Bhatia discloses a system, comprising:
a fixture comprising:
a startup data storage device and a connector disposed on a substrate (paragraph 58, a SD Card holds a BIOS image and is connected via SD card connector),
wherein first startup data is stored in the startup data storage device, and the connector is connected with the startup data storage device (paragraph 58, a SD Card holds a BIOS image and is connected via SD card connector) for a memory controller (Figure 1, the memory 184 and its associated controller are disposed on the host and connected to the firmware images accessible by the BMC) to perform an initialization operation that comprises executing a memory program (paragraphs 26 and 27, a BIOS performs a POST and runs other UEFI boot services) and a bootloader to complete system initialization (paragraph 28, bootstrap loader is read which loads an OS into memory); and
a memory apparatus comprising:
a main circuit board and a memory controller, wherein the main circuit board comprises a interface (Figure 1 shows host device 180 having an interface to a BMC),
the memory controller is disposed on the main circuit board and connected with the interface (Figure 1, host device includes memory 184 and storage 185; the storage itself includes an initialization image and a recovery initialization image (paragraph 33), these are recovered by use of the SD card (paragraph 56), necessitating a unshown memory controller device),
the memory apparatus is installed on the fixture, and the interface and the connector are in contact connection (Figure 1, the BMC interface is in contact with the BMC and its SD card connector).
Bhatia does not expressly disclose the memory apparatus wherein the interface is a test interface for testing and wherein the test interface comprises a plurality of test pads disposed on the main circuit board and configured for contact connection with a test connector on a test fixture during testing of the memory apparatus.
Wang teaches a test fixture having a BMC that can control the switching between a main BIOS and a backup BIOS for performing for testing BIOS (first few paragraphs).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the firmware failover system disclosed by Bhatia such that the host is in contact connection with a test connector on a test fixture having a BMC, as taught by Wang. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, testing of BIOS allows for confirmation of the correct functionality of the BIOS, and use of a test fixture to do so may save time when performing BIOS testing (Wang, third paragraph).
Bhatia does not expressly disclose the memory apparatus wherein the interface comprises a plurality of pads disposed on the main circuit board and configured for contact connection with a connector on a fixture. Bhatia teaches that the host is connected to BMC via USB (Figure 1, paragraph 21).
The examiner has taken official notice that it is well known in the art for a USB connector to include pads for electrical linking to a PCB (see, for example, attached NPL from StackExchange describing soldering USB port pads). This noticed fact has not been argued, only the sufficiency of the fact with respect to the scope of the claim.
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware loading disclosed by Bhatia such that USB connection to a test fixture BMC is done via conductive pads, as is well known in the art. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, conductive pads are often used to connect components to a PCB.
One of ordinary skill in the art would understand that generic connector pads (as in the official notice above), when used for a USB connector (as in Bhatia), and implemented for use with a test interface, as described by Wang, could be considered test pads.
Bhatia does not expressly disclose the memory apparatus wherein the memory program is a read-only memory program.
Wikipedia’s Boot ROM teaches use of a read-only memory used for booting a computer, the boot ROM storing initial loading code at a fixed location (first two paragraphs).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware disclosed by Bhatia in view of Wang such that the initialization code run in conjunction with a BIOS POST routine is run off a boot ROM, as taught by Wikipedia’s Boot ROM. This modification would have been obvious because a boot ROM typically loads a bootloader (first paragraph of Wikipedia’s boot ROM) and a boot ROM provides functionality for initializing hardware busses and peripherals (Wikipedia’s boot ROM section Operation, second paragraph) validating a bootloader (Wikipedia’s boot ROM section Operation, fourth paragraph), detecting suspend-to-RAM mode (Wikipedia’s boot ROM section Suspend to RAM).
Regarding claims 17 and 19, these claims recite limitations found in claims 1 and 13, respectively, and are respectively rejected for the same reasons as claims 1 and 13.
Claims 2-5, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bhatia in view of Wang and Interfacing SD Card with AVR Microcontroller- (Part 38/46) by Ashutosh Bhatt (herein Bhatt).
Regarding claim 2, Bhatia in view of Wang discloses the memory apparatus of claim 1. Bhatia in view of Wang does not expressly disclose the memory apparatus of claim 1, wherein the memory controller is configured to:
in response to determining that acquiring the second startup data fails,
enable, based on a select signal, an external storage device that provides the first startup data,
generate a startup data request signal, and
receive the first startup data provided by the external storage device in response to the startup data request signal; and
wherein the test interface is further configured to output the select signal and the startup data request signal.
Bhatt teaches details of an SD Card interface and architecture. Bhatt teaches that a SD card utilizes a chip select pin is used to choose between devices, host-to-card commands are sent via a DataIn pin, and that the host microcontroller host initiates all data transfers (section C 1) Serial Interface Layer).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the firmware recovery system disclosed by Bhatia in view of Wang such that the SD card which is used to load firmware, as in Bhatia, is interfaced with based on a combination of signals and commands as taught by Bhatt. This modification would have been obvious because these pins and signals allow a microcontroller to interface with a SD card and read files from the SD card (Bhatt, first paragraph).
Regarding claim 3, Bhatia in view of Wang and Bhatt discloses the memory apparatus of claim 2, wherein the memory controller is configured to:
output a clock signal through the test interface (Bhatt section C 1); and
provide a supply voltage and a ground voltage to the external storage device through the test interface (Bhatt section C 1).
Bhatia in view of Bhatt does not expressly disclose the memory apparatus wherein the memory controller is to sample the first startup data based on the clock signal.
The examiner has taken official notice that it is well known in the art to use a clock signal to sample data.
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the firmware recovery from SD card data, as disclosed by Bhatia in view of Bhatt, such that data read from the SD card is sampled using the input clock signal, as is known in the art. This modification would have been obvious because, as would be clear to one of ordinary skill in the art, a rising or falling edge of a clock signal is commonly used to trigger data sampling or writing on a data line.
Regarding claim 4, Bhatia in view of Wang Bhatt discloses the memory apparatus of claim 3, wherein the test interface comprises a plurality of test pads; and
the memory controller is connected with the plurality of test pads, so as to output the select signal, the startup data request signal, the clock signal, the supply voltage, and the ground voltage, and receive the first startup data through the plurality of test pads (Bhatt sections SD Card and C1) Serial Interface Layer describe the SD card as having pins for chip select, Host-to-Card Commands and Data Input, clock, Vdd, Vss and Card-to-Host Data Output).
Regarding claim 5, Bhatia in view of Wang and Bhatt discloses the memory apparatus of claim 4, wherein the test interface comprises:
a first test pad connected to a supply pin of the memory controller and configured to output the supply voltage (Bhatt sections SD Card and C1) Serial Interface Layer, Vdd pin);
a second test pad connected to a ground pin of the memory controller and configured to output the ground voltage (Bhatt sections SD Card and C1) Serial Interface Layer, Vss pin);
a third test pad connected to a chip select signal pin of the memory controller and configured to output the select signal (Bhatt sections SD Card and C1) Serial Interface Layer, CS pin);
a fourth test pad connected to a clock pin of the memory controller and configured to output the clock signal (Bhatt sections SD Card and C1) Serial Interface Layer, SCLK pin);
a fifth test pad connected to a signal output pin of the memory controller and configured to output the startup data request signal (Bhatt sections SD Card and C1) Serial Interface Layer, DataIn in); and
a sixth test pad connected to a signal input pin of the memory controller and configured to receive the first startup data (Bhatt sections SD Card and C1) Serial Interface Layer, DataOut pin).
Regarding claims 18 and 20, these claims recite limitations found in claims 2 and 5, respectively, and are rejected for the same reasons as claims 2 and 5.
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bhatia in view of Wang and Harding (PG-PUB 2003/0005277).
Bhatia in view of Wang discloses the memory apparatus of claim 1 wherein the first startup data comprises a memory code and a bootloader (Bhatia paragraph 46, the SD card recovers the BMC boot process)
Bhatia in view of Wang does not expressly disclose the memory apparatus wherein the memory code is read-only memory code; and
the memory controller is configured to:
run a read-only memory program according to the read-only memory code,
verify the bootloader using the read-only memory program, and
run the bootloader according to the verified bootloader, so as to complete the initialization operation.
Harding teaches use of a backup BIOS that is write-protected during system operation (see abstract). A validator is used to validate primary BIOS using code located in backup BIOS and determine whether it has been corrupted (paragraph 13).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware loading disclosed by Bhatia in view of Wang such that the backup recovery firmware is read-only and includes a read-only memory program the is used to verify the recovery firmware, as taught by Harding. This modification would have been obvious because the validation may determine if a BIOS image has been corrupted (Harding paragraph 13).
Regarding claim 12, Bhatia in view of Wang discloses the test fixture of claim 11. Bhatia in view of Wang does not expressly disclose the test fixture wherein the startup data storage device comprises: a read-only memory, wherein the first startup data is stored in the read-only memory.
Harding teaches use of a backup BIOS that is write-protected during system operation (see abstract). A validator is used to validate primary BIOS using code located in backup BIOS and determine whether it has been corrupted (paragraph 13).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware loading disclosed by Bhatia in view of Wang such that the backup recovery firmware is read-only and includes a read-only memory program the is used to verify the recovery firmware, as taught by Harding. This modification would have been obvious because the validation may determine if a BIOS image has been corrupted (Harding paragraph 13).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Bhatia in view of Wang and Fogel (US Patent 2018/0260348).
Regarding claim 9, Bhatia in view of Wang discloses the memory apparatus of claim 8, further comprising:
an input/output connector disposed at an end of the main circuit board (Bhatia paragraph 46, a SD card interface is used to read an SD card; the examiner takes official notice the it is common to put SD card headers at the end of a PCB; one of ordinary skill in the art would be motivated to do so because a header at the end of a PCB is more easily accessible for inserting a SD card than a header in the middle of a PCB), wherein the test interface is located between the memory controller and the input/output connector (Figure 1, the BMC interface is located between the host memory and memory functionality and the unshown SD card interface for the BMC); and
wherein the memory apparatus further comprises:
a non-volatile memory (Figure 1).
Bhatia does not expressly disclose the memory apparatus wherein the non-volatile memory is located on a first side of the main circuit board and located on an opposite side from the input/output connector.
Fogel teaches a PCB having a memory controller and multiple memory devices (Figure 5). The memory devices are placed on both sides of a PCB (paragraph 9).
Prior to the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the recovery firmware loading disclosed by Bhatia such that memory and storage are mounted to both sides of a PCB, as taught by Fogel. This modification would have been obvious because as PCBs increase in size and complexity, components are often mounted ton both side of the PCB (Fogel paragraph 4).
Regarding claim 10, Bhatia in view of Wang and Fogel discloses the memory apparatus of claim 9, wherein the memory controller is configured to: when failing to acquire the second startup data, output a startup data load failure signal through the input/output connector (Bhatia paragraphs 44-46, a failure to load the system from the active firmware image results in loading of recovery firmware from the SD card; this implies signal communication with the BMC as in Figure 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang Z teaches using two BIOS memory cards, one as a backup for use if a virus damages the main BIOS memory card. Liang teaches determining a threshold number of boot failures and control a power supply to perform a reset and reading backup BIOS code in second memory card.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH SCHELL whose telephone number is (571) 272-8186. The examiner can normally be reached on Monday through Friday 9AM-5:00PM (Pacific Time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Please note that all agendas or related documents that Applicant would like reviewed should be sent at least one full business day (i.e. 24 hours not including weekends or holidays) before the interview.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. The fax phone number for the examiner is 571-273-8186. The examiner may be e-mailed at joseph.schell@uspto.gov though communications via e-mail are not permitted without a written authorization form (see MPEP 502.03).
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JS/JOSEPH O SCHELL/Primary Examiner, Art Unit 2114
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