DETAILED ACTION
Claims 1-10, 18-20, and 32-38 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 3/4/2026.
Withdrawn objections and rejections
The specification objection has been withdrawn.
Allowable Subject Matter
Claims 1-10 and 32 are allowed.
Claims 33-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter:
Choquette et al. (U.S. 2007/0106883), Cho et al. (U.S. 5,922,066), and Desai et al. (U.S. 2003/0167460) are the closest prior art references to reading upon some, but all not of independent claim 1 limitations.
Choquette disclosed performing unaligned load operations using a scratch register while loading adjacent cache lines. A first cache line is read from memory and rotated into the scratch register based on the unaligned memory address. A second cache line is read from memory, rotated based on the unaligned memory address, and concatenated into the destination register with a portion of the scratch register. However, Choquette doesn’t teach causing a first set of data in the register to be moved from a first to second portion of the register based on the memory address of the instruction.
Cho disclosed performing unaligned loads using two separate load operations. The first load operation reads a first portion of the effective address, rotates the data, and writes the rotated data into the destination register. The second load operation reads a second portion of the effective address, rotates the data, and conditionally writes a subset of the rotated data into the destination register. However, Cho doesn’t teach causing a first set of data in the register to be moved from a first to second portion of the register based on the memory address of the instruction.
A potential combination of either Choquette/Cho could be made with Desai to read upon the independent claims. Desai disclosed vector shift instructions that shift data within vector registers. A vector shift operation could potentially be used to replace the functionality of scratch register of Choquette or the rotation logic of Cho. However, making such a rejection would require the use of improper hindsight by use of the applicant’s specification as a roadmap towards making the rejection.
Maintained Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-20 and 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Mahurin (U.S. 2016/0364147).
As per claim 18:
Mahurin disclosed a non-transitory computer readable storage medium comprising a load instruction to cause programmable circuitry to at least:
determine least significant bits of an address of memory corresponding to the load instruction (Mahurin: Figures 2 and 4 elements 218-220 and 402, paragraph 36 and 44)(The least significant bits of the unaligned memory address are determined by the “starting address modulus vector length” determination.);
determine an aligned address by zeroing out the least significant bits from the address (Mahurin: Figure 2 elements 208-210, paragraph 29-32)(The unaligned vector load operation is broken down into two aligned load operations. Official notice is given that aligned load operations can address cache lines by having the least significant bits being zero values for the advantage of accessing aligned cache lines. Thus, it would have been obvious to one of ordinary skill in the art to implement the aligned load operations of Mahurin with zero values in the least significant bits of the memory address.);
read data from the aligned address (Mahurin: Figure 2 elements 113 and 214-216, paragraphs 32-34); and
store the data into a register based on the least significant bits of the address (Mahurin: Figures 2 and 4 elements 218-224 and 404-406, paragraphs 35-36 and 45-46)(The rotation is performed based on the modulus determination, which determines the value of the least significant bits. The rotation result is stored in the destination register.).
As per claim 19:
Mahurin disclosed the non-transitory computer readable storage medium of claim 18, wherein the load instruction causes the programmable circuitry to determine the aligned address by performing a logical AND operation using the address and a number (Mahurin: Figure 2 elements 208-210, paragraph 29-32)(In view of the above official notice, the aligned memory address has a number of least significant bit values being zero values. Official notice is given that AND operations can be used to set and clear input bits for the advantage of performing masking operations of bit values. Thus, it would have been obvious to one of ordinary skill in the art to implement an AND operation using 1 values for the most significant bits of the aligned address and zero values for the least significant bits of the unaligned address portion.).
As per claim 20:
Mahurin disclosed the non-transitory computer readable storage medium of wherein the number includes a value of zero for the least two significant bits and a value of one for the remaining of the bits of the number (Mahurin: Figure 2 elements 208-210, paragraph 29-32)(In view of the above official notice, the AND operation uses 1 values for the most significant bits of the aligned address and zero values for the least significant bits of the unaligned address portion.)
As per claim 36:
Mahurin disclosed the non-transitory computer readable storage medium of wherein the storing of the data into the register stores the data at a location within the register that is based on the least significant bits of the address (Mahurin: Figures 2 and 4 elements 218-224 and 404-406, paragraphs 35-36 and 45-46)(The rotation is performed based on the modulus determination, which determines the value of the least significant bits. The rotation result is stored in the destination register.).
As per claim 37:
Mahurin disclosed the non-transitory computer readable storage medium of claim 18, wherein the address of the memory and an indication of the register are operands of the instruction (Mahurin: Figure 2 elements 206 and 224, paragraphs 30 and 36)(Official notice is given that load instructions can use source operands to store memory addresses to access data for the advantage of reducing instruction encoding sizes. Thus, it would have been obvious to one of ordinary skill in the art to implement a source operand for the load instruction of Mahurin storing the unaligned memory address.).
As per claim 38:
Mahurin disclosed the non-transitory computer readable storage medium of wherein the least significant bits of the address of the memory correspond to an alignment of the data within a word (Mahurin: Figures 2 and 4 elements 218-220 and 402, paragraph 36 and 44)(The least significant bits of the unaligned memory address represent alignment within the 64-byte vector of data in a cache line. A subset of these least significant bits represents a placement within a given word of the 64-byte cache line.).
Response to Arguments
The arguments presented by Applicant in the response, received on 3/4/2026 are not considered persuasive.
Applicant argues regarding claim 18:
“Mahurin does not teach or suggest at least these claim limitations. Mahurin discloses that a vector of data having an unaligned address corresponds to a vector of data that has a portion in a first cache line of memory unit 113 and a second portion in a second cache line of the memory unit 113. See, e.g., Mahurin, Paragraph [0031] and FIG. 2. Mahurin also discloses that the memory subsystem 102 may generate two transactions 209, 210 based on the location of the vector data. See, e.g., Mahurin, Paragraph, [0032] and FIG. 2. Additionally, Mahurin discloses that the execution unit 104 may include a merge unit 208 that is configured to merge a portion of the first data 214 (e.g., the first portion of the vector of data) and a portion of the second data 216 (e.g., the second portion of the vector of data) to generate merged data. See, e.g., Mahurin, Paragraph [0035] and FIG. 2 Also, Mahurin discloses that the rotating unit 220 may rotate the first portion of the vector of data and the second portion of the vector of data such that data associated with the starting address (e.g., the most significant bit) is on the right and data associated with the ending address (e.g., the least significant bit) is on the left. See, e.g., Mahurin, Paragraph [0036] and FIG. 2. The Office Action states that "Official notice is given that aligned load operations can address cache lines by having the least significant bits being zero values for the advantage of accessing aligned cache lines. Thus, it would have been obvious to one of ordinary skill in the art to implement the aligned load operations of Mahurin with zero values in the least significant bits of the memory address." Office Action, Page 5. In Mahurin, the unaligned addresses correspond to vector data on more than one cache line. Mahurin addresses this by performing two separate read operations, merging the data, and rotating the data. The problem Mahurin addresses would not be solved by "having the least significant bits being zero values" as asserted by the Examiner. Thus Mahurin does not teach or suggest determine least significant bits of an address of memory corresponding to the load instruction; determine an aligned address by zeroing out the least significant bits from the address; read data from the aligned address; and store the data into a register based on the least significant bits of the address.”
This argument is not found to be persuasive for the following reason. The official notice given was for accessing aligned cache lines, where a set of least significant bits are zero at the memory address of the aligned cache line. This allows for the memory address to include non-zero bits for accessing smaller data elements directly within the cache line. For example, a scalar 32-bit data element within a 256-bit cache line would allow for the three least significant bits to be used to select a given 32-bit data element. In this example, a memory address that selects the first data element within the cache line would have the three least significant bits as “000”, which is the same memory address as the aligned cache line memory address. Thus, the rejections have been maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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