Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, see The Objection to the Drawings and Amendment to the Specification, filed August 11, 2026, with respect to the reference character 700 not mentioned in the description has been fully considered and is persuasive. The drawing objection of May 12, 2026 has been withdrawn.
Applicant’s remarks, see The Claim Rejections under 35 U.S.C. § 112, filed August 11, 2026, with respect to claims 4-5, 8-11, and 17-20 have been fully considered and are persuasive. The 112(a) and 112(b) rejections of May 12, 2026 have been withdrawn.
Applicant’s arguments, see The Claim Rejections under 35 U.S.C. § 102, filed August 11, 2026, with respect to claims 1 and 12-13 have been considered but are moot because of the new ground of rejection.
Applicant’s arguments, see The Claim Rejections under 35 U.S.C. § 103, filed August 11, 2026, with respect to dependent claims have been considered but are moot because of the new ground of rejection.
Claim Objections
Claims 8-9 are objected to because of the following informalities:
Claim 8 (line 2) recites “a noise-shaping successive-approximation- register (SAR)”. There is a space between the dash and the word register.
Claim 9 (line 1) recites “the noise- shaping”. There is a space between the dash and the word shaping.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, and 12-15 are rejected under 35 U.S.C. 102(a)(1) and 102 (a)(2) as being anticipated by Mallinson (US 20140375356 A1); hereinafter Mallinson.
Regarding Claim 1, Mallinson discloses a delay cell [400] in a delay circuit [Fig. 4], comprising: a first p-type metal-oxide semiconductor (PMOS) transistor [M1] having a source [M1-source] coupled to a power supply node for a power supply voltage [Dvcc]; a first n-type metal-oxide semiconductor (NMOS) transistor [M2] having a source [M2-source] coupled to ground [DGnd]; a first transistor pair [M3/M4] coupled between a drain of the first PMOS transistor [M1-drain] and a drain of the first NMOS transistor [M2-drain]; a second PMOS transistor [M5] having a source [M5-source] coupled to the power supply node; a second NMOS transistor [M8] having a source [M8-source] coupled to ground; and a second transistor pair [M6/M7] coupled between a drain of the second PMOS transistor [M5-drain] and a drain of the second NMOS transistor [M8-drain], wherein the drain of the first PMOS transistor is coupled to a gate of the second PMOS transistor [M1-drain coupled directly to M5-gate], and wherein the drain of the first NMOS transistor is coupled to a gate of the second NMOS transistor [M2-drain coupled directly to M8-gate], wherein the first transistor pair comprises: a third PMOS transistor [M3] having a source [M3-source] coupled to the drain of the first PMOS transistor [coupled directly to M1-drain] and a gate [M3-gate] coupled to the drain of the first NMOS transistor [coupled indirectly thru M3 to M2-drain]; and a third NMOS transistor [M4] having a source [M4-source] coupled to the drain of the first NMOS transistor [directly coupled to M2-drain], a drain [M4-drain] coupled to a drain of the third PMOS transistor [coupled indirectly thru M4 to M3-drain], and a gate [M4-gate] coupled to the drain of the first PMOS transistor [coupled indirectly thru M4 to M1-drain], the gate of the third PMOS transistor being coupled to the drain of the third PMOS transistor through the third NMOS transistor [M3-gate coupled indirectly thru M3/M4 to M3-drain], and the gate of the third NMOS transistor being coupled to the drain of the third NMOS transistor through the third PMOS transistor [M4-gate coupled indirectly thru M4/M3 to M4-drain].
Regarding Claim 5, Mallinson discloses the delay cell of claim 1, wherein the second transistor pair comprises: a fourth PMOS transistor [M6] having a source [M6-source] coupled to the drain of the second PMOS transistor [coupled directly to M5-drain]; and a fourth NMOS transistor [M7] having a source [M7-source] coupled to the drain of the second NMOS transistor [coupled directly to M8-drain] and having a drain [M7-drain] coupled to a drain of the fourth PMOS transistor [coupled indirectly thru M6 to M6-drain], wherein the drain of the second NMOS transistor is coupled to a gate of the fourth PMOS transistor [M8-drain coupled indirectly thru M6 to M6-gate], and wherein the drain of the second PMOS transistor is coupled to a gate of the fourth NMOS transistor [M5-drain coupled indirectly thru M7 to M7-gate].
Regarding Claim 12, Mallinson discloses a delay cell [400] in a delay circuit [Fig. 4], comprising: a first serial stack of three transistors [M1, M3/M4, M2] including a first transistor [M1] coupled to a power supply node for a power supply voltage [DVcc], a second transistor [M2] coupled to ground [DGnd], and a third transistor [M3 or M4] coupled between the first transistor and the second transistor, wherein a drain of the first transistor [M1-drain] is connected to a first terminal of the third transistor [connected directly to M3-source or M4-drain] and a drain of the second transistor [M2-drain] is connected to a second terminal of the third transistor [connected directly to M3-drain or M4-source]; and a second serial stack of three transistors [M5, M6/M7, M8] including a fourth transistor [M5] coupled to the power supply node for the power supply voltage, a fifth transistor [M8] coupled to ground, and a sixth transistor [M6 or M7] coupled between the fourth transistor and the fifth transistor, wherein a drain of the fourth transistor [M5-drain] is connected to a first terminal of the sixth transistor [connected directly to M6-source or M7-drain] and a drain of the fifth transistor [M8-drain] is connected to a second terminal of the sixth transistor [connected directly to M6-drain or M7-source], wherein a node between the first transistor and the third transistor is coupled to a gate of the fourth transistor [node between M1-drain and M3-source coupled directly to M5-gate], and wherein a node between the third transistor and the second transistor is coupled to a gate of the fifth transistor [node between M3-drain and M2-drain coupled directly to M8-gate].
Regarding Claim 13, Mallinson discloses delay cell of claim 12, wherein the delay cell is an initial delay cell [M1, M3/M4, M2] in a serial chain of delay cells [M1, M3/M4, M2; M5, M6/M7, M8; M9, M10/M11, M12] in the delay circuit.
Regarding Claim 14, Mallinson discloses the delay cell of claim 12, wherein the third transistor is a PMOS transistor [M3, paragraph 0043], and wherein the sixth transistor is an NMOS transistor [M7, paragraph 0043].
Regarding Claim 15, Mallinson discloses the delay cell of claim 12, wherein the third transistor is an NMOS transistor [M4, paragraph 0043], and wherein the sixth transistor is a PMOS transistor [M6, paragraph 0043].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Mallinson, in view of Noguchi (US 20130134788 A1); hereinafter Mallinson, in view of Noguchi.
Regarding Claim 6, Mallinson does not explicitly disclose the delay cell of claim 1, wherein the delay circuit is included within a pulse generator.
However, Noguchi discloses wherein the delay circuit is included within a pulse generator [paragraph 0003]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Noguchi in the invention of Mallinson, with the expected benefit of controlling timings between an event and the output pulse. This method of improving Mallinson using Noguchi was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Noguchi. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mallinson and Noguchi to obtain the invention: incorporating a delay circuit within a pulse generator.
Regarding Claim 16, Mallinson does not explicitly disclose the delay cell of claim 12, wherein the delay circuit is included within a pulse generator.
However, Noguchi discloses wherein the delay circuit is included within a pulse generator [paragraph 0003]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Noguchi in the invention of Mallinson, with the expected benefit of controlling timings between an event and the output pulse. This method of improving Mallinson using Noguchi was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Noguchi. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mallinson and Noguchi to obtain the invention: incorporating a delay circuit within a pulse generator.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Mallinson, in view of Noguchi, further in view of Chen (US 20090134922 A1); hereinafter Mallinson, in view of Noguchi, further in view of Chen.
Regarding Claim 7, Mallinson, in view of Noguchi, does not explicitly disclose the delay cell of claim 6, wherein the pulse generator includes: an input node for an input signal to the pulse generator; a NOR gate configured to generate an output signal for the pulse generator, wherein the delay circuit is coupled between the input node and a first input terminal to the NOR gate; and an inverter coupled between the input node and a second input terminal to the NOR gate.
However, Chen discloses wherein the pulse generator includes [Fig. 4a; 200]: an input node [EN] for an input signal [EN signal] to the pulse generator; a NOR gate [NOR] configured to generate an output signal [S1] for the pulse generator, wherein the delay circuit [X1/X2] is coupled between the input node and a first input terminal to the NOR gate [upper input terminal of NOR gate]; and an inverter [X3] coupled between the input node and a second input terminal to the NOR gate [lower input terminal of the NOR gate]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Chen in the invention of Mallinson, in view of Noguchi, with the expected benefit of sharpening the voltage. This method of improving Mallinson, in view of Noguchi, using Chen was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Chen. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mallinson, in view of Noguchi, and Chen to obtain the invention: incorporating the input node, the NOR gate, and the inverter.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mallinson, in view of Noguchi, further in view of Guo et al. (US 20210266004 A1); hereinafter Mallinson, in view of Noguchi, further in view of Guo.
Regarding Claim 8, Mallinson, in view of Noguchi, does not explicitly disclose the delay cell of claim 6, wherein the pulse generator controls a plurality of integration switches in a noise-shaping successive-approximation-register (SAR) quantizer.
However, Guo discloses wherein the pulse generator [802] controls [paragraphs 0075, 0090] a plurality of integration switches [first switch unit 11/second switch unit 12 (12 in spec, but shown as 22 in drawings)] in a noise-shaping successive-approximation-register analog-to-digital converter [Fig. 1, Fig. 6]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Guo in the invention of Mallinson, in view of Noguchi, with the expected benefit of improving accuracy of the NSSAR ADC. This method of improving Mallinson, in view of Noguchi, using Guo was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Guo. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mallinson, in view of Noguchi, and Guo to obtain the invention: incorporating the noise-shaping successive-approximation-register.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mallinson, in view of Noguchi and Guo, further in view of Rajaee et al. (US 9425818 B1); hereinafter Mallinson, in view of Noguchi and Guo, further in view of Rajaee.
Regarding Claim 9, Mallinson, in view of Noguchi, further in view of Guo, does not explicitly disclose the delay cell of claim 8, wherein the noise-shaping SAR quantizer is included within a sigma-delta analog-to-digital converter.
However, Rajaee discloses wherein the noise-shaping successive-approximation-register analog-to-digital converter [column 1, lines 8-10; column 2, lines 7-10] is a quantizer [column 11, lines 6-11] for a sigma-delta analog-to-digital converter [column 11, lines 6-11]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Rajaee in the invention of Mallinson, in view of Noguchi, further in view of Guo, with the expected benefit of generating a digital signal. This method of improving Mallinson, in view of Noguchi, further in view of Guo, using Rajaee was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Rajaee. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mallinson, in view of Noguchi, further in view of Guo, and Rajaee to obtain the invention: incorporating the quantizer.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mallinson, in view of Noguchi/Guo/Rajaee, further in view of Henriksen (US 20120121106 A1); hereinafter Mallinson, in view of Noguchi/Guo/Rajaee, further in view of Henriksen.
Regarding Claim 10, Mallinson, in view of Noguchi and Guo, further in view of Rajaee, does not explicitly disclose the delay cell of claim 9, wherein the sigma-delta analog-to-digital converter is configured to digitize an audio signal from a micro-electromechanical system (MEMS) microphone.
However, Henriksen discloses wherein the sigma-delta analog-to-digital converter [Fig. 1, 111/112] is configured to digitize an audio signal [paragraph 0049] from a micro-electromechanical system (MEMS) microphone [paragraph 0019]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Henriksen in the invention of Mallinson, in view of Noguchi and Guo, further in view of Rajaee, with the expected benefit of standardizing data communication. This method of improving Mallinson, in view of Noguchi and Guo, further in view of Rajaee, using Henriksen was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Henriksen. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mallinson, in view of Noguchi and Guo, further in view of Rajaee, and Henriksen to obtain the invention: digitizing the audio signal form the MEMs microphone.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mallinson, in view of Noguchi/Guo/Rajaee/Henriksen, further in view of Mohammadi et al. (US 11381911 B1); hereinafter Mallinson, in view of Noguchi/Guo/Rajaee/Henriksen, further in view of Mohammadi.
Regarding Claim 11, Mallinson, in view of Noguchi/Guo/Rajaee, further in view of Henriksen, does not explicitly disclose the delay cell of claim 10, wherein the sigma-delta analog-to-digital converter is included within a cellular telephone.
However, Mohammadi discloses wherein the sigma-delta analog-to-digital converter is included within a cellular telephone [column 1, lines 13-20]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Mohammadi in the invention of Mallinson, in view of Noguchi/Guo/Rajaee, further in view of Henriksen, with the expected benefit of compensating for non-linearity. This method of improving Mallinson, in view of Noguchi/Guo/Rajaee, further in view of Henriksen, using Mohammadi was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Mohammadi. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mallinson, in view of Noguchi/Guo/Rajaee, further in view of Henriksen, and Mohammadi to obtain the invention: including the sigma-delta analog-to-digital converter in a cellular telephone.
Allowable Subject Matter
Claims 17-18 and 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 17, Mallinson discloses a delay cell method [Fig. 6; paragraphs 0026, 0074], comprising: responding to a rising-edge transition of an input signal [CMOS In] by switching on a first NMOS transistor [M2] having a source [M2-source] coupled to ground [DGnd] to discharge a drain of the first NMOS transistor [M2-drain]; responding to the discharge of the drain of the first NMOS transistor by switching on a first diode-connected PMOS transistor [M3B] having a drain [M3B-drain] and a gate [M3B-gate] coupled to the drain of the first NMOS transistor [coupled indirectly thru M3 to M2-drain] to discharge a source of the first diode-connected PMOS transistor [M3B-source] to a voltage that is a transistor threshold voltage greater than a voltage of the drain of the first NMOS transistor [receives the delayed voltage from DVcc which is greater than the voltage at M2-drain (which is near DGnd)]; responding to the discharge of the source of the first diode-connected PMOS transistor by switching on a second PMOS transistor [M5] having a gate [M5-gate] coupled to the source of the first diode-connected PMOS transistor [coupled indirectly thru M4/M8/DGnd/M1B to M3b-source] to begin charging a drain of the second PMOS transistor [M5-drain]; responding to the charging of the drain of the second PMOS transistor by switching on a first diode-connected NMOS transistor [M4B] having a drain [M4B-drain] and a gate [M4B-gate] coupled to the drain of the second PMOS transistor [coupled indirectly thru M7 to M5-drain] to charge a source of the first diode-connected NMOS transistor [M4B-source].
However, the prior art of the record does not disclose nor render obvious a second diode-connected NMOS transistor and a second diode-connected PMOS transistor, and any connections or couplings associated with the second diode-connected NMOS transistor and the second diode-connected PMOS transistor, as cited with the rest of the claimed limitation. Dependent claims are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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