DETAILED ACTION
Claims 1, 12, 18, 19 are amended. Claim(s) 1-6, 8-21 are pending. Claim 7 is cancelled.
Priority: 9/25/2023(FP)
Assignee: Yangtze Memory
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/19/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-6, 8-12, 17, 18, 19, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al.(20210173785), in view of Rho et al.(20230244402), and further in view of Das et al.(20210049104).
Claim 1 is similar to claim 18 as shown below and therefore the same rejections are incorporated.
As per claim 3, the rejection of claim 1 is incorporated, in addition, Jin discloses:
wherein the first command is to instruct to write the first data, and the first command further comprises the first data, and the performing the operation on the first data in the first storage space according to the at least one first physical page address comprises: writing the first data at at least one physical address in the first storage space(Jin, [0040 -- The memory controller 200 may control the memory device 100 to perform the program operation, the read operation, or the erase operation in response to a request from the host. During the program operation, the memory controller 200 may provide a write command, a physical block address, and data to the memory device 100. ]).
As per claim 5, the rejection of claim 1 is incorporated, in addition, Jin discloses:
wherein the first command is to instruct to read the first data, and the performing the operation on the first data in the first storage space according to the at least one first physical page address comprises: reading the first data at the at least one first physical page address in the first storage space(Jin, [0040 -- During the read operation, the memory controller 200 may provide a read command and the physical block address to the memory device 100.]).
As per claim 6, the rejection of claim 1 is incorporated, in addition, Jin discloses:
wherein a controller of the memory system comprises a cache in which the first mapping relationship is stored(Jin, [0138 - The map data manager 420 may manage the first mapping table and the second mapping table by different address mapping methods. ]).
As per claim 8, the rejection of claim 1 is incorporated, in addition, Jin discloses:
in response to a second command comprising a second logical address of second data on which an operation is to be performed is received, obtaining a second physical page address corresponding to the second logical address according to a second mapping relationship, the second logical address corresponding to a second storage space of the memory(Jin, [0170 -- When the logical address corresponds to random write data, the main controller may store the mapping data generated based on the logical address in the first mapping table 421. ]);
and performing the operation on the second data in the second storage space according to the second physical page address, wherein the second storage space is a storage space that can support random read or random write(Jin, [0102 -- In addition, the main controller may determine whether the data input from the host 300 is random write data or sequential write data based on the logical address received from the host 300.]).
As per claim 9, the rejection of claim 8 is incorporated, in addition, Jin discloses:
wherein the second mapping relationship is a mapping relationship comprising the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address(Jin, [0148 -- Specifically, in the first mapping table 421, the logical addresses and the physical address of the page unit may be mapped with each other one-to-one.]).
As per claim 10, the rejection of claim 8 is incorporated, in addition, Jin discloses:
before the obtaining a second physical page address corresponding to the second logical address according to a second mapping relationship and the second logical address, establishing the second mapping relationship corresponding to the second logical address(Jin, [0163 -- When the logical address received from the host 300 is included in the first logical address range LBA 1 to LBA 1000, the main controller may store the mapping data generated based on the logical address in the first mapping table 421. When the logical address received from the host 300 is included in the second logical address range LBA 1001 to LBA 2000, the main controller may store the mapping data generated based on the logical address in the second mapping table 422. As described with reference to FIG. 4B,]);
and writing the second mapping relationship corresponding to the second logical address into the memory, wherein the performing the operation on the second data in the second storage space according to the second physical page address comprises: writing the second data at the second physical page address in the second storage space(Jin, [0168 -- The main controller may determine whether the logical address corresponds to random write data or sequential write data based on a length (or the number of successive logical addresses) received from the host 300. In FIG. 8, when the length of the logical address string, i.e., number of logical addresses, is equal to or greater than 10, the main controller may determine that the logical address corresponds to sequential write data.]).
As per claim 11, the rejection of claim 8 is incorporated, in addition, Jin discloses:
wherein the second command is to instruct to read the second data, and the method further comprises: before the obtaining a second physical page address corresponding to the second logical address according to a second mapping relationship, in response to the second command, reading the second mapping relationship corresponding to the second logical address from the memory,(Jin, [0163 -- When the logical address received from the host 300 is included in the first logical address range LBA 1 to LBA 1000, the main controller may store the mapping data generated based on the logical address in the first mapping table 421. When the logical address received from the host 300 is included in the second logical address range LBA 1001 to LBA 2000, the main controller may store the mapping data generated based on the logical address in the second mapping table 422. As described with reference to FIG. 4B,]);
wherein the performing the operation on the second data in the second storage space according to the second physical page address comprises: reading the second data at the second physical page address in the second storage space(Jin, [0093 -- The first memory controller 200_1 may select a memory device group to perform the read operation based on the logical address received from the host 300. The first memory controller 200_1 may control the memory device group corresponding to the mapping table including the received logical address to perform the read operation.]).
As per claim 12, the rejection of claim 8 is incorporated, in addition, Jin does not explicitly disclose the following, however Das discloses:
wherein the second mapping relationship is a three-level mapping relationship that occupies more storage space than the two- level mapping relationship(Das, [0083 -- FIG. 4 illustrates a diagram of data structures at the intermediate physical addresses shown in FIGS. 2B and 3, according to an embodiment. In FIG. 4, data structures 401, 402, 403, and 404 are shown for the intermediate physical addresses A, B, C, and D of FIGS. 2B and 3, respectively. Each of the data structures 401, 402, 403, and 404 includes a pointer for each of the four (N=4) logical addresses mapped to the respective data structure. Each pointer points to a target physical address in the memory devices 106 where the actual data is to be read from, or written to, for the respective logical address.]).
As per claim 17, the rejection of claim 1 is incorporated, in addition, Jin discloses:
wherein the storage capacity of one of the zones is (1/n) times the storage capacity corresponding to the physical block of the memory of the memory system, and wherein 1<n≤256(Jin, [0087 -- A zone may be a physical area, the size of which is larger than that of a page. For example, a zone may correspond to at least two pages. For example, the zone may correspond to a single block or a group of blocks. The size of the physical area corresponding to the zone may be various. Thus, an entry in the second mapping table may be to one or more specific blocks.]).
As per claim 18, Jin discloses:
A controller comprising:
a processor(Jin, [0029 -- Referring to FIG. 1, the storage device 50 may include one or more instances of a memory device 100 and one or more instances of a memory controller 200 that controls operation of the memory device(s). For clarity, however, only one memory device 100 and one controller 200 are shown in FIG. 1.]);
and an interface circuit coupled to the processor and a memory(Jin, [0069 -- During the read operation or the verify operation, the sensing circuit 125 may generate a reference current in response to a signal of a permission bit VRYBIT generated by the control logic 130 and may compare a sensing voltage VPB received from the read and write circuit 123 with a reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic 130.]), wherein the processor is configured to:
in response to receiving a first command comprising a first logical address of first data on which an operation is to be performed, determine at least one zone corresponding to the first logical address, the at least one zone corresponding to a first storage space of the memory(Jin, [0088 -- The first memory controller 200_1 may receive the request and the logical address from the host 300. The request may be a read request or a write request.], [0149 -- In the second mapping table 422, the logical address and the physical address of the zone unit may be mapped with each other N-to-one (N is a natural number equal to or greater than 1). In FIG. 7, one zone may be mapped with 250 logical addresses, although this is merely an example. One zone may be mapped with any suitable number of logical addresses.]);
and send a second command to the memory via the interface circuit to perform the operation on the first data according to the at least one first physical page address(Jin, [0127 -- When the logical address is included in a second logical address range, the operation controller 410 may provide the write command and the write data to the second memory controller 500. The second memory controller 500 may control the second memory device group 100_2 to store the write data based on the write command received from the operation controller 410.]), wherein a storage capacity of one of the zones is less than a storage capacity corresponding to a physical block of the memory(Jin, [0087 -- A zone may be a physical area, the size of which is larger than that of a page. For example, a zone may correspond to at least two pages. For example, the zone may correspond to a single block or a group of blocks. The size of the physical area corresponding to the zone may be various. Thus, an entry in the second mapping table may be to one or more specific blocks.]), and the first storage space is a storage space that supports sequential read and sequential write((Jin, [0176 -- When mapping data is stored in a specific mapping table according to which logical address range the logical address is included in, the mapping data is stored in the specific mapping table according to whether the logical address corresponds to the random write data or the sequential write data, as exemplified by FIGS. 7 and 8.]);
Jin does not explicitly disclose the following in its entirety, however, Rho discloses:
obtain at least one first physical page address in a pointer mode corresponding to the at least one zone according to a first mapping relationship and the at least one zone,(Rho, [0047 -- When the logical block address or the write pointer is not included in the write command, the flash translation layer 214 of the storage controller 210 may identify a physical block address corresponding to a location of a current write pointer of a zone corresponding to the write command.]);
wherein the pointer mode comprises calculating the first logical address according to a preset algorithm to determine a pointer corresponding to the first logical address, and wherein the pointer indicates a sequence number of the at least one first physical page address among plurality of physical page addresses corresponding to the at least one zone(Rho, [0040 -- Logical block addresses of each zone may be consecutive. Consecutive logical block addresses of each zone may correspond to consecutive physical block addresses of the nonvolatile memory 220. In each zone, the storage device 200 may support a sequential write operation and may not support a random write operation.], [0047 -- When the write pointer is included in the write command, the flash translation layer 214 of the storage controller 210 may translate the write pointer into a physical block address. When the logical block address or the write pointer is not included in the write command, the flash translation layer 214 of the storage controller 210 may identify a physical block address corresponding to a location of a current write pointer of a zone corresponding to the write command.]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Rho into the system of Jin for the benefit of the storage device decreasing a read latency in a copy operation associated with a zoned storage space and an operating method of the storage device.
Jin in view of Rho does not explicitly disclose the following, however Das discloses:
wherein the first mapping relationship is a two-level mapping relationship, and wherein the two-level mapping relationship comprises a first-level mapping table that stores a physical address in a physical block indicating a second-level mapping table corresponding to a zone(Das, [0071 -- Each of the mapped logical addresses 202A has two (i.e., N=2) of the logical addresses 201A mapped thereto. Each of the mapped logical addresses 202A is mapped to one of the intermediate physical addresses 203A. For example, in FIG. 2A, logical addresses 1 and 2 are mapped to mapped logical address 1, which is mapped to intermediate physical address A], [0073 -- FIG. 2B illustrates a diagram of an example logical-to-physical address mapping table with four logical addresses mapped to an intermediate physical address, according to an embodiment. A logical-to-physical address mapping table 200B (also referred to herein as “mapping table 200B”) is shown and includes columns for logical addresses 201B, mapped logical addresses 202B, and intermediate physical addresses 203B.]), and the second-level mapping table corresponding to the zone stores a plurality of physical page addresses corresponding to the zone(Das, [0083 -- FIG. 4 illustrates a diagram of data structures at the intermediate physical addresses shown in FIGS. 2B and 3, according to an embodiment. In FIG. 4, data structures 401, 402, 403, and 404 are shown for the intermediate physical addresses A, B, C, and D of FIGS. 2B and 3, respectively. Each of the data structures 401, 402, 403, and 404 includes a pointer for each of the four (N=4) logical addresses mapped to the respective data structure. Each pointer points to a target physical address in the memory devices 106 where the actual data is to be read from, or written to, for the respective logical address.]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Das into the system of Jin and Rho for the benefit of implementing with single-level cells (SLC) to provide faster read speeds and require less sensing than blocks implemented with multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC)(Das, 0085).
Claim 19 is similar to claim 18 as shown below and therefore the same mappings are incorporated.
As per claim 21, the rejection of claim 18 is incorporated, in addition, Jin in view of Rho does not disclose:
wherein the processor is configured to: determine the at least one first physical page address in a pointer mode based on the first mapping relationship and the at least one zone(Das, [0086 -- n this way, each of the logical addresses 1 through 16 are ultimately mapped to a respective one of the target physical addresses E through T. The data D1 through D16 can be stored in the data storage portion of the storage device (e.g., the memory devices 106 of the storage device 101 FIG. 1).]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Das into the system of Jin and Rho for the benefit of implementing with single-level cells (SLC) to provide faster read speeds and require less sensing than blocks implemented with multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC)(Das, 0085).
Claim(s) 2, 4, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al.(20210173785), in view of Rho et al.(20230244402), in view of Das et al.(20210049104), and further in view of Helmick et al.(20210334203).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Jin does not explicitly disclose the following in its entirety, however Helmick discloses:
wherein the obtaining at least one first physical page address corresponding to the at least one zone according to a first mapping relationship and the at least one zone determined comprises: determining the at least one first physical page address in a pointer mode based on the first mapping relationship and the at least one zone(Helmick, [0036 -- As data is written to a zone 206, a write pointer 210 is advanced or updated to point to or to indicate the next available block in the zone 206 to write data to in order to track the next write starting point (i.e., the completion point of the prior write equals the starting point of a subsequent write). Thus, the write pointer 210 indicates where the subsequent write to the zone 206 will begin.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Helmick into the system Jin for the benefit of receiving a read command to read data stored in a non-volatile storage unit, and identifying a logical block address of the data, thus ensuring simple and efficient operation of the storage device.
As per claim 4, the rejection of claim 3 is incorporated, in addition, Jin does not explicitly disclose the following in its entirety, however Helmick discloses:
before the obtaining at least one first physical page address corresponding to the at least one zone according to a first mapping relationship and the at least one zone determined, establishing the first mapping relationship in which the at least one zone corresponds to a plurality of physical page addresses, the plurality of physical page addresses comprising the at least one first physical page address; and writing the first mapping relationship in which the at least one zone corresponds to the plurality of physical page addresses into the memory(Helmick, [0075 -- The first ZNS L2P table 420 comprise a pointer to the first or starting physical address of each zone, such that a pointer is associated with each zone start LBA (ZSLBA). A ZSLBA may be Z.sub.0SLBA 422, Z.sub.1SLBA 424, or Z.sub.NSLBA 426, where “N” is an integer. The DRAM 410 may further comprise one or more second ZNS L2P tables (second L2P table 430 shown). The second ZNS L2P table 430 comprises a pointer to each erase block within each zone, as discussed further below. The zones in the L2P tables may be in any order, such that a second zone is listed before a first zone.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Helmick into the system Jin for the benefit of receiving a read command to read data stored in a non-volatile storage unit, and identifying a logical block address of the data, thus ensuring simple and efficient operation of the storage device.
Claim 20 is similar to claim 2 as shown above and therefore the same mappings are incorporated.
Claim(s) 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al.(20210173785), in view of Rho et al.(20230244402), in view of Das et al.(20210049104), and further in view of Mathur et al.(20150347013).
As per claim 13, the rejection of claim 8 is incorporated, in addition, Jin does not explicitly disclose the following in its entirety discloses:
performing a first garbage collection operation on physical blocks other than blank physical blocks in the second storage space(Mathur, [0043 -- As an example, if data is written to a storage medium in pages, but the storage medium is erased in blocks, pages in the storage medium may contain invalid (e.g., stale) data, but those pages cannot be overwritten until the whole block containing those pages is erased. In order to write to the pages with invalid data, the pages with valid data in that block are read and re-written to a new block and the old block is erased (or put on a queue for erasing). This process is called garbage collection. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Mathur into the system Jin for the benefit of the sub-region accessing more than a predetermined threshold number of times is determined during a predetermined time period, thus reduces write amplification and improves endurance of the storage device.
As per claim 14, the rejection of claim 13 is incorporated, in addition, Jin does not explicitly disclose the following in its entirety, however Mathur discloses:
wherein the first garbage collection operation is performed when it is detected that a quantity of the blank physical blocks is less than a first preset value(Mathur, [0045 -- By reducing the write amplification, the endurance of the storage medium is increased and the overall cost of the storage system is decreased. Generally, garbage collection is performed on erase blocks with the fewest number of valid pages for best performance and best write amplification.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Mathur into the system Jin for the benefit of the sub-region accessing more than a predetermined threshold number of times is determined during a predetermined time period, thus reduces write amplification and improves endurance of the storage device.
As per claim 15, the rejection of claim 1 is incorporated, in addition, Jin does not explicitly disclose the following in its entirety, however Mathur discloses:
performing a second garbage collection operation on zones other than blank zones in the first storage space(Mathur, [0085 -- By grouping together data associated with hot regions in the hot blocks, hot blocks will typically have more invalid pages due to the frequent updating of data in the hot regions, resulting in fewer valid pages that need to be copied in a garbage collection operation. By grouping together data from cold regions in the cold blocks, cold blocks will typically have more valid pages, due to the lower frequency of updates in the cold regions than the hot regions, and will be less likely to be selected for garbage collection, reducing the movement of cold data to new blocks. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Mathur into the system Jin for the benefit of the sub-region accessing more than a predetermined threshold number of times is determined during a predetermined time period, thus reduces write amplification and improves endurance of the storage device.
As per claim 16, the rejection of claim 15 is incorporated, in addition, Jin does not explicitly disclose the following in its entirety, however Mathur discloses:
wherein the second garbage collection operation is performed when it is detected that a quantity of the blank zones is less than a second preset value(Mathur, [0045 -- By reducing the write amplification, the endurance of the storage medium is increased and the overall cost of the storage system is decreased. Generally, garbage collection is performed on erase blocks with the fewest number of valid pages for best performance and best write amplification.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Mathur into the system Jin for the benefit of the sub-region accessing more than a predetermined threshold number of times is determined during a predetermined time period, thus reduces write amplification and improves endurance of the storage device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, 8-21 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Das et al.(20210049104) where the solid-state storage system comprises a controller. Several memory devices (106) are coupled to the controller to store data. The controller is configured to receive a first command to read or write first data from or to a first logical address, respectively and determine a first mapped logical address that first logical address is mapped to. A first data structure at first mapped logical address is read, where first data structure comprises a pointer to a first intermediate physical address that the first mapped logical address is mapped. A second data structure at first intermediate physical address is read, where second data structure comprises several pointers to target physical addresses for first logical addresses. The pointers comprise a pointer to a target first physical address for first logical address, and read and write the first data from or to first target physical address, respectively, where the first target physical address is located in the memory devices.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132