DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/18/2026 have been fully considered but they are not persuasive because of the following reason:
Applicant argues that:
Non-limiting support for the amendments to Claim 1 may be found at least in original Claim 3. It is believed that no art of record discloses or suggests these features.
For example, the Office Action asserts that Tsuchida describes a capacitor disposed in or on the other of the first main surface and the second main surface (Office Action, pp. 5-6). However, Fig. 3A of Tsuchida discloses that the first circuit components (including capacitor 32) disposed on principal surface 91a and the output transformers 31 and 36 do not overlap in a plan view of the module board 91 (see paragraph [0096] of Tsuchida). Therefore, Applicant respectfully disagrees with the assertion that Tsuchida discloses the claimed capacitor.
Moreover, Tsuchida does not disclose or suggest that the capacitor is connected to a signal path connecting the one end of the secondary coil and the output terminal. In Tsuchida, one end of capacitor 32 is connected to a midpoint of the first coil, and the other end is connected to ground. Tsuchida also describes a capacitor connected to a signal path linking one end of the second coil to the output terminal of the power amplifier. However, Tsuchida does not describe the placement of that capacitor (See Fig. 2 of Tsuchida). Therefore, it is believed that Tsuchida does not disclose or suggest the amended features of Claim 1.
Lyalin does not cure the deficiencies in Tsuchida. Therefore, no combination of Lyalin and Tsuchida discloses or suggests every feature recited in amended Claim 1, and amended Claim 1 is believed to be in condition for allowance together with any claim depending therefrom. Withdrawal of the rejection of Claims 1, 3-9, and 11-20 under 35 U.S.C. 103 is respectfully requested.
Examiner respectfully disagrees for the following reason:
Applicant argues that Tsuchida does not disclose or suggest that “the capacitor is connected to a signal path connecting the one end of the secondary coil and the output terminal”. However, Examiner did not rely on Tsuchida for this feature. Rather, Lyalin was relied upon to teach the claimed capacitor connection, including the limitation that the capacitor is connected to the output transformer and the limitation that the capacitor is connected to a signal path connecting one end of the secondary coil and the output terminal.
As shown in Lyalin Fig. 8, Lyalin discloses a power amplification system including transformer balun 880 and reactance compensation circuit 890. Figure 8 shows secondary coil 882 of transformer balun 880, fifth tap 888 at an end of secondary coil 882, capacitor 891 of reactance compensation circuit 890, switch 805, and 2G output node 802.
More specifically, Lyalin paragraph [0063] states that reactance compensation circuit 890 includes first reactance compensation capacitor 891 coupled between fifth tap 888 and 2G output node 802 via switch 805. Thus, capacitor 891 is connected between fifth tap 888, which is at one end of secondary coil 882, and 2G output node 802, which corresponds to the claimed output terminal. Therefore, Lyalin teaches that the capacitor is connected to a signal path connecting one end of the secondary coil and the output terminal.
Further, because fifth tap 888 is part of transformer balun 880, the capacitor 891 is also connected to the output transformer as claimed. Therefore, Lyalin teaches both “a capacitor connected to the output transformer” and the amended feature that “the capacitor is connected to a signal path connecting the one end of the secondary coil and the output terminal.” See Lyalin, Fig. 8 and paragraph [0063].
Accordingly, Applicant's argument of Tsuchida's capacitor 32 does not overcome the rejection because the Office did not rely on Tsuchida's capacitor 32 for the claimed signal-path connection. Applicant's argument addresses Tsuchida individually and does not address the actual combination relied upon in the rejection. Lyalin cures the alleged deficiency by teaching capacitor 891 coupled between an end of the secondary coil of the transformer balun and the output node.
For at least these reasons, the combination of Tsuchida and Lyalin discloses or suggests the argued limitations of amended claim 1, and the rejection of claim 1 under 35 U.S.C. 103 is maintained.
Rejection for claims 2 and 10 are also maintained for the reason set forth above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-9 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lyalin et al. (US 20200091879, hereinafter “Lyalin”) and further in view of Tsuchida et al. (US 20210111743, hereinafter “Tsuchida”).
Regarding claim 1, Lyalin discloses,
A radio frequency module (the present disclosure relates to a radio-frequency (RF) module including a packaging substrate configured to receive a plurality of components) comprising:
a power amplifier (FIG. 2 shows that the amplification system 52) that amplifies a transmission signal and includes a first amplification device and a second amplification device (the amplification system 52 includes a radio-frequency (RF) amplifier assembly 54 having one or more power amplifiers (PAs), for example, three PAs 60a-60c are depicted as forming the RF amplifier assembly 54, [0034]),
an output transformer (Fig. 8; transformer balun 880) including a first coil and a second coil (The transformer balun 880 includes a first coil 881 (e.g., a primary coil) and a second coil 882 (e.g., a secondary coil), [0061]), and a capacitor connected to the output transformer (Fig. 8 illustrates the reactance compensation circuit 890, which includes capacitors 891-89, is coupled to the transformer Balun 880),
wherein one end of the first coil is connected to an output terminal of the first amplification device (The transformer balun 880 includes a first tap 883 at a first end of the first coil 881 is coupled to transistor 842, Fig. 8 and [0061]-[0062]), another end of the first coil is connected to an output terminal of the second amplification device (The transformer balun 880 includes a second tap 884 at a second end of the first coil 881 is coupled to transistor 843, Fig. 8 and [0061]-[0062]), and one end of the second coil is connected to an output terminal of the power amplifier (The fifth tap 888 or sixth tap 889 of the second coil 882 of the transformer balun 880 are coupled, via the reactance compensation circuit 890 and a switch 805, to the 2G output node 802 or the 3G output node 803, Fig. 8 and [0061]-[0062]),
the output transformer is disposed in or on the module substrate (a module 300 can include a packaging substrate 302, and a number of components can be mounted on such a packaging substrate. For example, the power amplifier assembly 306 may include a Class-E push-pull amplifier including a transformer-based balun, [0073]) and
the capacitor is connected to a signal path connecting the one end of the second coil and the output terminal of the power amplifier (The reactance compensation circuit 890 includes a first reactance compensation capacitor 891 coupled between the fifth tap 888 and the 2G output node 802, a second reactance compensation capacitor 892 coupled between the sixth tap 889 and the 3G output node 803, Fig. 8 and [0063]).
However, Lyalin does not discloses, a module substrate including a first main surface that faces a second main surface, the output transformer is disposed closer to one of the first main surface and the second main surface than to an other of the first main surface and the second main surface, and the capacitor is disposed in or on the other of the first main surface and the second main surface, and is disposed to overlap the output transformer in a case where the module substrate is viewed in a plan view.
In the same field of endeavor, Tsuchida discloses, a module substrate including a first main surface that faces a second main surface (a radio frequency module according to an aspect of the present disclosure includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board, [0007]), the output transformer is disposed closer to one of the first main surface and the second main surface than to another of the first main surface and the second main surface (FIG. 3A-3B illustrates output transformers 31 and 36 formed (or disposed) inside of module board 91 indicated with dashed lines. output transformers 31 and 36 are formed inside of module board 91 between principal surface 91a and principal surface 91b and offset toward principal surface 91a [0113]. Note: offset towards to the principal surface 91a means its closer to 91a than to 91b), and the capacitor is disposed in or on the other of the first main surface and the second main surface (Amplifying element 11A and amplifying element 11B are disposed on principal surface 91a. The first circuit component is disposed on principal surface 91b [0188] and capacitors 32 or 37 are part of first circuit components [0172]), and is disposed to overlap the output transformer in a case where the module substrate is viewed in a plan view (in Fig. 3A illustrates in plain view capacitor 32 is on principle surface 91a overlaps transformer 31, see the drawing below)
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Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Lyalin by specifically providing a module substrate including a first main surface that faces a second main surface, the output transformer is disposed closer to one of the first main surface and the second main surface than to another of the first main surface and the second main surface, and the capacitor is disposed in or on the other of the first main surface and the second main surface, and is disposed to overlap the output transformer in a case where the module substrate is viewed in a plan view, as taught by Tsuchida for the purpose of providing a small radio frequency module that includes a difference amplifying type power amplifier, and a communication device that includes the radio frequency module [0006].
Regarding claim 4, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the output transformer is formed inside the module substrate (FIG. 3A-3B illustrates output transformers 31 and 36 formed (or disposed) inside of module board 91 indicated with dashed lines).
Regarding claim 5, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the output transformer is disposed on the first main surface, and the capacitor is disposed on the second main surface (As illustrated in FIGS. 6A and 6B, capacitors 32 and 37 are mounted on principal surface 91a of module board 91, in radio frequency module 1G according to this variation. On the other hand, output transformers 31 and 36 are mounted on principal surface 91b of module board 91, [0150]).
Regarding claim 6, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the output transformer is disposed on the second main surface, and the capacitor is disposed on the first main surface (As illustrated in FIGS. 6A and 6B, capacitors 32 and 37 are mounted on principal surface 91a of module board 91, in radio frequency module 1G according to this variation. On the other hand, output transformers 31 and 36 are mounted on principal surface 91b of module board 91, [0150]).
Regarding claim 7, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein an external connection terminal is disposed in or on the second main surface (In radio frequency module 1, external-connection terminal 150 may be disposed on principal surface 91b, [0212]), the output transformer is disposed on a surface of or inside the module substrate (FIG. 3A-3B illustrates output transformers 31 and 36 formed (or disposed) inside of module board 91 indicated with dashed lines), and is disposed closer to the first main surface than the second main surface, and the capacitor is disposed on the second main surface (As illustrated in FIGS. 6A and 6B, capacitors 32 and 37 are mounted on principal surface 91a of module board 91, in radio frequency module 1G according to this variation. On the other hand, output transformers 31 and 36 are mounted on principal surface 91b of module board 91, [0150]).
Regarding claim 8, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 7), in addition Tsuchida discloses,
wherein the first amplification device and the second amplification device are disposed on the first main surface (As illustrated in FIGS. 3A and 3B, in radio frequency module 1A according to this example, amplifying elements 11A, 11B, 12A, and 12B are mounted on principal surface 91a of module board 91, [0080]).
Regarding claim 9, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the capacitor is a surface mount device (capacitors 32 and 37 are mounted on principal surface 91a of module board 91, [0080]).
Regarding claim 11, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the power amplifier is a differential amplification type amplifier (The power amplification system 800 includes two differential bias circuits 862, 863 powered by the supply voltage, respectively coupled to the respective gates of the differential transistors 842, 843, and respectively configured to bias the differential transistors 842, 843, [0059]).
Regarding claim 12, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), further Lyalin discloses,
wherein the first amplification device is a carrier amplifier or a peak amplifier, the second amplification device is a carrier amplifier or a peak amplifier, and the power amplifier is a Doherty amplifier (FIG. 3D shows that in some embodiments, a PA can be configured as a Doherty PA. Such a Doherty PA can include amplifying transistors 64a, 64b configured to provide carrier amplification and peaking amplification of an input RF signal (RF_in) to yield an amplified output RF signal (RF_out). The input RF signal can be split into the carrier portion and the peaking portion by a splitter. The amplified carrier and peaking signals can be combined to yield the output RF signal by a combiner, [0041]). Regarding claim 13, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses, wherein the module substrate includes a ground electrode layer formed along a direction parallel to the first main surface or the second main surface, wherein in a case where the module substrate is viewed in a plan view, the ground electrode layer is not formed in a region that overlaps the output transformer (in a plan view of module board 91, ground electrode layer 95g is not formed in regions on both principal surfaces 91a and 91b, which overlap formation region 30 in which output transformers 31 and 36 are formed, but a configuration in which ground electrode layer 95g is not formed in a region on one of principal surface 91a and principal surface 91b, which overlaps formation region 30 in which output transformers 31 and 36 are formed, [0108]-[0110]).
Regarding claim 14, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the module substrate includes a low temperature co-fired ceramic (LTCC) substrate (module board 91 includes low temperature co-fired ceramics (LTCC), [0078]).
Regarding claim 15, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the module substrate includes a High temperature co-fired ceramic (HTCC) substrate ((module board 91 includes high temperature co-fired ceramics (HTCC), [0078]).
Regarding claim 16, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the module substrate includes a substrate having a redistribution layer (RDL) (module board 91 includes a redistribution layer, [0078]).
Regarding claim 17, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), in addition Tsuchida discloses,
wherein the module substrate includes a printed circuit board (module board 91 includes a printed circuit board, [0078]).
Regarding claim 18, Lyalin discloses,
A communication device (FIG. 11 depicts an example wireless device 400) comprising:
a signal processing circuit that processes a radio frequency signal (Referring to FIG. 11, power amplifiers (PAs) 420 can receive their respective RF signals from a transceiver 410 that can be configured and operated in known manners to generate RF signals to be amplified and transmitted, and to process received signals, [0076]); and the radio frequency module according to claim 1 (see, claim 1 rejection above) that transmits the radio frequency signal between the signal processing circuit and an antenna (In the example wireless device 400, outputs of the PAs 420 are shown to be matched (via respective match circuits 422) and routed to their respective duplexers 424. Such amplified and filtered signals can be routed to an antenna 416 through an antenna switch 414 for transmission, [0078]).
Regarding claim 19, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 18), further Lyalin discloses,
wherein the signal processing circuit includes a radio frequency signal processing circuit (RFIC) (Referring to FIG. 11, power amplifiers (PAs) 420 can receive their respective RF signals from a transceiver 410 that can be configured and operated in known manners to generate RF signals to be amplified and transmitted, and to process received signals, [0076]).
Regarding claim 20, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 18), further Lyalin discloses,
wherein the signal processing circuit includes a base band signal processing circuit (BBIC) (The transceiver 410 is shown to interact with a baseband sub-system 408 that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver 410, [0076]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lyalin, in view of Tsuchida and further in view of Grede et al. (US 10396720, hereinafter “Grede”).
Regarding claim 2, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), the combination of Lyalin and Tsuchida does not disclose, wherein one end of the capacitor is connected to a middle point of the first coil, and the other end of the capacitor is connected to ground.
In the same field of endeavor, Grede discloses, wherein one end of the capacitor is connected to a middle point of the first coil (The primary winding 6 of the power transformer 7 comprises a center tap 37. A network 38, which may comprise an inductor and/or a capacitor, is connected to the center tap 37, Fig. 1 and Col. 5; lines 24-27), and the other end of the capacitor is connected to ground (a capacitor to ground could be provided, Col. 5; lines 29-30).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Lyalin and Tsuchida by specifically providing wherein one end of the capacitor is connected to a middle point of the first coil, and the other end of the capacitor is connected to ground, as taught by Grede for the purpose of preventing excitation of parasitic resonances by very high harmonics and improving stability of the circuit (Col. 4; lines 1-6).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lyalin, in view of Tsuchida and further in view of Sato et al. (US 20210343662, hereinafter “Sato”).
Regarding claim 10, the combination of Lyalin and Tsuchida discloses everything claimed as applied above (see claim 1), the combination of Lyalin and Tsuchida does not disclose, wherein the capacitor is a semiconductor component.
In the same field of endeavor, Sato discloses, wherein the capacitor is a semiconductor component (Electronic components, such as a die, semiconductors, resistors, and/or capacitors are attached to the substrate of each IC being fabricated. For example, if an 8×8 array of ICs is being fabricated, then one or more dies (e.g., power supply controller integrated circuits, or switching transistors) and associated resistors, capacitors, etc. may be attached to each of the 64 module substrates of the 8×8 array, [0024]).
Therefore, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the combination of Lyalin and Tsuchida by specifically providing wherein the capacitor is a semiconductor component, as taught by Sato for the purpose of providing shielding from electromagnetic interference, and protects the electronic components of the IC from the environment [0021].
Prior Art of the Record:
The prior art made of record not relied upon and considered pertinent to
Applicant’s disclosure:
US 20210306012: A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a first power amplifier disposed on the first principal surface and configured to amplify a transmission signal in a first frequency band.
US 20180302047: A power amplifier module includes a plurality of power amplifiers and at least one switch that switches between power supply sources such that each of the plurality of power amplifiers is supplied with one of a power supply voltage according to an envelope tracking scheme or a power supply voltage according to an average power tracking scheme.
WO 2021084848: The high frequency module has a first wiring board (9) which has a first main surface and a second main surface which are mutually opposite. A second wiring board has third main and fourth main surfaces which are mutually opposite, and is separated from the first wiring board in a thickness direction of the first wiring board. A power amplifier has a pad electrode for an output.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GOLAM SOROWAR whose telephone number is (571)270-3761. The examiner can normally be reached Mon-Fri: 8:30AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles Appiah can be reached at (571) 272-7904. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GOLAM SOROWAR/Primary Examiner, Art Unit 2641
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